CN115940595B - Output drive circuit for power module and drive circuit system using the same - Google Patents
Output drive circuit for power module and drive circuit system using the sameInfo
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- CN115940595B CN115940595B CN202111232034.XA CN202111232034A CN115940595B CN 115940595 B CN115940595 B CN 115940595B CN 202111232034 A CN202111232034 A CN 202111232034A CN 115940595 B CN115940595 B CN 115940595B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
An output driving circuit uses a thinner oxide layer thickness process for a high-voltage transistor, and through the design of a front-end circuit of the high-voltage transistor, the voltage-withstanding degree between a gate electrode and a source electrode of the high-voltage transistor can be adjusted downwards, but the voltage-withstanding degree between a drain electrode and the source electrode can reach 25 volts as well, and the characteristic specification of an output end cannot be influenced.
Description
Technical Field
The present invention relates to an output driving circuit for a power device and a driving circuit system using the same, and more particularly, to an output driving circuit capable of having a small circuit area (or a large driving current) and having a thin oxide layer of a high voltage transistor, and a driving circuit system using the same.
Background
MOSFET, IGBT, SJ (super junction), siC or GaN, are currently widely used in power electronic systems, and a key to controlling the power component on or off is to drive a chip. For optimum efficiency, the power device specifications are selected, for example, 25V/40A or 200V/5A power device can be selected under 1KW requirement, and the corresponding required driving chip voltage and driving current specifications are different. If the driving capability of the driving chip is insufficient, there are problems of system efficiency decrease and power component temperature rise (chip junction temperature TJ rise).
Referring to fig. 1, fig. 1 is a schematic diagram of a conventional power circuit system. In the power circuit system 1, two power transistors HQ, LQ, a driving chip 11, an external diode BD and a capacitor C. One end of the driving chip 11 is connected to the system voltage VCC to obtain a supply voltage, and the driving chip 11 receives the input signals HIN, LIN and outputs driving signals HO and LO to control the power transistors HQ, LQ to be turned on or turned off. The driving chip 11, the logic control circuit 111 and two output driving circuits 112, 113, wherein the logic control circuit 111 receives the input signals HIN, LIN and generates the switch control signals to the output driving circuits 112, 113, so that the output driving circuits 112, 113 are respectively used for outputting the driving signals HO and LO.
Since parasitic gate capacitors of the power transistors HQ and LQ need to be charged to be driven, the driving current values of the driving signals HO and LO outputted from the output driving circuits 112 and 113 must be large enough to smoothly turn on the power transistors HQ and LQ. Since the driving current value is related to the area of the transistors of the driving circuits 112 and 113, an increase in area has been conventionally employed to obtain a sufficient driving current value, but the increase in area causes a chip cost increase and also limits the packaging of the chip.
Fig. 2 is a schematic diagram of a prior art output driving circuit, and the circuit architecture of the driving circuits 112, 113 can refer to fig. 2. An output driving circuit 2, amplifying stage modules 21, 22 and an output stage module 23. The amplifier stage modules 21, 22 are used for amplifying the switch control signal v_in, wherein the amplifier stage module 21 is composed of amplifiers A4 to A6 connected IN series, and the amplifier stage module 22 is composed of amplifiers A1 to A3 connected IN series. When the system voltage VCC is generally 10-20 v, the high voltage transistors hv_pmos and hv_nmos of the output stage module 23 must be three-terminal high voltage devices capable of withstanding voltages above 20 v, so as to generate the driving signal DRVOUT with high current value to the parasitic gate stage capacitor COUT.
In order to improve the withstand voltage, the high voltage transistors hv_pmos and hv_nmos use a material with a larger distance, a larger layer thickness (deep), but the saturation currents of the high voltage transistors hv_pmos and hv_nmos are smaller than those of the low voltage transistors hv_pmos and hv_nmos with the same width, so in order to further increase the driving current, this makes the high voltage transistors hv_pmos and hv_nmos have to increase the area thereof.
Disclosure of Invention
According to the purpose of the invention, the embodiment of the invention provides an output driving circuit, which is provided with a pair of high-voltage transistors, a voltage clamping circuit, a switching control signal receiving the switching control signal and outputting a voltage difference value not lower than the system voltage, a voltage switching control signal receiving the switching control signal, a voltage switching circuit receiving the switching control signal and outputting a voltage difference value not lower than the switching control signal, and a voltage switching circuit receiving the switching control signal, wherein the voltage withstanding between a gate electrode stage and a source electrode of the first high-voltage transistor and an N-type second high-voltage transistor are respectively a first limiting voltage and a second limiting voltage, and the first limiting voltage and the second limiting voltage are respectively related to oxide layer thicknesses of the gate electrode of the first high-voltage transistor and the second high-voltage transistor.
Alternatively, the first and second limiting voltages may be the same as each other, i.e., the oxide thickness of the gate of the first high voltage transistor is the same as the oxide thickness of the gate of the second high voltage transistor.
According to the purpose of the invention, the embodiment of the invention provides a driving circuit system, the output driving circuit and a logic control circuit, wherein the logic control circuit is electrically connected with the output driving circuit to provide the switch control signal.
Alternatively, the driving circuitry may be integrated into a single chip to form the driving chip.
In summary, the output driving circuit provided in the embodiments of the present invention has a larger driving current compared to the conventional output driving circuit with the same area, or has a smaller area compared to the same driving current.
For a further understanding of the technology, means, and effects of the present invention, reference should be made to the following detailed description and accompanying drawings so that the objects, features, and concepts of the invention may be fully and specifically understood. However, the following detailed description and drawings are merely for purposes of reference and illustration of implementations of the invention and are not intended to limit the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention to those skilled in the art, and are incorporated into and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic diagram of a generally conventional power supply circuit system.
Fig. 2 is a schematic diagram of a prior art output drive circuit.
Fig. 3 is a schematic diagram of an output driving circuit according to an embodiment of the invention.
Fig. 4 is a schematic diagram of an output driving circuit according to another embodiment of the invention.
Fig. 5 is a schematic diagram of an output driving circuit according to another embodiment of the invention.
Fig. 6 is a schematic diagram of an output driving circuit according to another embodiment of the present invention.
The symbols marked IN the drawings are described as A1 power supply circuit system, a 11 driving chip, a 111 logic control circuit, 112, 113, 2-6 output driving circuits, 21, 22 amplifying stage modules, 23 output stage modules, 31, 41, 51, 61 voltage clamping circuits, 32, 42, 52, 62 conversion circuits, 33, 43, 53, 63 high-voltage transistor pairs, A1-A6, G1-G5 amplifiers, BD diodes, C capacitors, CS current sources, COUT parasitic gate capacitors, INV1, INV2 inverters, HIN, LIN input signals, HO, LO, DRVOUT driving signals, HQ, LQ power transistors, HV_PMOS, HV_NMOS high-voltage transistors, Q1-Q7 transistors, R1 resistors, V_IN switch control signals, VCC system voltages, VL limiting voltages and ZD zener diodes.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In addition, the practice of the exemplary embodiments is only one of the implementation of the design concept of the present invention, and the following examples are not intended to limit the present invention.
The embodiment of the invention provides an innovative technical scheme which can improve the output current of a driving circuit system and reduce the area of a circuit so as to obtain great related benefits. In the embodiment of the invention, the high voltage transistor uses a thinner oxide thickness process, for example, the oxide thickness (gate oxide thickness, hereinafter referred to as oxide thickness) of the high voltage transistor with a typical withstand voltage of 25V is about(90 Nm) but the oxide layer thickness of the low voltage transistor withstanding 5V is about(12 Nm) or so. The oxide layer thickness of the high-voltage transistor adopted by the embodiment of the invention is thinner, but the voltage-resistant degree between the gate electrode and the source electrode of the high-voltage transistor can be downwards adjusted by the design of the front-end circuit of the high-voltage transistor, but the voltage-resistant degree between the drain electrode and the source electrode can reach 25 volts as well, and the characteristic specification of the output end can not be influenced.
Further, taking the voltage-withstanding degree between the gate and the source as 5 volts and the system voltage as 15 volts as an example, the front-end circuit connected to the gate of the N-type high-voltage transistor in the high-voltage transistor may be a conversion circuit with the highest output voltage of 5 volts, and the front-end circuit connected to the gate of the P-type high-voltage transistor in the high-voltage transistor may be a voltage clamping circuit for clamping the voltage of the gate of the P-type high-voltage transistor in the high-voltage transistor to be not lower than 10 volts. In this way, a high voltage transistor with a thinner oxide thickness can be protected. Meanwhile, under the condition of the same channel width, the saturation current value of the high-voltage transistor with the thinner oxide layer thickness is three times that of the high-voltage transistor with the common oxide layer thickness, so that the technical scheme of the embodiment of the invention can reduce the circuit area and increase the driving current.
Next, referring to fig. 3 of the present invention, fig. 3 is a schematic diagram of an output driving circuit according to an embodiment of the present invention. The output driving circuit 3 is used in driving circuitry (the driving circuitry may be an integrated chip, but is not limited thereto) for controlling the on and off of the power transistors outside the driving circuitry. The output driving circuit 3, the voltage clamping circuit 31, the converting circuit 32 and the high voltage transistor pair 33, wherein the high voltage transistor pair 33, the high voltage transistors hv_pmos (P-type high voltage transistor) and hv_nmos (N-type high voltage transistor). The source of the high voltage transistor hv_pmos is electrically connected to the system voltage VCC, the gate of the high voltage transistor hv_pmos is electrically connected to the output of the voltage clamp 31, and the drain of the high voltage transistor hv_nmos is electrically connected to the drain of the high voltage transistor hv_pmos. The gate of the high voltage transistor hv_nmos is electrically connected to the output of the conversion circuit 32, the source of the high voltage transistor hv_nmos is electrically connected to the ground voltage, and the drain of the high voltage transistor hv_nmos and the drain of the high voltage transistor hv_pmos are electrically connected to the gate of the power transistor outside the driving circuitry to output the driving signal DRVOUT, where the current of the driving signal DRVOUT is used to charge and discharge the parasitic gate capacitor COUT of the power transistor.
The conversion circuit 32 is configured to receive the switch control signal v_in and amplify the switch control signal v_in, and the conversion circuit 32 may be an inverting or non-inverting amplifying or buffering circuit, or may be a conversion circuit with logic gates or other circuit components, and the invention is not limited thereto. The converting circuit 32 receives the limiting voltage VL as the supply voltage (or a voltage lower than the limiting voltage VL may be received as the supply voltage), and the maximum voltage value of the amplified switch control signal v_in does not exceed the limiting voltage VL, wherein IN this embodiment, the converting circuit 32 connects the plurality of amplifiers G1, G2 and G3 IN series, and the signal output by each of the amplifiers G1, G2 and G3 does not exceed the limiting voltage VL, for example, 5 volts. In the embodiment of the invention, the high voltage transistor HV_NMOS is selected to use a thinner oxide layer thickness, the voltage resistance between the drain and the source is still high, for example 25V, and the voltage resistance between the gate and the source is a limiting voltage VL (the limiting voltage VL is related to the oxide layer thickness), for example, the oxide layer thickness is aboutWhen (12 nm) is around, the limit voltage VL is 5 volts. Thus, the voltage difference between the gate and the source of the high voltage transistor hv_nmos does not exceed the limit voltage VL, so that the high voltage transistor hv_nmos is protected.
The voltage clamp circuit 31 receives the switch control signal v_in and the system voltage VCC, wherein the system voltage is between 10 to 20 volts, for example 15 volts, and the voltage clamp circuit 31 uses the system voltage VCC as the supply voltage. In the embodiment of the invention, the high voltage transistor HV_PMOS also uses a thinner oxide layer thickness, the voltage resistance between the drain and the source is still high, such as 25V, and the voltage resistance between the gate and the source is a limiting voltage VL (the limiting voltage VL is related to the oxide layer thickness), such as the oxide layer thickness is aboutWhen (12 nm) is around, the limit voltage VL is 5 volts. The voltage clamping circuit 31 is designed to output a clamping voltage (e.g., 10 volts) not lower than the voltage value VCC-VL to prevent the voltage difference between the gate and the source of the high voltage transistor hv_pmos from exceeding the voltage withstanding degree between the gate and the source of the high voltage transistor hv_pmos, thereby protecting the high voltage transistor hv_pmos. Oxide thickness of the high voltage transistors HV_PMOS and HV_NMOS is aboutWhen the voltage is about (12 nanometers), the output currents of the high-voltage transistors HV_PMOS and HV_NMOS in the embodiment are three times that of the high-voltage transistors with the common oxide layer thickness, so that the technical scheme of the embodiment of the invention can be used for really reducing the circuit area and increasing the driving current.
Referring to fig. 4, fig. 4 is a schematic diagram of an output driving circuit according to another embodiment of the invention. In this embodiment, the output driving circuit 4, the voltage clamping circuit 41, the switching circuit 42 and the high voltage transistor pair 43 are the same as the switching circuit 32 and the high voltage transistor pair 33 in fig. 3, and therefore are not described in detail.
The voltage clamp 41, the amplifiers G4, G5, the N-type transistor Q1, the resistor R1, and the zener diode ZD. The amplifiers G4 and G5 are connected IN series, and the amplifier G4 receives the switch control signal v_in, and the amplifier G5 outputs the switch control signal v_in amplified by the amplifiers G4 and G5, and the maximum voltage value of the amplified switch control signal v_in does not exceed the limit voltage VL, for example, 5 volts, because the amplifiers G4 and G5 receive the limit voltage VL as the supply voltage. The gate of the transistor Q1 is electrically connected to the amplifier G5 to receive the amplified switch control signal v_in, the source of the transistor Q1 is electrically connected to the ground voltage, and the drain of the transistor Q1 is electrically connected to one end of the resistor R1. The cathode of the zener diode ZD is electrically connected to the system voltage VCC, and the anode of the zener diode ZD is electrically connected to the other end of the resistor R1 and the gate of the high voltage transistor hv_pmos.
Because of the existence of the zener diode ZD, once the voltage of the gate of the high voltage transistor hv_nmos is smaller than VCC-V ZD, the voltage of the gate of the high voltage transistor hv_pmos is clamped at VCC-V ZD, where V ZD represents the breakdown voltage of the zener diode ZD. By selecting the breakdown voltage V ZD of the zener diode ZD to be less than or equal to the limit voltage VL, the voltage difference between the gate and the source of the high voltage transistor hv_pmos can not exceed the limit voltage VL, so that the high voltage transistor hv_pmos is protected.
Referring to fig. 5, fig. 5 is a schematic diagram of an output driving circuit according to another embodiment of the invention. In this embodiment, the output driving circuit 5, the voltage clamping circuit 51, the switching circuit 52 and the high voltage transistor pair 53, wherein the switching circuit 52 and the high voltage transistor pair 53 are the same as the switching circuit 32 and the high voltage transistor pair 33 of fig. 3, and therefore are not described in detail. The voltage clamp circuit 51 includes amplifiers G4, G5, N-type transistors Q1 and resistors R1, and a plurality of transistors Q2, Q3, Q4 serving as diodes. The difference between this embodiment and fig. 4 is that a plurality of transistors Q2, Q3, Q4 are used as diodes instead of the zener diode ZD, wherein the drain of the transistor Q2 is electrically connected to the system voltage VCC, and the source of the transistor Q4 is electrically connected to the other end of the resistor R1 and the gate of the high voltage transistor hv_pmos.
Due to the presence of the plurality of transistors Q2, Q3, Q4 used as diodes, once the voltage at the gate of the high voltage transistor HV_NMOS is less than VCC-V th1-Vth2-Vth3, the voltage at the gate of the high voltage transistor HV_PMOS is clamped at VCC-V th1-Vth2-Vth3, where V th1、Vth2、Vth3 represents the threshold voltages of the transistors Q2, Q3, Q4. By selecting the sum V th1+Vth2+Vth3 of the threshold voltages of the transistors Q2, Q3, Q4 to be less than or equal to the limit voltage VL, the voltage difference between the gate and the source of the high voltage transistor hv_pmos can be kept from exceeding the limit voltage VL, so that the high voltage transistor hv_pmos is protected.
Referring to fig. 6, fig. 6 is a schematic diagram of an output driving circuit according to another embodiment of the invention. The output driving circuit 6, the voltage clamping circuit 61, the switching circuit 62 and the high voltage transistor pair 63, and the high voltage transistor pair 63 is the same as the high voltage transistor pair 33 of fig. 3, and thus will not be described in detail. Unlike the embodiment of fig. 3, the inverter circuit 62, an inverter INV1, outputs a voltage having a value not exceeding the limit voltage VL at maximum, for example, 5 volts. The input end of the inverter INV1 receives the switch control signal v_in, and the output end of the inverter INV1 is used for outputting the inverted switch control signal v_in to the gate electrode of the high voltage transistor hv_nmos.
The voltage clamp 61 includes transistors Q1 to Q7, an inverter INV2, a resistor R1 and a current source CS, wherein the transistors Q1 and Q2 are N-type transistors and the transistors Q3 to Q7 are P-type transistors. The sources of the transistors Q1 and Q2 are electrically connected to the ground voltage, the gates of the transistors Q1 and Q2 are electrically connected to the output and input terminals of the inverter INV2, respectively, and the input terminal of the inverter INV2 receives the switch control signal v_in. The two ends of the resistor R1 are respectively and electrically connected with the system voltage VCC and the gate electrodes of the transistors Q3 and Q4, and the two ends of the current source CS are respectively and electrically connected with the grounding voltage and one ends of the gate electrodes of the transistors Q3 and Q4. The drains of the transistors Q3 and Q4 are electrically connected to the drains of the transistors Q1 and Q2, respectively, and the sources of the transistors Q3 and Q4 are electrically connected to the drains 4 of the transistors Q5 and Q6, respectively. The sources of the transistors Q5 and Q6 receive the system voltage VCC, and the gates of the transistors Q5 and Q6 are electrically connected to the sources of the transistors Q3 and Q4, respectively. The source of the transistor Q7 receives the system voltage VCC, the drain of the transistor Q7 is electrically connected to the source of the transistor Q4 and the gate of the high voltage transistor HV_PMOS, and the gate of the transistor Q7 is electrically connected to the gate of the transistor Q2.
Through the above connection, the transistors Q1 to Q7 and the resistor R1 are configured as a level converter (LEVEL SHIFTER) so that the voltage on the gate of the high voltage transistor hv_nmos is VCC-i×r1+v GSQ4, where V GSQ4 is the voltage between the gate and the source of the transistor Q4, and I is the current provided by the current source CS. By proper threshold bias design and resistor selection, the voltage difference between the gate and the source of the high voltage transistor HV_PMOS can be kept from exceeding the limit voltage VL by making I_R1-V GSQ4 smaller than or equal to the limit voltage VL, so that the high voltage transistor HV_PMOS can be protected.
Incidentally, although the above description has been given by taking the example in which the limit voltages VL of the high voltage transistors hv_pmos and hv_nmos are the same, the present invention is not limited thereto. In a specific application, the limiting voltages of the high voltage transistors hv_pmos and hv_nmos are VL1 and VL2, respectively, and the limiting voltages VL1 and VL2 are different from each other. At this time, according to the above inventive concept, the switching circuit may only output a signal not higher than the limit voltage VL2 to control the on and off of the high voltage transistor hv_nmos, and the voltage clamping circuit may only output a signal not lower than the system voltage VCC minus the voltage difference (VCC-VL 1) of the limit voltage VL1 to control the on and off of the high voltage transistor hv_pmos.
In addition, the embodiment of the invention further provides a driving circuit system, a logic control circuit and at least one output driving circuit, wherein the logic control circuit is electrically connected with the output driving circuit to provide a switch control signal to the output driving circuit, and the output driving circuit is used for generating a driving signal DRVOUT according to the switch control signal to a power component (for example, a power transistor) electrically connected with the driving circuit system. The output drive circuit may be implemented in any of the embodiments described above, and the drive circuitry may be used in motor systems, charging posts, chargers, or other applications requiring high power.
In view of the foregoing, embodiments of the present invention provide an output driving circuit for power device applications, where a thin oxide layer is used for a high voltage transistor of the output driving circuit, and a switching circuit and a voltage clamping circuit are correspondingly provided to protect the high voltage transistor. The output driving circuit can output a higher driving current due to the thinner oxide layer thickness, or the area of the output driving circuit can be reduced under the same driving current. Therefore, the technical scheme of the invention can reduce the manufacturing cost or limit the packaging area, and even can make trade-off between the area and the driving current so as to obtain a better product as a better solution for the application end of the power component.
It is understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
Claims (10)
1. An output drive circuit, the drive circuit comprising:
The high-voltage transistor pair is provided with a first high-voltage transistor of a P type and a second high-voltage transistor of an N type, wherein a source electrode and a drain electrode of the first high-voltage transistor are respectively and electrically connected with a system voltage and a drain electrode of the second high-voltage transistor, a source electrode of the second high-voltage transistor is electrically connected with a grounding voltage, the drain electrodes of the first high-voltage transistor and the second high-voltage transistor are used for outputting driving signals, withstand voltages between gate electrodes and source electrodes of the first high-voltage transistor and the second high-voltage transistor are limiting voltages, and the limiting voltages are related to oxide layer thicknesses of the gate electrodes of the first high-voltage transistor and the second high-voltage transistor;
A voltage clamping circuit electrically connected to the gate of the first high voltage transistor, receiving a switch control signal and outputting a first signal not lower than the voltage difference of the system voltage minus the limiting voltage to control the on and off of the first high voltage transistor, and
And the conversion circuit is electrically connected with the gate electrode of the second high-voltage transistor, receives the switch control signal and outputs a second signal which does not exceed the limit voltage to control the on and off of the second high-voltage transistor.
2. The output driving circuit according to claim 1, wherein the plurality of first amplifiers are connected in series, receive the limiting voltage as a supply voltage thereof, and amplify the switch control signal to transmit the amplified switch control signal to a gate of the second high voltage transistor.
3. The output drive circuit of claim 2, wherein the voltage clamp circuit further comprises:
the first transistor is connected with the first amplifier in series;
The second amplifiers receive the limiting voltage as a supply voltage and amplify the switch control signals to transmit the amplified switch control signals to the gate of the first transistor, the source of the first transistor is electrically connected with the grounding voltage, the drain of the first transistor is electrically connected with one end of the resistor, the cathode of the zener diode is electrically connected with the system voltage, and the anode of the zener diode is electrically connected with the other end of the resistor and the gate of the high-voltage transistor.
4. The output driving circuit according to claim 2, wherein a plurality of second amplifiers, a first transistor, a resistor, and a plurality of second transistors used as diodes are connected in series, wherein the plurality of second amplifiers receive the limiting voltage as its supply voltage and amplify the switch control signal to transmit the amplified switch control signal to a gate electrode of the first transistor, a source electrode of the first transistor is electrically connected to the ground voltage, a drain electrode of the first transistor is electrically connected to one end of the resistor, the plurality of second transistors are connected in series with each other, a drain electrode of one of the plurality of second transistors is electrically connected to the system voltage, and a source electrode of the other of the plurality of second transistors is electrically connected to the other end of the resistor and the gate electrode of the high-voltage transistor.
5. The output driver circuit of claim 1, wherein a first inverter has an input receiving the switch control signal and an output for outputting the inverted switch control signal to a gate of the second high voltage transistor.
6. The output driving circuit as recited in claim 5, wherein the voltage clamp circuit is a level shifter.
7. The output driver circuit of claim 1, wherein the oxide thickness of the gate of the first high voltage transistor and the second high voltage transistor is 12 nanometers, the limiting voltage is 5 volts, and the system voltage is 15 volts.
8. An output drive circuit, the drive circuit comprising:
The high-voltage transistor pair is provided with a first high-voltage transistor and a second high-voltage transistor, wherein the first high-voltage transistor is provided with a P type, the source electrode and the drain electrode of the first high-voltage transistor are respectively and electrically connected with a system voltage and the drain electrode of the second high-voltage transistor, the source electrode of the second high-voltage transistor is electrically connected with a grounding voltage, the drain electrodes of the first high-voltage transistor and the second high-voltage transistor are used for outputting driving signals, the voltage resistances between the gate electrodes and the source electrodes of the first high-voltage transistor and the second high-voltage transistor are respectively a first limiting voltage and a second limiting voltage, and the first limiting voltage and the second limiting voltage are respectively related to the oxide layer thicknesses of the gate electrodes of the first high-voltage transistor and the second high-voltage transistor;
A voltage clamping circuit electrically connected to the gate of the first high voltage transistor, receiving a switch control signal and outputting a first signal not lower than the voltage difference of the system voltage minus the first limit voltage to control the on and off of the first high voltage transistor, and
And the conversion circuit is electrically connected with the gate electrode of the second high-voltage transistor, receives the switch control signal and outputs a second signal which does not exceed the second limiting voltage to control the on and off of the second high-voltage transistor.
9. A drive circuitry, the drive circuitry comprising:
at least one output drive circuit as claimed in one of claims 1 to 8, and
And the logic control circuit is electrically connected with the output driving circuit to provide the switch control signal.
10. The drive circuitry of claim 9, wherein the drive circuitry is integrated into a single chip.
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| TW110132957 | 2021-09-06 | ||
| TW110132957A TW202312659A (en) | 2021-09-06 | 2021-09-06 | Output driving circuit for power devices and driving circuit system using the same |
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| CN115940595A CN115940595A (en) | 2023-04-07 |
| CN115940595B true CN115940595B (en) | 2025-09-23 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103427603A (en) * | 2012-05-22 | 2013-12-04 | 通嘉科技股份有限公司 | Ultra-high pressure assembly and method of operating an ultra-high pressure assembly |
| CN111162665A (en) * | 2020-02-05 | 2020-05-15 | 电子科技大学 | A fully integrated high-side driver circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510774B (en) * | 2009-03-03 | 2010-10-13 | 中国航天时代电子公司第七七一研究所 | Mixing voltage output circuit |
| TWI465040B (en) * | 2011-03-08 | 2014-12-11 | Etron Technology Inc | Output stage circuit for outputting a driving current varying with a process |
| CN102709324B (en) * | 2012-06-06 | 2014-12-10 | 苏州博创集成电路设计有限公司 | Low-power-consumption and high-voltage driving circuit and two-way P-type switching tube used by same |
| CN103841707B (en) * | 2012-11-26 | 2015-09-09 | 硕颉科技股份有限公司 | Load driver associated with light-emitting diodes |
| JP6565162B2 (en) * | 2014-10-28 | 2019-08-28 | セイコーエプソン株式会社 | Circuit device and electronic device |
| US10587262B1 (en) * | 2019-03-01 | 2020-03-10 | Infineon Technologies Austria Ag | DV/DT self-adjustment gate driver architecture |
-
2021
- 2021-09-06 TW TW110132957A patent/TW202312659A/en unknown
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103427603A (en) * | 2012-05-22 | 2013-12-04 | 通嘉科技股份有限公司 | Ultra-high pressure assembly and method of operating an ultra-high pressure assembly |
| CN111162665A (en) * | 2020-02-05 | 2020-05-15 | 电子科技大学 | A fully integrated high-side driver circuit |
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