CN115966166B

CN115966166B - Resolution control method, device and storage medium

Info

Publication number: CN115966166B
Application number: CN202211659637.2A
Authority: CN
Inventors: 冯禹; 许李尚
Original assignee: Hangzhou Hikvision Digital Technology Co Ltd
Current assignee: Hangzhou Hikvision Digital Technology Co Ltd
Priority date: 2022-12-22
Filing date: 2022-12-22
Publication date: 2025-08-01
Anticipated expiration: 2042-12-22
Also published as: CN115966166A

Abstract

The application provides a resolution control method, a resolution control device and a storage medium, relates to the technical field of display, and can be applied to an LED (light-emitting diode) splice controller. The method comprises the steps of obtaining preset effective display widths and preset effective display heights of one or more output interfaces of a video source, determining target resolution corresponding to each output interface in a resolution database according to the preset effective display widths and the preset effective display heights of each output interface, wherein the resolution database comprises at least one resolution corresponding to a standard clock, the standard clock is a clock in the standard resolution, one standard clock corresponds to multiple resolutions, and sending the target resolution corresponding to each output interface to the video source so that the video source outputs video images according to the target resolution corresponding to each output interface. The method is suitable for the spelling control display process and is used for solving the compatibility problem between the video source and the spelling controller.

Description

Resolution control method, device and storage medium

Technical Field

The present application relates to the field of display technologies, and in particular, to a resolution control method, a resolution control device, and a storage medium.

Background

A light emitting diode (L IGHT EMITT ING) tiled display system includes a video source, a tiled controller connected to the video source, and one or more LED display assemblies connected to the tiled controller.

The video source may output a plurality of video images. The spelling controller can splice a plurality of video images output by the video source into one video image and divide the video image into a plurality of video images, and the divided video images are respectively sent to one or a plurality of LED display components. Each LED display assembly can display the video images received by the LED display assembly, and the video images displayed by one or more LED display assemblies are combined together to form a video image spliced by the splice controller.

Because the final display width and height of each LED display assembly are designed according to actual requirements, the resolution of the LED display assemblies is also various, and the conventional display method can only scale the effective width and height of the video image output by the video source to a certain extent, and the scaling can cause the loss of the content of the video image, especially when the scaling is large. In order to keep the content of the video image displayed by the one or more LED display modules intact, the mosaic needs to adjust the resolution of the video image output by the video source.

However, the scheme of adjusting resolution of video images output by a video source by using a spelling controller has compatibility problem.

Disclosure of Invention

Based on the technical problems, the application provides a resolution control method, a resolution control device and a storage medium, which can generate a set of resolutions (detailed time sequences) meeting clocks in standard resolutions for each potential display wide high frame rate (W is H P/I FPS) and send the generated resolutions to a video source, thereby controlling the video source to automatically output video images according to the resolutions meeting the clocks in the standard resolutions, and avoiding compatibility problems.

The application provides a resolution control method, which is applied to a jigsaw controller, wherein the jigsaw controller is connected with a video source, the method comprises the steps of obtaining preset effective display widths and preset effective display heights of one or more output interfaces of the video source, determining target resolutions corresponding to each output interface in a resolution database according to the preset effective display widths and preset effective display heights of each output interface, wherein the resolution database comprises resolutions corresponding to at least one standard clock, the standard clock is a clock in the standard resolutions, the standard clock corresponds to multiple resolutions, and sending the target resolutions corresponding to each output interface to the video source so that the video source outputs video images according to the target resolutions corresponding to each output interface.

It will be appreciated that the mosaic is typically configured to preferentially guarantee compatibility with standard clocks in standard resolutions, which may not be supported by the mosaic when the video source outputs video images with non-standard clocks in non-standard resolutions, resulting in compatibility problems. The resolution control method provided by the application can be used for selecting the target resolution corresponding to each output interface from a plurality of resolutions corresponding to the standard clock based on the preset effective display width and the preset effective height of one or more output interfaces of the video source, controlling the video source to output video images from one or more output interfaces according to the target resolutions corresponding to the video source, and enabling the one or more target resolutions to meet the standard clock, so that the compatibility problem is avoided, and the universality of the spelling control display scheme is improved.

Optionally, the effective width of the target resolution corresponding to any one output interface is larger than or equal to the preset effective display width of the output interface, and the effective height of the target resolution corresponding to any one output interface is larger than or equal to the preset effective display height of the output interface.

Optionally, the method further comprises obtaining a preset frame rate of one or more output interfaces of the video source, obtaining at least one initial standard clock, and generating a resolution database based on the at least one initial standard clock and the preset frame rate of the one or more output interfaces of the video source.

In one possible implementation manner, acquiring at least one initial standard clock comprises determining a plurality of candidate clocks from a plurality of initial clocks according to a preset sequence according to preset clock stepping precision, wherein the clock stepping precision is used for indicating the minimum interval of the candidate clocks selected from the initial clocks according to the preset sequence, and selecting a clock overlapped with the clock in the standard resolution from the plurality of candidate clocks as the standard clock.

In one possible implementation, the at least one standard clock includes a first standard clock, and the one or more output interfaces include a first output interface, and a preset frame rate of the first output interface is a first frame rate. Generating a resolution database based on a plurality of standard clocks and a preset frame rate of one or more output interfaces of a video source, including dividing a first standard clock by a first frame rate to obtain a first area, performing one or more factorization of the first area, each time the first area is decomposed into two factors, each time factorization, taking one of the two factors obtained by factorization as a maximum width, the other one of the two factors obtained by factorization as a maximum height, determining an effective width according to the maximum width, determining an effective height according to the maximum height, and generating a resolution in the resolution database based on the maximum width, the maximum height, the effective width, and the effective height.

Optionally, the one or more output interfaces comprise a first output interface, and after determining the target resolution corresponding to each output interface according to the resolution database, the preset effective display width and the preset effective display height of each output interface, the method further comprises generating resolution information of the first output interface according to the target resolution corresponding to the first output interface, wherein the resolution information of the first output interface comprises the target resolution corresponding to the first output interface. The method comprises the step of sending the target resolution corresponding to each output interface to a video source, wherein the step of sending the resolution information of the first output interface to the video source.

Optionally, when the effective width or the effective height in the target resolution of the first output interface is smaller than 4096, generating the resolution information of the first output interface according to the target resolution corresponding to the first output interface includes generating extended display identification data EDID of the first output interface according to the target resolution corresponding to the first output interface, the EDID of the first output interface includes the target resolution corresponding to the first output interface, and the resolution information of the first output interface includes the EDID of the first output interface.

Optionally, when the effective width or the effective height in the target resolution of the first output interface is greater than or equal to 4096, generating the resolution information of the first output interface according to the target resolution corresponding to the first output interface includes generating second generation display identification data DISPLAYID of the first output interface according to the target resolution corresponding to the first output interface, DISPLAYID of the first output interface includes the target resolution corresponding to the first output interface, and the resolution information of the first output interface includes DISPLAYID of the first output interface.

It should be appreciated that the 18 byte parameter bit width of the detail timing in EDID supports a maximum effective width and maximum effective height of the transmission of only 4095, which cannot be adapted to any resolution above 4 k. In the resolution control method provided by the application, when the effective width or the effective height of the target resolution corresponding to the generated output interface is larger than or equal to 4096, the target resolution can be sent to the video source by adopting the VII type detailed time sequence description with the parameter bit width of 20 bytes in DISPALYID, so that the parameter bit width limit of the EDID is broken through, and the universality of the resolution control scheme is improved.

Optionally, the method further comprises multiplying the at least one initial standard clock by a preset coefficient to obtain at least one near standard clock, wherein the preset coefficient is positive, and generating a near standard clock resolution database based on the at least one near standard clock and a preset frame rate of one or more output interfaces of the video source.

Optionally, the one or more output interfaces comprise a first output interface, and the method further comprises determining the target resolution corresponding to the first output interface in the near-standard clock resolution database according to a preset effective display width and a preset effective display height of the first output interface when the resolution database does not comprise the target resolution corresponding to the first output interface.

It should be understood that the clock is used to express the total number of pixels contained in the video image per unit time. When the clock of the video source for outputting the video image is the standard clock supported by the spelling controller, the number of pixels output by the video source in unit time is matched with the number of pixels output by the spelling controller in unit time, so that the problem of compatibility between the video source and the spelling controller is avoided. When the clock of the video source for outputting the video image is the preset coefficient times of the standard clock supported by the spelling controller, the spelling controller can perform corresponding operations such as delay output or advance output on the video image output by the video source according to the preset coefficient, and can also achieve the mutual matching of the number of pixels output in unit time, so that the compatibility problem between the video source and the spelling controller is avoided. In the resolution control method provided by the application, when the target resolution cannot be selected from the resolution database generated by the standard clock, the target resolution is selected from the near standard clock resolution database generated by the near standard clock, so that the compatibility problem between the video source and the spelling controller is avoided, the variety supporting the preset effective display width and the preset effective display height can be increased, and the universality of the spelling control display scheme is improved.

For example, taking the standard clock supported by the jigsaw as a, and taking the clock in the target resolution corresponding to the first output interface as 0.5A as an example, the jigsaw can output a video image at a certain moment, and the video image same as the moment is output in the next second of the moment, namely, the video image output by the video source is delayed to be output so as to be matched with the clock of 0.5A of the video source, thereby avoiding the compatibility problem.

In a second aspect, the present application provides a resolution control apparatus for connection to a video source, the apparatus comprising respective modules for use in the method of the first aspect described above.

In a third aspect, the application provides a resolution control apparatus comprising a processor and a memory, the memory storing instructions executable by the processor, the processor being configured to cause the resolution control apparatus to implement the method of the first aspect described above when the instructions are executed.

In a fourth aspect, the present application provides a computer program product for, when run on resolution control means, causing the resolution control means to perform the steps of the related method of the first aspect described above, to carry out the method of the first aspect described above.

In a fifth aspect, the application provides a readable storage medium comprising software instructions which, when run in a resolution control device, cause the resolution control device to implement the method of the first aspect described above.

In a sixth aspect, the application provides a mosaic display system, which comprises a video source and a mosaic controller, wherein the video source is connected with the mosaic controller, the mosaic controller is used for acquiring preset effective display widths and preset effective display heights of one or more output interfaces of the video source, determining target resolutions corresponding to each output interface in a resolution database according to the preset effective display widths and preset effective display heights of each output interface, the resolution database comprises resolutions corresponding to at least one standard clock, the standard clock is a clock in the standard resolutions, one standard clock corresponds to a plurality of resolutions, the target resolutions corresponding to each output interface are sent to the video source, and the video source is used for receiving the target resolutions corresponding to each output interface sent by the mosaic controller and outputting video images according to the target resolutions corresponding to each output interface.

In a seventh aspect, the present application provides a chip comprising a processor and an interface, the processor being coupled to a memory via the interface, which when executed by a computer program or resolution control means in the memory, causes the method of the first aspect described above to be performed.

The advantageous effects of the second aspect to the seventh aspect described above may be described with reference to the first aspect, and will not be repeated.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic illustration of a mosaic display;

fig. 2 is a schematic diagram of an LED tiled display system according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a controller according to an embodiment of the present application;

Fig. 4 is a flow chart of a resolution control method according to an embodiment of the present application;

FIG. 5 is a schematic flow chart of a resolution control method according to an embodiment of the present application;

FIG. 6 is a schematic flow chart of another resolution control method according to an embodiment of the present application;

fig. 7 is a schematic flow chart of a resolution control method according to an embodiment of the present application;

FIG. 8 is a schematic diagram of the design constraints provided by an embodiment of the present application;

Fig. 9 is a schematic diagram of a resolution control apparatus according to an embodiment of the present application.

Detailed Description

Hereinafter, the terms "first," "second," and "third," etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", or "a third", etc., may explicitly or implicitly include one or more such feature.

First, terms related to the embodiments of the present application will be described.

1. Resolution (or also referred to as detailed timing), an attribute of digital video, including a combination of a set of data information describing the pixel transmission and display process. Some of the parameters of resolution are the (effective) width of the single frame digital image, the (effective) height of the single frame digital image, and the frame rate (i.e., the number of frames refreshed in one second), which are typically described in terms of the (effective) width (width, W) x (effective) height (height, H), progressive refresh (progress ive, P)/interlaced refresh (interleaved, I), and the number of transmission frames per second (FRAMES PER seconds, FPS). Wherein the width is represented by the number of active pixels comprised by a row of a frame of the digital image and the height is represented by the number of active pixels comprised by a column of the digital image (or the number of rows). For example, 1920×1080p60 indicates that a video image is composed of 1920 effective pixel points per line and 1080 effective pixels per line, and refresh is performed with a refresh frame rate of 60 frames per second. Another part of the parameters of the resolution are related parameters of the blanking part. For example, horizontal front shoulders (horizon front porch, HFP), horizontal back shoulders (horizon back porch, HBP), horizontal sync (horizon synchronizat ion, HSYNC) periods, vertical front shoulders (vert ical front porch, VFP), vertical back shoulders (vert ical back porch, VBP), and vertical sync (vert ical synchronizat ion, VSYNC) periods, etc.

2. Standard resolution-resolution standardized by the video electronics standards association (video electronics standards associat ion, VESA) or the like, various standard resolutions being given in the standard documents. For example, 640 x 350p85 and its blanking portion related parameters, 720 x 400p85 and its blanking portion related parameters, 800 x 600p100 and its blanking portion related parameters, 1600 x 1200p60 and its blanking portion related parameters, 1920 x 1400p60 and its blanking portion related parameters, and the like. The splice controller needs to be guaranteed with priority for clock compatibility in standard resolution.

3. The clock (which may also be referred to as a pixel clock or a pixel frequency) is used to express the number of total pixels included in the video image (digital image) per unit time, and can be calculated from the total width (effective width+blanking width) of the single frame digital image and the total height (effective height+blanking height) of the single frame digital image and the frame rate.

The LED tiled display system includes a video source, a tiled controller coupled to the video source, and one or more LED display assemblies coupled to the tiled controller. The video source may output a plurality of video images (i.e., the digital images described above). The spelling controller can splice a plurality of video images output by the video source into one video image and divide the video image into a plurality of video images, and the divided video images are respectively sent to one or a plurality of LED display components. Each LED display assembly can respectively display the video images received by the LED display assembly, and the video images displayed by one or more LED display assemblies are combined together to form one video image spliced by the splice controller.

Illustratively, FIG. 1 is a schematic illustration of a mosaic display. As shown in fig. 1, taking an example that a user needs to display 9920×1440 video images, the video source may output two 4960×1440 video images, the mosaic controller may stitch the two 4960×1440 video images output by the video source into 1 9920×1440 video image, and divide the 9920×1440 video image into 4 1920×900 video images, 2 3840×540 video images, 1 2240×900 video image, and 1 2240×540 video image, and send the divided video images to respective corresponding LED display components, where the video images displayed by the LED display components are combined together to form the 9920×1440 video image stitched by the mosaic controller.

With the development of display technology, people have increasingly higher requirements on display effects, and point-to-point display is the best method for displaying images to users without loss. Generally, the beads of the imaging device of the fixed pixel LED display assembly are fixed. Only when the resolution of the video image output by the video source is exactly the same as the resolution of the video image received by the LED display assembly, the pixels of the video image output by the video source and the pixels of the video image displayed by the LED display assembly can have a one-to-one mapping, i.e. point-to-point display.

Because the final display width and height of each LED display assembly are designed according to actual requirements, the resolution of the LED display assemblies is also various, and the conventional display method can only scale the effective width and height of the video image output by the video source to a certain extent, and the scaling can cause the loss of the content of the video image, especially when the scaling is large.

In order to keep the content of the video image displayed by the LED display assembly intact, the controller may obtain an instruction to modify the resolution parameter, calculate a clock according to the effective width, the effective height, and the frame rate in the instruction to modify the resolution parameter, and determine the detail timing (DETAIL TIMING) in the extended display identification data (extended display identification data, EDID) according to the calculated clock. The splice controller can send the EDID to the video source through a hot plug mechanism, so that the video source outputs video images according to the resolution required by a user.

However, the effective width, the effective height, and the frame rate of the splice controller in the instruction for modifying the resolution parameter generally use a fixed blanking width and blanking height when calculating the clock, so that the calculated clock may not match the clock in the standard resolution, and thus compatibility problems between the video source and the splice controller due to clock mismatch occur.

For example, the splice controller may calculate the clock according to the following equation (1):

pixel clock= (H _active+168)×(V_active+45)×V_freq equation (1))

Where Pixel Clock represents the Clock. H _active denotes an effective height in an instruction to modify a resolution parameter. 168, i.e. the fixed blanking height described above. V _active denotes the effective width in the instruction to modify the resolution parameter. 45, i.e. the fixed blanking width described above. V _freq denotes the frame rate in the instruction to modify the resolution parameter.

In order to solve the above-mentioned problems, embodiments of the present application provide a resolution control method, apparatus, a spelling controller, a storage medium, and a system, which can generate a set of resolutions (detailed timings) satisfying clocks in standard resolutions for each of potential display wide high frame rates (w× H P/I FPS), and send the generated resolutions to a video source, thereby controlling the video source to automatically output video images according to the generated resolutions.

The following description is made with reference to the accompanying drawings.

Fig. 2 is a schematic diagram of an LED tiled display system according to an embodiment of the present application. As shown in fig. 2, the tiled display system includes a video source 100 and a tiled controller 200. The video source 100 and the mosaic are connected through a wired network or a wireless network.

Optionally, the tiled display system can also include one or more LED display assemblies 300 coupled to the tile controller.

The video source 100 may be a computing device such as a computer or a server having a computing function. The server may be a single server or may be a server cluster formed by a plurality of servers. In some implementations, the server cluster may also be a distributed cluster. Video source 100 may also be implemented on a cloud platform, which may include, for example, a private cloud, public cloud, hybrid cloud, community cloud (community cloud), distributed cloud, inter-cloud (inter-cloud), or multi-cloud (multi-cloud), or the like, or any combination thereof.

For example, the video source 100 may be an ultra-high resolution server/ultra-high resolution server.

A video source 100 for acquiring video images. For example, the video source 100 may be connected to an image capture device, and the video source 100 may receive video images transmitted by the image capture device.

In some embodiments, the video source 100 is further configured to send one or more video images to the tile 200 via one or more output interfaces (illustrated in fig. 2 as three video images sent by the video source 100 to the tile 200 via three output interfaces).

As described above, the video source 100, the mosaic 200, and the one or more LED display modules 300 may be connected by a wired network or a wireless network. The wired or wireless network may include one or more media or devices capable of transmitting video images from the video source 100 to the mosaic 200.

In some embodiments, the wired or wireless network may include one or more communication media that enable the video source 100 to transmit video images directly to the mosaic 200 in real-time. In this embodiment, the video source 100 may modulate the video image according to a communication standard (e.g., a wireless communication protocol) and transmit the modulated video image to the mosaic 200. The one or more communication media may include wireless and/or wired communication media such as a Radio Frequency (RF) spectrum or one or more physical transmission lines. Alternatively, the one or more communication media may form part of a packet-based network, which may be, for example, a local area network, a wide area network, or a global network (e.g., the Internet). Alternatively, the one or more communication media may include routers, switches, base stations, or other devices that facilitate communication from video source 100 to the mosaic 200.

The splice controller 200 may also be referred to as a splice controller (spl icing control ler) or a resolution control device, and its specific form may be described with reference to the related art, and will not be described herein.

The spelling controller 200 may be configured to obtain a preset effective display width and a preset effective display height of one or more output interfaces of the video source 100, generate a target resolution for each output interface according to the preset effective display width and the preset effective display height of each output interface, and send the generated target resolution to the video source 100, where a specific process may be described in a resolution control method in the following method embodiments, and will not be described herein.

In some embodiments, the spelling controller 200 may be configured to receive a video image sent by the video source 100, splice and divide the video image sent by the video source 100 to obtain a video image corresponding to each LED display assembly, obtain a resolution corresponding to each LED display assembly, and send the video image to each LED display assembly according to the resolution corresponding to each LED display assembly.

The LED display assembly 300 may have a plurality, and each LED display assembly 300 may include a transmitting card, a plurality of receiving cards, and a plurality of LED bead modules.

The transmitting card is a video protocol conversion system, the transmitting card can strip out video data transmitted by the splice controller, the video data is transmitted to the receiving card after internal processing, and the receiving card can control the LED lamp bead module to emit light to display images according to the video data which is transmitted by the transmitting card and is subjected to internal processing.

The data transmission between the display device 200 and the transmitting card in the LED display module 300 may be described with reference to the above-mentioned data transmission between the video source 100 and the display device 200, and will not be described herein.

The execution body of the resolution control method provided in the embodiment of the present application may be the above-mentioned jigsaw controller 200, or an Application (APP) installed in the jigsaw controller 200 and providing a resolution acquisition function, or a processor (for example, a central processing unit (central process ing unit, CPU)) in the jigsaw controller 200, or a functional module in the jigsaw controller 200 for executing the resolution acquisition method, etc. The embodiments of the present application are not limited in this regard.

For convenience of description, the following description will be given by taking the implementation subject of the resolution control method provided by the embodiment of the application as an example.

FIG. 3 is a schematic diagram of a controller according to an embodiment of the present application. As shown in FIG. 3, the splice controller may include a processor 10, a memory 20, a communication line 30, a communication interface 40, and an input-output interface 50.

The processor 10, the memory 20, the communication interface 40, and the input/output interface 50 may be connected by a communication line 30.

The processor 10 is configured to execute instructions stored in the memory 20 to implement a resolution control method according to the following embodiments of the present application. The processor 10 may be a CPU, general purpose processor network processor (network processor, NP), digital signal processor (DIGITAL S IGNAL processing, DSP), microprocessor, microcontroller, programmable logic device (programmable logic device, PLD), or any combination thereof. The processor 10 may also be any other device having processing functions, such as a circuit, a device, or a software module, as embodiments of the application are not limited in this respect. In one example, processor 10 may include one or more CPUs, such as CPU0 and CPU1 in fig. 3. As an alternative implementation, the electronic device may include multiple processors, for example, and may include processor 60 (illustrated in phantom in fig. 3) in addition to processor 10.

Memory 20 for storing instructions. For example, the instructions may be a computer program. Alternatively, memory 20 may be a read-only memory (ROM) or other type of static storage device that may store static information and/or instructions, an access memory (random access memory, RAM) or other type of dynamic storage device that may store information and/or instructions, an electrically erasable programmable read-only memory (ELECTRICAL LY erasable programmable read-only memory, EEPROM), a compact disc read-only memory (compact disc read-only memory, CD-ROM) or other optical storage, optical storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media, or other magnetic storage devices, etc., as embodiments of the application are not limited in this respect.

It should be noted that, the memory 20 may exist separately from the processor 10 or may be integrated with the processor 10. The memory 20 may be located within the controller or may be located outside the controller, as embodiments of the application are not limited in this respect.

And a communication line 30 for communicating information between the various components included in the splice controller. Communication lines 30 may be industry standard architecture (industry standard architecture, ISA) lines, external device interconnect (PERIPHERAL COMPONENT INTERCONNECT, PCI) lines, or extended industry standard architecture (extended industry standard architecture, EISA) lines, among others. The communication line 30 may be divided into an address line, a data line, a control line, and the like. For ease of illustration, only one solid line is shown in fig. 3, but not only one line or one type of line.

A communication interface 40 for communicating with other devices (e.g., the video source 100 described above, or the LED display assembly 300, etc.) or other communication networks. For example, the communication interface 40 may be a digital video interface (digital visual interface, DVI) or a video interface such as HDMI.

Alternatively, the other communication network in communication with communication interface 40 may be an Ethernet network, a radio access network (radio access network, RAN), a wireless local area network (wireless local area networks, WLAN), or the like. The communication interface 40 may be a module, a circuit, a transceiver, or any device capable of enabling communication.

And the input/output interface 50 is used for realizing man-machine interaction between the user and the spelling controller. Such as enabling action interactions, text interactions, voice interactions, etc. between the user and the splice controller.

Illustratively, the input/output interface 50 may be a mouse, a keyboard, a display screen, or a touch display screen, etc., through which a user and a spelling controller can interact with each other in work or text.

It should be noted that the configuration shown in fig. 3 does not constitute a limitation of the jigsaw, and the jigsaw may include more or less components than those shown in fig. 3, or a combination of some components, or a different arrangement of components.

The resolution control method provided by the embodiment of the application is described below with reference to the accompanying drawings.

Fig. 4 is a flow chart of a resolution control method according to an embodiment of the present application. Alternatively, the method may be performed by a jigsaw having the hardware configuration shown in FIG. 3 described above. As shown in fig. 4, the method includes S101 to S103.

S101, the spelling controller obtains preset effective display width and preset effective display height of one or more output interfaces of the video source.

The preset effective display width and the preset effective display height of one or more output interfaces output by the video source refer to the effective width and the effective height of video images which are simultaneously output by the one or more output interfaces of the video source at a certain moment. For example, two 4960×1440 video images output by the video source in the mosaic display schematic shown in fig. 1 described above. The mosaic controller can obtain the preset effective display width and the preset effective display height of one or more video images output by the video source by receiving user input.

For example, as described above, the controller may include an input-output interface, which may be a mouse, a keyboard, or a touch-sensitive display screen, etc. The spelling controller can receive the preset effective display width and the preset effective display height of one or more output interfaces input by a user through a mouse, a keyboard, a touch display screen or the like.

S102, the spelling controller determines the target resolution corresponding to each output interface in the resolution database according to the preset effective display width and the preset effective display height of each output interface.

Wherein the resolution database may include a resolution corresponding to at least one standard clock. The standard clock is a clock in the reference resolution. One standard clock may correspond to multiple resolutions. The effective width of the target resolution corresponding to any one output interface is larger than or equal to the preset effective display width of the output interface, and the effective height of the target resolution corresponding to any one output interface is larger than or equal to the preset effective display height of the output interface.

Illustratively, the resolution database may be as shown in table 1 below.

TABLE 1

Resolution ID

Clock (clock)

Total width of

Total height of

Effective width of

Effective height of

Frame rate

Resolution 1

Clock 1

Total width 1

Total height 1

Effective width 1

Effective height 1

Frame rate 1

Resolution 2

Clock 1

Total width 2

Total height 2

Effective width 2

Effective height 2

Frame rate 2

Resolution 3

Clock 2

Total width 3

Total height 3

Effective width 3

Effective height 3

Frame rate 3

As shown in table 1, the resolution database may include a resolution ID term, a clock term, an overall width term, an overall height term, an effective width term, an effective height term, and a frame rate term. The resolution ID entry may include resolution 1, resolution 2, and resolution 3, among others. The clock entries may include clock 1 and clock 2. The total width term may include a total width 1, a total width 2, and a total width 3. The total height items may include a total height 1, a total height 2, and a total height 3. The effective width term may include an effective width 1, an effective width 2, and an effective width 3. The effective height items may include an effective height 1, an effective height 2, and an effective height 3. The frame rate entries may include frame rate 1, frame rate 2, and frame rate 3. Resolution 1, clock 1, total width 1, total height 1, effective width 1, effective height 1, and frame rate 1 have correspondence. Resolution 2, clock 1, total width 2, total height 2, effective width 2, effective height 2, and frame rate 2 have correspondence. Resolution 3, clock 2, total width 3, total height 3, effective width 3, effective height 3, and frame rate 3 have correspondence.

In one possible implementation, the spelling controller may sort the resolutions in the resolution database in a certain order, e.g., from smaller clock to larger clock, to obtain a first sorting result, and select the target resolution according to the first sorting result. Fig. 5 is a schematic flow chart of a resolution control method according to an embodiment of the present application. As shown in fig. 5, taking an example that one or more output interfaces of the video source includes a first output interface, S102 may specifically include S201 to S211.

S201, the spelling controller obtains a preset effective display width and a preset effective display height of the first output interface.

S201 may be described with reference to S101, and will not be described herein.

S202, sequencing a plurality of resolutions in a resolution database according to the order of the clocks from small to large by the spelling controller to obtain a first sequencing result.

S202, the spelling controller judges whether the number of times of the resolution selected currently is larger than or equal to the number of resolutions in the first sequencing result.

If yes, S204 is executed, and if no, S205 is executed.

S204, the spelling controller sends out first information.

The first information is used for indicating selection failure.

For example, as described above, the controller may include an input-output interface, which may be a touch display screen, and the controller may display a first interface in the touch display screen, the first interface including the first information described above.

S205, the spelling controller judges whether the effective width of the resolution ratio selected at present is larger than or equal to the preset effective display width of the first output interface, and whether the effective height of the resolution ratio selected at present is larger than or equal to the preset effective display height of the first output interface.

If yes, execution is S206, and if not, execution is S207.

S206, the spelling controller takes the currently selected resolution as the target resolution of the first output interface.

S207, the spelling controller judges whether the effective width of the resolution ratio selected at present is larger than or equal to the preset target effective width of the first output interface, and whether the effective height of the resolution ratio selected at present is smaller than the preset target effective height of the first output interface.

If yes, S208 and S209 are executed, and then S202 is returned, and if not, S210 is executed.

S208, the spelling controller selects the resolution before the resolution currently selected in the first sorting result to judge.

S209, the spelling controller adds 1 to the number of times of the resolution currently selected.

S210, the spelling controller judges whether the effective width of the resolution selected currently is smaller than the preset effective display width of the first output interface, and whether the effective height of the resolution selected currently is larger than or equal to the preset effective display height of the first output interface.

If yes, S211 and S209 are executed, and then S202 is returned, and if no, S204 is executed.

S211, the spelling controller selects the resolution after the resolution currently selected in the first sorting result to judge.

Optionally, before S102, the spelling controller may further acquire a standard clock and generate a resolution database according to the standard clock. Fig. 6 is another flow chart of the resolution control method according to the embodiment of the present application, as shown in fig. 6, before S102, the method may further include S301 to S303.

S301, the spelling controller obtains preset frame rate of one or more output interfaces of the video source.

S301 may be described with reference to S101, and will not be described herein.

S302, the spelling controller acquires at least one initial standard clock.

Alternatively, the spelling controller may determine a plurality of candidate clocks from the plurality of initial clocks in a preset order according to a preset clock stepping accuracy.

The clock step precision can be preset in the spelling controller by a manager, and the clock step precision is used for selecting the minimum interval of the candidate clocks from the initial clocks according to a preset sequence. For example, the clock step accuracy may be 1 kilohertz (khz), or 1Mhz, etc. The embodiment of the application does not limit specific numerical values of the clock stepping precision. The initial clock refers to a clock between a minimum clock and a maximum clock. The minimum clock can also be preset in the spelling controller by a manager, and the specific value of the minimum clock is not limited in the embodiment of the application. The maximum clock may be preset in the controller by the manager, or the controller may first determine, according to the maximum limit bandwidth of the current scene input by the user and the correspondence between the maximum limit bandwidth and the preset maximum limit bandwidth and the maximum limit clock, the maximum limit clock corresponding to the maximum limit bandwidth of the current scene as the maximum clock. The embodiment of the application also does not limit the specific value of the maximum clock.

For example, the splice controller may choose a candidate clock every other clock step precision starting with the minimum clock until traversing from the minimum clock to the maximum clock. Alternatively, the splice controller may select a candidate clock every other clock step from the maximum clock until traversing from the maximum clock to the minimum clock.

For example, taking the example that the jigsaw traverses from the minimum clock to the maximum clock, assuming that the minimum clock is 100Mhz and the clock stepping precision is 1Mhz, the maximum limit bandwidth of the current scene is 10.2 gigabits per second (Giga bits per second, gbps) (i.e., the current scene uses the HMDI1.4 standard transmission link to transmit video image data), the jigsaw may determine that the maximum limit clock 340Mhz corresponding to 10.2 (Gbps) is the maximum clock according to the correspondence between the maximum limit bandwidth and the maximum limit clock, and traverse the minimum clock 100Mhz and the maximum clock 340Mhz with the 1Mhz as the stepping precision, obtain a plurality of candidate clocks 101Mhz, 102Mhz, 103Mhz, and 340Mhz, and determine a plurality of initial standard clocks from the plurality of candidate clocks.

Optionally, the jigsaw may further acquire capability information of the video source, determine a clock supported by the video source and a clock supported by the jigsaw according to the capability information of the video source and the capability information of the preset jigsaw, and delete clocks out of a union of the clocks supported by the video source and the clocks supported by the jigsaw from the plurality of standard clocks.

S303, the spelling controller generates a resolution database based on at least one standard clock and preset frame rates of one or more output interfaces of the video source.

Alternatively, also taking the first output interface of the one or more output interfaces of the video source as an example, assuming that the preset frame rate of the first output interface is the first frame rate, the spelling controller may divide the first standard clock by the first frame rate to obtain the first area, perform one or more times of factorization on the first area, each time of factorize the first area into two factors, regarding each time of factorization, regarding one (e.g., a larger one) of the two factors obtained by factorization as a maximum width, regarding the other (e.g., a smaller one) of the two factors obtained by factorization as a maximum height, determining an effective width according to the maximum width, determining an effective height according to the maximum height, and generating the resolution in the resolution database based on the maximum width, the maximum height, the effective width, and the effective height.

For example, the splice controller may subtract 80 from the maximum width to obtain the effective width. Also taking the first standard clock, the first frame rate, and the first area as examples, the controller may calculate the first standard clock, the first frame rate, and the first area according to a VESA-coordinated video timing (VESA-coordinated video t imings, VESA-CVT) standard to obtain a first value, and subtract the first value from the maximum height to obtain an effective height.

The first standard clock is a standard clock capable of dividing the first frame rate.

Optionally, after determining the target resolution corresponding to each output interface, the spelling controller may also modify the target resolution according to the resolution standard. For example, the target resolution is modified according to the VESA-CVT standard, or the VESA-image interchange format (GIF) standard, so that the target resolution satisfies the above resolution standard, thereby better ensuring compatibility between the video source and the mosaic controller.

Optionally, after determining the target resolution corresponding to each output interface, the spelling controller may further modify the target resolution according to the hardware bit width limit of the transmission link, so that when the spelling controller sends the target resolution to the video source, the bit width of each parameter in the sent target resolution is smaller than the hardware bit width limit of the transmission link. In this case, taking the clock in the target resolution as an example, the method may further include the splice controller obtaining bit width information of the video source, and modifying the clock in the target resolution corresponding to each output interface according to the bit width information of the video source and the bit width information of the splice controller so that the bit width of the clock in the target resolution corresponding to each output interface is less than or equal to a minimum value of a maximum bit width of the transmission link transmission clock indicated by the bit width information of the video source and a maximum bit width of the splice controller transmission clock indicated by the bit width information of the splice controller.

Wherein, the bit width information of the spelling controller can be preset in the spelling controller. For example, preset in the memory of the mosaic. The embodiment of the application does not limit the specific content of the bit width information of the spelling controller and the numerical value of the indicated maximum bit width.

Alternatively, the splice controller may modify the target resolution according to the resolution criterion, and then modify the target resolution according to the hardware bit width limitation of the transmission link. In this case, fig. 7 is a schematic flow chart of a resolution control method according to an embodiment of the present application. As shown in fig. 7, after S102, the method may further include S401 to S405.

S401, the spelling controller acquires bit width information of the video source.

The bit width information of the video source is used for indicating the maximum bit width of a transmission clock of a transmission link between the splice controller and the video source. For example, the splice controller may be obtained by receiving bit width information sent by a video source.

S402, the spelling controller corrects the target resolution corresponding to each output interface according to the resolution standard.

The specific correction process may be described with reference to the related art of the resolution standard, and will not be described herein.

S403, the spelling controller judges whether the bit width of the clock in the target resolution corresponding to each output interface is smaller than or equal to the maximum bit width of the transmission link transmission clock indicated by the bit width information of the video source and the minimum value of the maximum bit width of the spelling controller transmission clock indicated by the bit width information of the spelling controller.

If yes, S404 is executed, and if no, S405 is executed, and then S404 is executed.

S404, outputting the target resolution by the spelling controller.

S405, the jigsaw controller adjusts the target resolution corresponding to each output interface so that the bit width of the target clock in the target resolution corresponding to each output interface is smaller than or equal to the minimum value of the maximum bit width of the transmission clock of the transmission link indicated by the bit width information of the video source and the maximum bit width of the transmission clock of the jigsaw controller indicated by the bit width information of the jigsaw controller.

It should be noted that, the above description is given by taking the clock in the target resolution as an example, and the correction process of other parameters in the target resolution, such as the maximum width, the maximum height, the effective width, the effective height, etc., may also be described with reference to S401 to S405, which are not repeated herein.

The above description is made with reference to the generation process of the resolution database by taking the standard clock as an example. Optionally, the splice controller may also generate a near-standard clock resolution database based on the near-standard clock. Specific processes may be described with reference to S301 to S303, and are not described herein. In this case, when the jigsaw device cannot determine the target resolution from the resolution database (i.e., the resolution database does not include the target resolution corresponding to a certain output interface), the jigsaw device may select the target resolution from the non-standard database. The specific selection process may be described with reference to S201 to S211, and will not be described herein.

The near standard clock is a clock obtained by multiplying a preset coefficient by the standard clock, and the preset coefficient is a positive number. For example, the preset coefficient may be 0.1, 0.5, 1,2, or the like. The embodiment of the application does not limit the specific numerical value of the preset coefficient.

For example, when the resolution database does not include the target resolution corresponding to the first output interface, the method may further include multiplying at least one standard clock by a preset coefficient to obtain at least one near standard clock, generating a near standard clock resolution database by the jigsaw based on the at least one near standard clock and the preset frame rate of one or more output interfaces of the video source, and determining the target resolution corresponding to the first output interface in the near standard clock resolution database by the jigsaw according to the preset effective display width and the preset effective display height of the first output interface.

It should be understood that the clock is used to express the total number of pixels contained in the video image per unit time. When the clock of the video source for outputting the video image is the standard clock supported by the spelling controller, the number of pixels output by the video source in unit time is matched with the number of pixels output by the spelling controller in unit time, so that the problem of compatibility between the video source and the spelling controller is avoided. When the clock of the video source for outputting the video image is the preset coefficient times of the standard clock supported by the spelling controller, the spelling controller can perform corresponding operations such as delay output or advance output on the video image output by the video source according to the preset coefficient, and can also achieve the mutual matching of the number of pixels output in unit time, so that the compatibility problem between the video source and the spelling controller is avoided. In the resolution control method provided by the embodiment of the application, when the target resolution cannot be selected from the resolution database generated by the standard clock, the target resolution is selected from the near-standard clock resolution database generated by the near-standard clock, so that the compatibility problem between the video source and the spelling controller is avoided, the variety supporting the preset effective display width and the preset effective display height can be increased, and the universality of the spelling control display scheme is improved.

And S103, the spelling controller sends the target resolution corresponding to each output interface to the video source so that the video source outputs video images according to the target resolution corresponding to each output interface.

In one possible implementation, the splice controller may interact with the video source via a hot plug mechanism in a handshake-like protocol, and send resolution information of one or more output interfaces to the video source during the interaction.

The resolution information corresponding to the one or more output interfaces respectively comprises target resolutions corresponding to the one or more output interfaces respectively.

Optionally, taking the first output interface as an example, after S102 and before S103, the method may further include generating, by the spelling controller, resolution information of the first output interface according to a target resolution corresponding to the first output interface, where the resolution information of the first output interface includes the target resolution corresponding to the first output interface.

Optionally, taking the first output interface as an example, the splice controller may determine resolution information of the first output interface according to the target resolution corresponding to the first output interface, write the resolution information into an EEPROM of the splice controller, and reset the hot plug according to the level high and low states of the hot plug pin of the video interface of the splice controller.

For example, if the video interface hot plug of the splice controller is high, the splice controller can pull down the hot plug first, delay by about 200 microseconds, and then pull up the hot plug, and if the video interface hot plug of the splice controller is low, the splice controller can pull up the hot plug first, delay by about 200 microseconds, and then pull down the hot plug.

Alternatively, taking the first output interface as an example, when the effective width in the target resolution corresponding to the first output interface is less than or equal to 4096, or when the effective height in the resolution corresponding to the first output interface is less than 4096, the spelling controller may determine the detail timing (DETAIL TIMING) in the EDID of the first output interface according to the target resolution corresponding to the first output interface, and send the EDID of the first output interface to the video source as the resolution information of the first output interface.

The EDID is a VESA standard data format, and includes vendor information, a maximum image size, a color setting, a vendor preset value, and parameter information of a frequency range.

Illustratively, the specific timed memory addresses in the EDID may be as shown in table 2 below.

TABLE 2

Referring to table 2, table 2 shows a memory address of 18-byte parameters of detail timing in EDID, and table 2 is exemplified by bold and underline.

Illustratively, also taking the storage address shown in table 2 above as an example, the specific calculation rule of the storage address for this detailed timing can be shown in table 3 below.

TABLE 3 Table 3

As shown in table 3, the meaning of the parameters stored in each specific memory address of the detail timing in the EDID may be described with reference to the related art, which is repeated here.

Alternatively, taking the first output interface as an example, when the effective width in the target resolution corresponding to the first output interface is greater than or equal to 4096, or when the effective height in the resolution corresponding to the first output interface is greater than or equal to 4096, the spelling controller may determine, according to the target resolution corresponding to the first output interface, the VII type detailed timing description (TYPEVIIDETAI LED T IMING DATA b lock) in the second generation display identification data (DISPLAYID) of the first output interface, and send DISPLAYID of the first output interface to the video source as resolution information of the first output interface.

Illustratively, the detailed timing description of type VII in DISPLAYID may be as shown in Table 4 below.

TABLE 4 Table 4

As shown in table 4, the specific meaning of the 20-byte parameter in the VII-type detailed timing description may be described with reference to the related art, and will not be repeated here.

It should be appreciated that the 18 byte parameter bit width of the detail timing in EDID supports a maximum effective width and maximum effective height of the transmission of only 4095, which cannot be adapted to any resolution above 4 k. In the resolution control method provided by the embodiment of the application, when the effective width or the effective height of the target resolution corresponding to the generated output interface is larger than or equal to 4096, the target resolution can be sent to the video source by adopting the VII type detailed time sequence description with the parameter bit width of 20 bytes in DISPALYID, so that the parameter bit width limit of EDID is broken through, and the universality of the resolution control scheme is improved.

It will be appreciated that the mosaic is typically configured to preferentially guarantee compatibility with standard clocks in standard resolutions, which may not be supported by the mosaic when the video source outputs video images with non-standard clocks in non-standard resolutions, resulting in compatibility problems. The resolution control method provided by the embodiment of the application can select the target resolution corresponding to each output interface from a plurality of resolutions corresponding to the standard clock based on the preset effective display width and the preset effective height of one or more output interfaces of the video source, and control the video source to output video images from one or more output interfaces according to the corresponding target resolutions, wherein the one or more target resolutions all meet the standard clock, thereby avoiding compatibility problems and improving the universality of the spelling control display scheme.

From the above description of the resolution control method, the design constraint of the present application mainly includes two aspects, namely, clock compatibility constraint and transmission link constraint.

Fig. 8 is a schematic structural diagram of a design constraint provided by an embodiment of the present application. As shown in fig. 8, the design constraints of the present application include clock compatibility constraints and transmission link constraints.

The clock compatibility constraint means that the video source often preferentially supports the resolution of the standard clock, and the resolution corresponding to the non-standard clock may have compatibility problem, so that the clock corresponding to the target resolution needs to be selected according to the following strategy:

(1) Preference is given to selecting a standard clock in a standard resolution;

(2) When the standard clock cannot meet the preset effective display width and the preset effective display height of one or more output interfaces of the video source acquired by the spelling controller, the near standard clock obtained by multiplying the standard clock by a preset coefficient is preferentially selected;

(3) When both (1) and (2) are not satisfied, a non-standard clock generation target resolution is selected.

The transmission link constraints are mainly constraints on three aspects of maximum (limit) bandwidth of the transmission link, hardware bit length, and time Zhong Kongdong.

The constraints on maximum (limit) bandwidth depend mainly on the version of the video interface protocol between the video source and the mosaic. For example, the maximum clock explicitly specified to be supported in the high definition multimedia interface (HIGH DEFINIT ion mutt IMEDIA INTERFACE, HDMI) 1.4 protocol standard is 340 megahertz (Mhz), the maximum clock explicitly specified to be supported in the HDMI2.0 protocol standard is 600Mhz, and the like.

In the constraint of hardware bit length, the spelling controller completes the analysis of the video protocol through the video interface chip, the registers inside the chip often have bit length limitation on each component part of the resolution (such as HFP, HSYNC, HBP, VFP, VSYNC and VBP, etc.), and the bit length of each component part in the generated target resolution should be smaller than the bit length limitation of the registers inside the chip.

In the constraint of clock hole, a producer of a chip may have some clock holes inside when designing hardware or software, and the clock holes are not supported clocks, so that when determining clocks in a resolution database from candidate clocks, the unsupported candidate clocks can be removed.

The foregoing description of the solution provided by the embodiments of the present application has been mainly presented in terms of a method. To achieve the above functions, it includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. The technical aim may be to use different methods to implement the described functions for each particular application, but such implementation should not be considered beyond the scope of the present application.

In an exemplary embodiment, the embodiment of the application further provides a resolution control device, which can apply the above-mentioned jigsaw. Fig. 9 is a schematic diagram of a resolution control apparatus according to an embodiment of the present application. As shown in fig. 9, the apparatus includes an acquisition module 901, a processing module 902, and a transmission module 903.

The obtaining module 901 is configured to obtain a preset effective display width and a preset effective display height of one or more output interfaces of a video source.

The processing module 902 is configured to determine, according to a preset effective display width and a preset effective display height of each output interface, a target resolution corresponding to each output interface in a resolution database, where the resolution database includes resolutions corresponding to at least one standard clock, the standard clock is a clock in the standard resolutions, and one standard clock corresponds to multiple resolutions.

The sending module 903 is configured to send the target resolution corresponding to each output interface to the video source, so that the video source shows the video image according to the target resolution corresponding to each output interface.

In some possible embodiments, the effective width of the target resolution corresponding to any one output interface is greater than or equal to the preset effective display width of the output interface, and the effective height of the target resolution corresponding to any one output interface is greater than or equal to the preset effective display height of the output interface.

In other possible embodiments, the obtaining module 901 is further configured to obtain a preset frame rate of one or more output interfaces of the video source, obtain at least one initial standard clock, and the processing module 902 is further configured to generate the resolution database based on the at least one initial standard clock and the preset frame rate of the one or more output interfaces of the video source.

In still other possible embodiments, the processing module 902 is specifically configured to determine a plurality of candidate clocks from the plurality of initial clocks according to a preset sequence according to a preset clock stepping precision, where the clock stepping precision is used to indicate a minimum interval of candidate clocks selected from the initial clocks according to the preset sequence, and select, from the plurality of candidate clocks, a clock overlapping with a clock in the standard resolution as the standard clock.

In still other possible embodiments, the at least one standard clock comprises a first standard clock, the one or more output interfaces comprise a first output interface, and the preset frame rate of the first output interface is the first frame rate. The processing module 902 is specifically configured to divide the first standard clock by the first frame rate to obtain a first area, perform one or more factorization on the first area, each time decompose the first area into two factors, for each factorization, take one of the two factors obtained by the factorization as a maximum width, the other one of the two factors obtained by the factorization as a maximum height, determine an effective width according to the maximum width, determine an effective height according to the maximum height, and generate a resolution in the resolution database based on the maximum width, the maximum height, the effective width, and the effective height.

In still other possible embodiments, the one or more output interfaces include a first output interface, a processing module 902, after determining a target resolution corresponding to each output interface according to the resolution database and the preset effective display width and the preset effective display height of each output interface, the processing module 902 is further configured to generate resolution information of the first output interface according to the target resolution corresponding to the first output interface, where the resolution information of the first output interface includes the target resolution corresponding to the first output interface, and a sending module 903, specifically configured to send the resolution information of the first output interface to the video source;

In still other possible embodiments, when the effective width or the effective height in the target resolution of the first output interface is smaller than 4096, the processing module 902 is specifically configured to generate extended display identification data EDID of the first output interface according to the target resolution corresponding to the first output interface, where the EDID of the first output interface includes the target resolution corresponding to the first output interface, and the resolution information of the first output interface includes the EDID of the first output interface.

In still other possible embodiments, when the effective width or the effective height of the target resolution of the first output interface is greater than or equal to 4096, the processing module 902 is specifically configured to generate second-generation display identification data DISPLAYID of the first output interface according to the target resolution corresponding to the first output interface, DISPLAYID of the first output interface includes the target resolution corresponding to the first output interface, and the resolution information of the first output interface includes DISPLAYID of the first output interface.

In still other possible embodiments, the processing module 902 is further configured to multiply the at least one initial standard clock by a preset coefficient to obtain at least one near standard clock, where the preset coefficient is positive, and generate a near standard clock resolution database based on the at least one near standard clock and a preset frame rate of one or more output interfaces of the video source.

In still other possible embodiments, the processing module 902 is further configured to determine, when the resolution database does not include the target resolution corresponding to the first output interface, the target resolution corresponding to the first output interface in the near-standard clock resolution database according to the preset effective display width and the preset effective display height of the first output interface.

It should be noted that the division of the modules in fig. 9 is illustrative, and is merely a logic function division, and other division manners may be actually implemented. For example, two or more functions may also be integrated in one processing module. The integrated modules may be implemented in hardware or in software functional modules.

In an exemplary embodiment, the present application also provides a readable storage medium including instructions that, when executed on a jigsaw (resolution control device), cause the jigsaw (resolution control device) to perform any of the methods provided by the above embodiments.

In an exemplary embodiment, the present application also provides a computer program product containing computer-executable instructions that, when run on a jigsaw (resolution control device), cause the jigsaw (resolution control device) to perform any of the methods provided by the above embodiments.

In an exemplary embodiment, the application also provides a chip comprising a processor and an interface, the processor being coupled to the memory through the interface, which when executed by the processor, causes any one of the methods provided by the above embodiments to be performed, when the processor executes instructions in the memory by a computer program or a jigsaw (resolution control device).

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer-executable instructions. When the computer-executable instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are fully or partially produced. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer-executable instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, from one website, computer, server, or data center by wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices including one or more servers, data centers, etc. that can be integrated with the media. Usable media may be magnetic media (e.g., floppy disks, hard disks, magnetic tape), optical media (e.g., DVD), or semiconductor media (e.g., solid State Disk (SSD)) or the like.

Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims. In the claims, the term "comprising" (Compris ing) does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

The foregoing is merely illustrative of specific embodiments of the present application, and the scope of the present application is not limited thereto, but any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A resolution control method, characterized in that the method is applied to a splicing controller connected to a video source; the method comprises:

Obtaining a preset frame rate of one or more output interfaces of the video source;

Determining a plurality of candidate clocks from a plurality of initial clocks in a preset order according to a preset clock stepping precision; the clock stepping precision is used to indicate a minimum interval for selecting a candidate clock from the initial clocks in the preset order;

Selecting a clock that overlaps with a clock in a standard resolution from the plurality of candidate clocks as a standard clock to obtain at least one initial standard clock;

generating a resolution database based on the at least one initial standard clock and preset frame rates of one or more output interfaces of the video source;

Obtaining a preset effective display width and a preset effective display height of one or more output interfaces of the video source;

Determining a target resolution corresponding to each output interface in the resolution database according to a preset effective display width and a preset effective display height of each output interface; the resolution database includes a resolution corresponding to at least one standard clock, the standard clock being a clock in a standard resolution, and one standard clock corresponding to multiple resolutions; the effective width in the target resolution corresponding to any output interface is greater than or equal to the preset effective display width of the output interface; and the effective height in the target resolution corresponding to any output interface is greater than or equal to the preset effective display height of the output interface;

The target resolution corresponding to each output interface is sent to the video source, so that the video source outputs a video image according to the target resolution corresponding to each output interface.

2. The method according to claim 1, wherein the at least one standard clock comprises a first standard clock, the one or more output interfaces comprises a first output interface, and the preset frame rate of the first output interface is a first frame rate;

The generating of a resolution database based on the at least one initial standard clock and preset frame rates of one or more output interfaces of the video source includes:

Dividing the first standard clock by a first frame rate to obtain a first area;

Factoring the first area once or more times, each time factoring the first area into two factors;

For each factorization, one of the two factors obtained by the factorization is used as the maximum width, and the other of the two factors obtained by the factorization is used as the maximum height;

determining an effective width according to the maximum width;

determining an effective altitude based on the maximum altitude;

A resolution in the resolution database is generated based on the maximum width, the maximum height, the effective width, and the effective height.

3. The method according to claim 1 or 2, wherein the one or more output interfaces include a first output interface;

After determining the target resolution corresponding to each output interface in the resolution database according to the preset effective display width and the preset effective display height of each output interface, the method further includes:

generating resolution information of the first output interface according to the target resolution corresponding to the first output interface; the resolution information of the first output interface including the target resolution corresponding to the first output interface;

The sending the target resolution corresponding to each output interface to the video source includes:

Sending resolution information of the first output interface to the video source.

4. The method according to claim 3, wherein when the effective width or effective height of the target resolution of the first output interface is less than 4096, generating the resolution information of the first output interface according to the target resolution corresponding to the first output interface comprises:

generating, according to a target resolution corresponding to the first output interface, extended display identification data EDID of the first output interface, wherein the EDID of the first output interface includes the target resolution corresponding to the first output interface; and the resolution information of the first output interface includes the EDID of the first output interface;

or,

When the effective width or the effective height of the target resolution of the first output interface is greater than or equal to 4096, generating the resolution information of the first output interface according to the target resolution corresponding to the first output interface includes:

According to the target resolution corresponding to the first output interface, the second-generation display identification data DisplayID of the first output interface is generated, and the DisplayID of the first output interface includes the target resolution corresponding to the first output interface; the resolution information of the first output interface includes the DisplayID of the first output interface.

5. The method according to claim 1, wherein the one or more output interfaces include a first output interface, and the method further comprises:

Multiplying the at least one initial standard clock by a preset coefficient to obtain at least one near-standard clock; the preset coefficient is a positive number;

generating a near-standard clock resolution database based on the at least one near-standard clock and preset frame rates of one or more output interfaces of the video source;

When the resolution database does not include the target resolution corresponding to the first output interface, the target resolution corresponding to the first output interface is determined in the near-standard clock resolution database according to the preset effective display width and preset effective display height of the first output interface.

6. A resolution control device, characterized in that the device is connected to a video source; the device comprises: an acquisition module, a processing module, and a sending module;

The acquisition module is configured to acquire a preset frame rate of one or more output interfaces of the video source; determine a plurality of candidate clocks from a plurality of initial clocks in a preset order based on a preset clock stepping precision; the clock stepping precision is used to indicate a minimum interval for selecting a candidate clock from the initial clocks in the preset order; select a clock that overlaps with a clock in a standard resolution from the plurality of candidate clocks as a standard clock to obtain at least one initial standard clock; the processing module is further configured to generate a resolution database based on the at least one initial standard clock and the preset frame rate of one or more output interfaces of the video source; and obtain a preset effective display width and a preset effective display height of the one or more output interfaces of the video source;

The processing module is configured to determine, in the resolution database, a target resolution corresponding to each output interface based on a preset effective display width and a preset effective display height of each output interface; the resolution database includes a resolution corresponding to at least one standard clock, the standard clock being a clock in a standard resolution, and one standard clock corresponding to multiple resolutions; the effective width of the target resolution corresponding to any output interface is greater than or equal to the preset effective display width of the output interface; and the effective height of the target resolution corresponding to any output interface is greater than or equal to the preset effective display height of the output interface;

The sending module is configured to send the target resolution corresponding to each output interface to the video source, so that the video source displays the video image according to the target resolution corresponding to each output interface.

7. The device according to claim 6, characterized in that

The at least one standard clock includes a first standard clock, the one or more output interfaces include a first output interface, and the preset frame rate of the first output interface is a first frame rate; the processing module is specifically used to divide the first standard clock by the first frame rate to obtain a first area; factorize the first area once or multiple times, and decompose the first area into two factors each time; for each factorization, one of the two factors obtained by the factorization is used as the maximum width, and the other of the two factors obtained by the factorization is used as the maximum height; determine the effective width according to the maximum width; determine the effective height according to the maximum height; and generate the resolution in the resolution database based on the maximum width, the maximum height, the effective width, and the effective height.

8. The device according to claim 6 or 7, characterized in that

The one or more output interfaces include a first output interface; after the processing module determines the target resolution corresponding to each output interface in the resolution database based on the preset effective display width and the preset effective display height of each output interface, the processing module is further used to generate resolution information of the first output interface based on the target resolution corresponding to the first output interface; the resolution information of the first output interface includes the target resolution corresponding to the first output interface; the sending module is specifically used to send the resolution information of the first output interface to the video source.

9. The device according to claim 8, characterized in that

When the effective width or effective height in the target resolution of the first output interface is less than 4096, the processing module is specifically used to generate the extended display identification data EDID of the first output interface according to the target resolution corresponding to the first output interface, and the EDID of the first output interface includes the target resolution corresponding to the first output interface; the resolution information of the first output interface includes the EDID of the first output interface; or, when the effective width or effective height in the target resolution of the first output interface is greater than or equal to 4096, the processing module is specifically used to generate the second-generation display identification data DisplayID of the first output interface according to the target resolution corresponding to the first output interface, and the DisplayID of the first output interface includes the target resolution corresponding to the first output interface; the resolution information of the first output interface includes the DisplayID of the first output interface.

10. The device according to claim 6, characterized in that

The one or more output interfaces include a first output interface, and the processing module is further used to multiply the at least one initial standard clock by a preset coefficient to obtain at least one near-standard clock; the preset coefficient is a positive number; based on the at least one near-standard clock and the preset frame rate of one or more output interfaces of the video source, a near-standard clock resolution database is generated; when the resolution database does not include the target resolution corresponding to the first output interface, the target resolution corresponding to the first output interface is determined in the near-standard clock resolution database according to the preset effective display width and preset effective display height of the first output interface.

11. A resolution control device, characterized in that the splicing controller comprises: a processor and a memory;

The memory stores instructions executable by the processor;

When the processor is configured to execute the instructions, the resolution control device implements the method according to any one of claims 1 to 5.

12. A readable storage medium, characterized in that the readable storage medium comprises: software instructions;

When the software instructions are executed in the spelling controller, the spelling controller implements the method according to any one of claims 1 to 5.