CN115995220A - Display screen output control method and display - Google Patents

Abstract

The embodiment of the present application provides a display screen output control method and a display, the method includes: obtaining the set of pixel rows and/or the set of pixel columns to which the image display area in the display screen belongs; according to the set of pixel rows, using a logic chip to Perform display control on the pixel row for image display in the display screen; and/or; determine the power management chip and/or source chip corresponding to the set of pixel columns, and use the power management chip and/or the source chip The pole chip controls the pixel columns for image display in the display screen. By using a logic chip to control the pixel row for image display in the display screen, and/or using a power management chip and/or source chip to control the pixel column for image display in the display screen, the image can be controlled. Scanning and displaying images is performed in the display area, and scanning display in non-image display areas is reduced, so as to reduce power consumption of liquid crystal display products.

Description

Display output control method and display

technical field

The present application relates to the field of display technology, in particular to a display screen output control method and a display.

Background technique

At present, when a liquid crystal display product is normally displayed, if a certain display area does not display an image, then this display area will display an L0 grayscale image, as shown in FIG. 1 . However, this display method will lead to higher power consumption of liquid crystal display products.

Contents of the invention

The purpose of the embodiments of the present application is to provide a display screen output control method and a display to reduce power consumption of liquid crystal display products. The specific technical scheme is as follows:

In the first aspect, the embodiment of the present application provides a display screen output control method, the method comprising:

Obtain the set of pixel rows and/or the set of pixel columns to which the image display area in the display screen belongs;

According to the set of pixel rows, using a logic chip to perform display control on the pixel rows for image display in the display screen;

and / or;

Determine the power management chip and/or source chip corresponding to the set of pixel columns, and use the power management chip and/or the source chip to control the pixel columns for image display in the display screen.

In a possible implementation manner, the determining the power management chip and/or the source chip corresponding to the set of pixel columns uses the power management chip and/or the source chip to The pixel columns for image display are controlled, including:

Generate a data signal through the logic chip according to the set of pixel columns, wherein the data signal includes a start column identifier and an end column identifier;

The data signal is sent to the source chip, and the source chip is used to control the pixel columns for image display in the display screen according to the start column identifier and the end column identifier.

In a possible implementation manner, the generating a data signal through the logic chip according to the set of pixel columns includes:

For each source chip, according to the pixel column interval driven by the source chip and the set of pixel columns, determine the start column identifier and end column identifier of the source chip through the logic chip, and generate the source chip The unified standard interface USIT data signal of the chip;

The sending the data signal to the source chip, using the source chip to control the pixel column for image display in the display screen according to the start column identifier and the end column identifier, include:

For each source chip, use the USIT transmission protocol to send the USIT data signal of the source chip to the source chip through the logic chip; The identification and the end column identification control the pixel columns for image display in the display screen.

In a possible implementation manner, the determining the power management chip and/or the source chip corresponding to the set of pixel columns uses the power management chip and/or the source chip to The pixel columns for image display are controlled, including:

Acquiring respectively the intervals of the pixel columns driven by each of the source chips;

According to each of the pixel column intervals and the pixel column set, determine a target source chip that needs to be powered on each of the source chips;

The target source chip is powered by a power management chip, and the pixel columns for image display in the display screen are controlled by the target source chip.

In a possible implementation manner, the controlling the pixel column for image display in the display screen through the target source chip includes:

Generate a data signal through the logic chip according to the set of pixel columns, wherein the data signal includes a start column identifier and an end column identifier;

The data signal is sent to the source chip, and the source chip is used to control the pixel columns for image display in the display screen according to the start column identifier and the end column identifier.

In a possible implementation manner, the generating a data signal through the logic chip according to the set of pixel columns includes:

For each source chip, according to the pixel column interval driven by the source chip and the set of pixel columns, determine the start column identifier and end column identifier of the source chip through the logic chip, and generate the source chip Chip USIT data signal;

The sending the data signal to the source chip, using the source chip to control the pixel column for image display in the display screen according to the start column identifier and the end column identifier, include:

For each source chip, use the USIT transmission protocol to send the USIT data signal of the source chip to the source chip through the logic chip; The identification and the end column identification control the pixel columns for image display in the display screen.

In a possible implementation manner, using a logic chip to perform display control on pixel rows for image display in the display screen according to the set of pixel rows includes:

According to the set of pixel rows, the image display detection module of the system chip is used to determine the pixel rows to be scanned;

The logic chip controls the pulse signal TP to scan the row of pixels to be scanned row by row, so as to control the display of the row of pixels for image display in the display screen.

In a possible implementation manner, the control pulse signal TP through the logic chip performs progressive scanning on the pixel row to be scanned, so as to perform display control on the pixel row for image display in the display screen, including:

The logic chip controls the pulse signal TP to output the first voltage signal, and scans the pixel rows to be scanned row by row, so as to control the display of the pixel rows for image display in the display screen.

In a second aspect, an embodiment of the present application provides a display, including a source chip, a logic chip, and a power management chip, and the display is used to implement the method described in any one of the above-mentioned first aspects.

In a possible implementation manner, the display further includes a system chip configured to determine the set of pixel rows and/or the set of pixel columns to which the image display area in the display screen belongs.

Beneficial effects of the embodiment of the application:

A display screen output control method and a display provided in an embodiment of the present application, the method includes: obtaining the set of pixel rows and/or the set of pixel columns to which the image display area in the display screen belongs; according to the set of pixel rows, using a logic chip to Perform display control on the pixel row for image display in the display screen; and/or; determine the power management chip and/or source chip corresponding to the set of pixel columns, and use the power management chip and/or the source chip The pole chip controls the pixel columns for image display in the display screen. By using the logic chip to control the pixel row for image display in the display screen, and/or using the power management chip and/or source chip to control the pixel column for image display in the display screen, the image can be controlled. Scanning and displaying images is performed in the display area, and scanning display in non-image display areas is reduced, so as to reduce power consumption of liquid crystal display products.

Of course, implementing any product or method of the present application does not necessarily need to achieve all the above-mentioned advantages at the same time.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present application, and those skilled in the art can also obtain other embodiments according to these drawings.

1 is a schematic diagram of data signal output in a non-image display area of a liquid crystal display product in the related art;

FIG. 2 is a schematic flow chart of the first type of display screen output control method provided by the embodiment of the present application;

Fig. 3 is a second schematic flow chart of the display screen output control method provided by the embodiment of the present application;

Fig. 4a is a schematic flow chart of a third display screen output control method provided by the embodiment of the present application;

Figure 4b is a working diagram of the start control signal and end control signal of the source chip Source IC;

Fig. 5a is a schematic flow chart of a fourth display screen output control method provided by the embodiment of the present application;

Figure 5b is a schematic diagram of providing working voltage for the source chip Source IC through the power management chip PMIC;

FIG. 6 is a schematic flowchart of a fifth type of display screen output control method provided by the embodiment of the present application;

FIG. 7 is a schematic flowchart of a sixth method of display screen output control method provided by the embodiment of the present application;

FIG. 8 is a schematic diagram of a seventh flow chart of a display screen output control method provided in an embodiment of the present application;

Fig. 9a is a schematic flowchart of an eighth type of display screen output control method provided by the embodiment of the present application;

Fig. 9b is a schematic diagram of the logic chip TCON controlling the output of the pulse signal TP;

Fig. 9c is a schematic diagram of data input in the image display area and non-image display area of the display screen;

FIG. 10 is a schematic diagram of the first structure of the display provided by the embodiment of the present application;

FIG. 11 is a schematic diagram of a second structure of a display provided by an embodiment of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art based on this application belong to the scope of protection of this application.

First, a brief description will be given of the data signal output in the non-image display area of the liquid crystal display product in the related art. As shown in Figure 1, TCON (timing controller, timing controller, also known as logic chip) is separated from source chip Source IC (Integrated Circuit Chip), and connected through FFC (Flexible Flat Cable, flexible flat cable). The logic chip TCON converts the video signal transmitted from the motherboard into a data signal, and transmits these data signals to the data-driven integrated circuit COF IC (Chip On Flex, chip-on-chip) to control when the driving circuit starts. The logic chip TCON also provides the drive signal for the gate chip Gate IC. The Gate IC is responsible for controlling the turn-on and turn-off of transistors in different rows according to the drive signal (row drive), and also provides the drive signal for the source chip Source IC. The data signal is transmitted to the source chip Source IC, and the source chip Source IC sends the data signal to the source of different columns of transistors (column driver), charges the liquid crystal capacitor, and connects to the display screen through the COF IC to realize display. At present, when the liquid crystal display product displays normally, refer to FIG. 1 , where the AA area (active area) is the pixel area. If a certain pixel area does not display an image, then this pixel area will display an L0 grayscale image, but this display method will increase the power consumption of the liquid crystal display product. The relevant explanation of the L0 gray scale is as follows. Each point on the display screen, that is, a pixel is composed of three sub-pixels of red, green, and blue (RGB). Make different light and shade controls respectively to "adjust" different colors. The more levels of intermediate light and shade, the more delicate the image effect that can be presented. Taking an 8-bit display screen as an example, it can display 256 brightness levels (2 to the 8th power), which can be called 256 gray levels. L represents the actual brightness, L0 represents the brightness with the grayscale value equal to 0, and L255 represents the brightness with the grayscale value equal to 255.

In order to reduce power consumption of liquid crystal display products, embodiments of the present application provide a method for controlling output of a display screen and a display.

Next, a display screen output control method provided in the embodiment of the present application will be described in detail, see FIG. 2, including the following steps:

Step S201, acquiring the set of pixel rows and/or the set of pixel columns to which the image display area in the display screen belongs.

In order to reduce the power consumption of liquid crystal display products, during normal display, the image display area can be controlled to display, and the non-image display area can be controlled not to display.

The pixel row set to which the image display area belongs includes each pixel row in the image display area, and the pixel column set to which the image display area belongs includes each pixel column in the image display area.

On the premise that the pixel columns in the image display area are displayed by controlling the pixel columns scanned and displayed in the display screen, the display of pixel columns in the non-display area can be reduced; or by controlling the pixel rows scanned and displayed in the display screen, in Under the premise that the pixel rows in the image display area are displayed, the display of the pixel rows in the non-display area is reduced; in one example, by controlling the pixel columns and pixel rows displayed in the display screen, the pixels in the image display area On the premise of displaying the columns and rows of pixels, the display of the columns and rows of pixels in the non-display area is reduced.

Step S202 , according to the set of pixel rows, use a logic chip to perform display control on the pixel rows for image display in the display screen.

The normal display of the image is realized through the data-driven integrated circuit COF IC. The COF IC receives the data signal and control signal provided by the front-end logic chip TCON, converts the digital signal into a corresponding analog gray-scale voltage signal through digital-to-analog conversion, and inputs it to the LCD In the pixels of the display screen, the rotation of the liquid crystal molecules is driven to realize the change of the brightness of the projected light. In the above analysis of related technologies, it is mentioned that "the logic chip TCON also provides the drive signal for the gate chip Gate IC, and the Gate IC is responsible for controlling the on and off of transistors in different rows according to the drive signal (row drive)". The TCON performs display control on pixel rows for image display in the display screen. In one example, the output of the pulse signal TP can be controlled by the logic chip TCON to control the display of the pixel row for image display. For the pixel row belonging to the image display area, the pulse signal TP outputs the first voltage signal, and for the pixel row belonging to the non-image display area. pixel row, the pulse signal TP outputs a second voltage signal. The first voltage signal may be at a high level or at a low level. Correspondingly, the polarity of the second voltage signal is opposite to that of the first voltage signal.

Step S203, determine the power management chip and/or source chip corresponding to the set of pixel columns, and use the power management chip and/or the source chip to control the pixel columns for image display in the display screen .

PMIC (Power Management IC, power management chip) is a semiconductor integrated circuit, mainly used to manage the power system, it can control and monitor the input and output of various voltages and currents in the power system, so as to ensure the stability and safety of the power system run.

The power management chip PMIC in this application is used to generate the digital working voltage DVDD and the analog working voltage AVDD, and provide the working voltage for the source chip Source IC. The source chip Source IC is used to receive the data signal transmitted by the logic chip TCON, and send the data signal to the source of different columns of transistors (column drive), to charge the liquid crystal capacitor, and connect to the display screen through the data drive integrated circuit COF IC. show.

The working voltage of the source chip Source IC can be controlled by the power management chip PMIC to control the pixel column for image display in the display screen, and the pixel column for image display in the display screen can be controlled by the source chip Source IC To control, the power management chip PMIC and the source chip Source IC can also be used to control the pixel columns for image display in the display screen.

In the embodiment of the present application, display control is performed on the pixel row for image display in the display screen by using a logic chip, and/or, the pixel row for image display in the display screen is controlled by a power management chip and/or a source chip By controlling the columns, the image display area can be controlled to scan and display images, and the scan display of non-image display areas can be reduced, so as to reduce the power consumption of liquid crystal display products.

In a possible implementation manner, referring to FIG. 3 , it is a second schematic flow chart of the display screen output control method provided in the embodiment of the present application. Step S203 is refined based on FIG. 2 , including the following steps:

Step S301 , generating a data signal through the logic chip according to the set of pixel columns, wherein the data signal includes a start column identifier and an end column identifier.

The pixel column set includes each pixel column in the image display area. Based on the pixel column set, TCON (logic chip) can determine which pixel columns need to be scanned and displayed, so as to further generate data signals; the data signal includes the start column identification and the end column identification, The start column identifier indicates the first pixel column of the image display area, and the end column identifier indicates the last pixel column of the image display area.

Step S302, sending the data signal to the source chip, and using the source chip to control the pixel columns for image display in the display screen according to the start column identifier and the end column identifier .

Use the Source IC (source chip) to display and control the pixel column for image display in the display screen according to the start column label and the end column label, and control the pixel column represented by the start column label and the end column label and the two Each pixel column between the pixel columns provides source signals, and other pixel columns do not provide source signals, so that the pixel columns in the image display area are scanned and displayed, and the pixel columns in the non-image display area are not scanned. scan display.

In the embodiment of the present application, the source chip is used to control the pixel columns for image display in the display screen according to the start column identifier and the end column identifier. In the case of scanning and displaying the pixel columns in the image display area, and The pixel columns in the non-image display area are not scanned and displayed, thereby saving the energy consumption of the display screen.

In a possible implementation, referring to FIG. 4a, it is a third schematic flowchart of the display screen output control method provided in the embodiment of the present application. Based on FIG. 3, step S301 and step S302 are respectively refined, including the following steps :

Step S401, for each source chip, according to the pixel column interval driven by the source chip and the set of pixel columns, determine the start column identifier and end column identifier of the source chip through the logic chip, and generate The unified standard interface USIT data signal of the source chip.

One source chip is used to drive multiple pixel columns (multiple pixel columns form a pixel column interval), and each source chip is used to provide source voltages for the pixel columns driven by itself. In an example, the range of pixel columns driven by a source chip can be column 1-column 6. When the set of pixel columns is column 5-column 22, the starting column of the source chip is column 5, and the end column is labeled is column 6; in an example, the range of pixel columns driven by a source chip can be column 7-column 12, when the set of pixel columns is column 5-column 22, the starting column of the source chip is column 7 , the end column is identified as column 12; in an example, the pixel column interval driven by a source chip can be column 19-column 24, when the set of pixel columns is column 5-column 22, the starting column of the source chip Identified as column 19 and the ending column is identified as column 22.

Modify the internal configuration package of the Source IC through the logic chip, and add the start column identification instruction and the end column identification instruction to the USIT data signal.

Step S402, for each source chip, through the logic chip, use the USIT transmission protocol to send the USIT data signal of the source chip to the source chip; use the source chip according to the received USIT data signal The start column identifier and the end column identifier control the pixel columns for image display in the display screen.

USIT is a P2P protocol (Point to Point Interface), its full name is Unified Standard Interface for TV, which is generally used for communication between the system chip/logic chip and the driver of the display product. USIT uses an embedded clock without a dedicated clock signal, so the transmission rate can be greatly improved, and now it can generally achieve 1.8-3.0G bps.

The USIT data signal is divided into a display data signal and a configuration control signal, and the configuration control signal is divided into a data polarity selection control signal (POL), a charge sharing mode selection control signal (MODE), and the like. Two new control signals can be created: Channel_Start (start column identifier) and Channel_End (end column identifier), as shown in Figure 4b, if the signal transmission is output in 960channel (channel) mode, then 2 ¹⁰ bit data volume is required to To control the start and end of Source IC channel of each source chip, the Channel_Start control signal and Channel_End control signal need 10 bits respectively. After the logic chip TCON IC sends the transmission instruction to the source chip Source IC, the Channel start control signal and end control signal of the source chip Source IC start to work. Among them, CSEL (Chip Selected) is the chip selection signal, INV (Invert) is the reverse signal, CLK (Clock) is the clock signal, PACMOD (Programmable Automation Control MODE) is the programmable automation control mode, N/A (Not Available/Available ) is not applicable/applicable, that is, the instruction is not used, GMA_OFS_MODE is the compensation cancellation selection mode, CSMODE (Charge SharingMODE Selection Control) is the control signal for the charge sharing mode selection, BDF (Bus Device Function) is the bus device function, POL (Polarity Selection Control) is the polarity selection control signal, FSTR (FileStream) is the data stream, SHL (Shift Logical Left) is the logical left shift instruction, DATAPOL (DATA Polarity Selection Control) is the data polarity selection control signal, POLC (Polarity Selection Control) Select the control signal for polarity. TH (High Level Time) means high level, and TL (Low Level Time) means low level. N ^th Frame Data is the frame data, SOL is the storage file, HBP (Horizontal back porch) is the start timing of the horizontal sync pulse, and 1H Line is the signal of one line.

In the embodiment of the present application, the pixel column for image display in the display screen is controlled through the start column identifier and the end column identifier in the USIT data signal received by the source chip.

In a possible implementation manner, referring to FIG. 5a, it is a fourth schematic flow chart of the display screen output control method provided in the embodiment of the present application. Based on FIG. 2, step S203 is refined, including the following steps:

Step S501 , respectively acquiring the intervals of pixel columns driven by each of the source chips.

Step S502 , according to each of the pixel column intervals and the pixel column set, determine a target source chip that needs to be powered on each of the source chips.

The source chip that needs to be powered is called the target source chip. In one example, the range of pixel columns driven by a certain source chip can be column 1-column 6. When the set of pixel columns is column 5-column 22, the source chip needs power supply; in one example, a certain source The range of pixel columns driven by the pole chip can be column 1-column 6. When the set of pixel columns is column 7-column 22, the source chip does not need power supply.

Step S503, supplying power to the target source chip through the power management chip, and controlling the pixel columns for image display in the display screen through the target source chip.

DVDD and AVDD jointly provide the working voltage for the source chip Source IC, DVDD provides the digital working voltage for the data-driven integrated circuit COF IC, and AVDD is the analog working voltage, which drives the transistor to turn on and off. DVDD/AVDD is generated by the power management chip PMIC. By customizing the power management chip PMIC, an independent working voltage is provided for each source chip Source IC, as shown in Figure 5b, so that the display can be controlled by the target source chip. The pixel column of the image display performs display control. In the non-image display area, the power management chip PMIC does not provide the operating voltage to the source chip Source IC; in the image display area, the power management chip PMIC provides the operating voltage to the source chip Source IC.

In the embodiment of this application, only the target source chip is powered, and other source chips other than the target source chip are not powered, that is, source chips that do not provide the source voltage required for image display are not powered , so that the power consumption of the display screen can be further reduced.

In a possible implementation, referring to FIG. 6 , it is a fifth schematic flow chart of the display screen output control method provided in the embodiment of the present application. Based on FIG. 5a, step S503 is refined, including the following steps:

Step S601 , generating a data signal through the logic chip according to the set of pixel columns, wherein the data signal includes a start column identifier and an end column identifier.

Step S602, sending the data signal to the source chip, and using the source chip to control the pixel columns for image display in the display screen according to the start column identifier and the end column identifier .

In the embodiment of the present application, the display control of the pixel column for image display in the display screen is performed through the power management chip and the source chip.

In a possible implementation, referring to FIG. 7 , it is a schematic flowchart of the sixth display screen output control method provided in the embodiment of the present application. Based on FIG. 6 , step S601 and step S602 are respectively refined, including the following steps :

Step S701, for each source chip, according to the pixel column interval driven by the source chip and the set of pixel columns, determine the start column identifier and end column identifier of the source chip through the logic chip, and generate The USIT data signal of the source chip.

Step S702, for each source chip, through the logic chip, use the USIT transmission protocol to send the USIT data signal of the source chip to the source chip; use the source chip according to the received USIT data signal The start column identifier and the end column identifier control the pixel columns for image display in the display screen.

In the embodiment of the present application, the display control of the pixel column for image display in the display screen is performed through the power management chip and the source chip.

In a possible implementation, referring to FIG. 8 , it is a seventh schematic flow chart of the display screen output control method provided in the embodiment of the present application. Step S202 is refined based on FIG. 2 , including the following steps:

Step S801, according to the set of pixel rows, use the image display detection module of the system chip to determine the pixel rows to be scanned.

By adding an image display detection module (essentially a software module) inside the SOC (System on Chip), it is used to detect pixel rows line by line. When it is detected that a certain pixel line does not display an image, determine the pixel Behavior is a non-scanning pixel row; when a certain pixel row is detected to display an image, it is determined that the pixel is a pixel row to be scanned.

In step S802, the logic chip controls the pulse signal to scan the pixel row to be scanned row by row, so as to control the display of the pixel row for image display in the display screen.

The pulse signal (TP, time pulse) is the control signal of the data latch (Line Latch), which is output by the logic chip TCON. The data latch is controlled by the pulse signal, and then the latch of the signal input to the source chip Source IC is controlled.

In the embodiment of the present application, the pulse signal is controlled by the logic chip to control the display of the pixel row for image display in the display screen.

In a possible implementation manner, referring to FIG. 9a, it is a schematic flowchart of an eighth display screen output control method provided in the embodiment of the present application. Based on FIG. 8, step S802 is refined, including the following steps:

Step S901 , outputting a first voltage signal through a logic chip control pulse signal, and performing progressive scanning on the pixel rows to be scanned, so as to perform display control on the pixel rows for image display in the display screen.

The pulse signal TP is a data output control signal, the rising edge latches the data signal input from the logic chip TCON to the source chip Source IC, and the falling edge controls the latched data signal to be released to the display.

The data latch is divided into data latch 1 (Line Latch1) at the input end and data latch 2 (Line Latch2) at the output end. In an example, the first voltage signal can be at a high level, and it can be that the high level of each pulse signal TP controls the output of one line of the display image, then at the rising edge of the pulse signal TP, Line Latch1 receives the data signal and latches it to Line In Latch2, at the falling edge of the pulse signal TP, the data signal is transferred to the next stage circuit, that is, the source chip SourceIC.

It is understandable that the low level of each pulse signal TP can also control the output of one line of the display image, then at the falling edge of the pulse signal TP, Line Latch1 receives the data signal and latches it into Line Latch2, and when the pulse signal TP rises Along the edge, the data signal is transferred to the next-level circuit, that is, the source chip Source IC.

Taking the high level of each pulse signal TP to control the output of one line of display image as an example, the image display detection module inside the system chip SOC performs line-by-line detection. When it is detected that a certain pixel line does not display an image, the pulse signal TP does not Output high level, when a certain pixel row is detected to display an image, the pulse signal TP outputs high level, and the output of the pulse signal TP is controlled by the logic chip TCON. As shown in Figure 9b, the logic chip TCON controls the pulse signal to output a high level to scan the row of pixels to be scanned (scanning area/image display area) line by line, and the control data signal is input to the source chip SourceIC to control the display screen. The display control is performed on the pixel row for image display; the logic chip TCON controls the pulse signal not to output high level, and then controls the data signal not to be input to the source chip Source IC, so that there is no data signal input in the non-scanning area. The specific illustration As shown in Figure 9c.

In the embodiment of the present application, the pulse signal is controlled by the logic chip to output the first voltage signal, and the pixel row to be scanned is scanned row by row, so as to control the display of the pixel row for image display in the display screen.

The embodiment of the present application also provides a display 1, as shown in FIG. 10 , including a source chip 11, a logic chip 12 and a power management chip 13. The display 1 is used to realize the display screen output described in any of the above embodiments. Control Method.

In a possible implementation manner, referring to FIG. 11 , the display 1 further includes a system chip 14 configured to determine the set of pixel rows and/or the set of pixel columns to which an image display area in the display screen belongs.

The pixel row set and/or the pixel column set to which the image display area in the display screen belongs is determined by the image display detection module of the system chip SOC.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Each embodiment in this specification is described in a related manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, refer to part of the description of the method embodiment.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application are included within the protection scope of this application.

Claims (10)

1. A display screen output control method, the method comprising:

acquiring a pixel row set and/or a pixel column set of an image display area in a display screen;

according to the pixel row set, utilizing a logic chip to display and control the pixel rows for displaying the image in the display screen;

and/or;

and determining a power management chip and/or a source chip corresponding to the pixel column set, and controlling the pixel columns for image display in the display screen by using the power management chip and/or the source chip.

2. The method according to claim 1, wherein the determining a power management chip and/or a source chip corresponding to the pixel column set, and controlling the pixel column for displaying the image in the display screen by using the power management chip and/or the source chip, includes:

generating a data signal through the logic chip according to the pixel column set, wherein the data signal comprises a start column identifier and an end column identifier;

and sending the data signal to the source chip, and controlling the pixel columns for displaying the image in the display screen by utilizing the source chip according to the starting column identifier and the ending column identifier.

3. The method of claim 2, wherein generating, by the logic chip, a data signal from the set of pixel columns comprises:

for each source chip, determining a starting column identifier and an ending column identifier of the source chip through the logic chip according to a pixel column interval driven by the source chip and the pixel column set, and generating a unified standard interface USIT data signal of the source chip;

the step of sending the data signal to the source chip, and controlling the pixel columns for displaying the image in the display screen by using the source chip according to the start column identifier and the end column identifier, including:

for each source chip, transmitting a USIT data signal of the source chip to the source chip by using a USIT transmission protocol through the logic chip; and controlling the pixel columns for displaying the image in the display screen by utilizing the source chip according to the start column identifier and the end column identifier in the received USIT data signal.

4. The method according to claim 1, wherein the determining a power management chip and/or a source chip corresponding to the pixel column set, and controlling the pixel column for displaying the image in the display screen by using the power management chip and/or the source chip, includes:

respectively acquiring pixel column intervals driven by the source chips;

determining a target source chip needing power supply in each source chip according to each pixel column interval and each pixel column set;

and supplying power to the target source electrode chip through a power management chip, and controlling pixel columns for displaying images in the display screen through the target source electrode chip.

5. The method of claim 4, wherein the controlling, by the target source chip, the pixel columns of the display screen for image display comprises:

generating a data signal through the logic chip according to the pixel column set, wherein the data signal comprises a start column identifier and an end column identifier;

and sending the data signal to the source chip, and controlling the pixel columns for displaying the image in the display screen by utilizing the source chip according to the starting column identifier and the ending column identifier.

6. The method of claim 5, wherein generating, by the logic chip, a data signal from the set of pixel columns comprises:

for each source chip, determining a start column identifier and an end column identifier of the source chip through the logic chip according to a pixel column interval driven by the source chip and the pixel column set, and generating a USIT data signal of the source chip;

the step of sending the data signal to the source chip, and controlling the pixel columns for displaying the image in the display screen by using the source chip according to the start column identifier and the end column identifier, including:

for each source chip, transmitting a USIT data signal of the source chip to the source chip by using a USIT transmission protocol through the logic chip; and controlling the pixel columns for displaying the image in the display screen by utilizing the source chip according to the start column identifier and the end column identifier in the received USIT data signal.

7. The method according to claim 1, wherein the displaying control of the pixel rows for displaying the image in the display screen by using the logic chip according to the pixel row set includes:

according to the pixel row set, determining a pixel row to be scanned by using an image display detection module of a system chip;

and scanning the pixel rows to be scanned line by a logic chip control pulse signal TP so as to display and control the pixel rows for displaying the image in the display screen.

8. The method according to claim 7, wherein the scanning the pixel row to be scanned line by the logic chip control pulse signal TP to perform display control on the pixel row in the display screen for image display, includes:

and outputting a first voltage signal through a logic chip control pulse signal TP, and scanning the pixel rows to be scanned line by line so as to perform display control on the pixel rows for displaying the image in the display screen.

9. A display comprising a source chip, a logic chip and a power management chip, the display being adapted to implement the method of any of claims 1-8.

10. The display of claim 9, further comprising a system chip for determining a set of pixel rows and/or a set of pixel columns to which an image display area in a display screen belongs.

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