CN115995962A - Current sensing circuit and corresponding DC-DC converter - Google Patents

Abstract

Embodiments of the present disclosure relate to a current sensing circuit and a corresponding DC-DC converter. The power switch current sensing circuit includes matched first and second transistors having sources connected to first and second terminals of the power switch, respectively. The current mirror has a first node coupled to the drain of the first transistor and a second node coupled to the drain of the second transistor. The current mirror sinks a current from the first node equal to the current flowing through the second transistor. The bias circuit supplies the same bias voltage to the control terminals of the first and second transistors. An output resistor is coupled between the first node and a reference voltage node. The difference between the current flowing through the first transistor and the current drawn by the current mirror circuit from the first node flows through the output resistor. The output voltage generated at the first node is representative of the current flowing through the power switch.

Description

Current sensing circuit and corresponding DC-DC converter

Priority claim

The present application claims the benefit of priority from italian patent application No.102021000026927 filed 10/20 of 2021, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law.

Technical Field

The present description relates to current sensing circuits that may be used in, for example, DC-DC converters.

Background

The operation of certain DC-DC converters known in the art relies on current control algorithms (e.g., peak current control or valley current control). To perform a current control algorithm, a current sensing circuit is typically provided in the DC-DC converter to sense and reproduce the waveform of the current flowing through the power switches of the converter.

As shown in fig. 1, the current I flowing through the power switch of the converter _SW Typically having a trapezoidal waveform (i.e. each current pulse includes a steep rising edge RE, a linear portion LP that can be increased or decreased, and a steep falling edge FE). Therefore, the current I is accurately sensed due to the high frequency component of the current signal _SW Can be challenging. In particular, if the current sensing circuit has a limited bandwidth, the current signal I _SW May be difficult to sense (e.g., track).

Certain current sensing circuits with wide bandwidths are known in the art. However, those solutions may suffer from one or more drawbacks, such as high quiescent current consumption, large silicon area occupation, and/or inability to sense bi-directional current (i.e., inability to sense both positive and negative current in the same branch).

Accordingly, there is a need in the art to provide improved current sensing circuits with wide bandwidths that aim to mitigate (e.g., overcome) one or more of the disadvantages of known solutions.

Disclosure of Invention

One or more embodiments may relate to a circuit.

One or more embodiments may relate to a corresponding DC-DC converter.

In one or more embodiments, the first transistor has a source terminal configured to be selectively coupled to a first terminal of the electronic power transistor switch, and the second transistor has a source terminal configured to be selectively coupled to a second terminal of the electronic power transistor switch. The second transistor has the same size as the first transistor. The current mirror circuit is coupled between the first node and the second node. The drain terminal of the first transistor is connected to the first node and the drain terminal of the second transistor is connected to the second node. The current mirror circuit is configured to sink a current from the first node equal to a current flowing through the second transistor. The bias circuit is coupled to the first transistor and the second transistor and is configured to provide the same bias voltage to the control terminal of the first transistor and the control terminal of the second transistor. An output resistor is coupled between the first node and the reference voltage node such that a difference between a current flowing through the first transistor and a current drawn from the first node by the current mirror circuit flows through the output resistor and generates an output voltage signal at the first node indicative of the current flowing through the electronic power transistor switch.

Thus, one or more embodiments facilitate accurately sensing current flowing through a power switch having a wide bandwidth.

In one or more embodiments, the current generator circuit may be arranged to inject an offset current into the output resistor. A positive offset can be generated in the output voltage signal.

In one or more embodiments, the first switch and the first resistive element may be arranged in series between the source terminal of the first transistor and the first terminal of the electronic power transistor switch. The second switch and the second resistive element may be arranged in series between the source terminal of the second transistor and the second terminal of the electronic power transistor switch. The first switch may be controllable to close in response to the electronic power transistor switch being on and to open in response to the electronic power transistor switch being off. The first switch, the second switch, the first resistive element, the second resistive element, and the current mirror circuit may be sized such that the amount of current flowing through the first transistor and the second transistor is the same when the current flowing through the electric power transistor switch is zero.

In one or more embodiments, the first switch and the second switch may have the same conductivity when in the closed state; the first resistive element and the second resistive element may have the same resistance value; the current mirror circuit may have 1: 1.

In one or more embodiments, the resistance values of the first and second resistive elements may be greater than the reciprocal of the transconductance values of the first and second transistors, optionally at least 10 times greater, optionally at least 20 times greater.

In one or more embodiments, the bias circuit may include a third transistor arranged in a cross-diode (i.e., diode-connected transistor) configuration and arranged in series with the bias current generator. The bias circuit may include a third switch and a third resistive element arranged in series between the source terminal of the third transistor and the second terminal of the electronic power transistor switch. The control terminal of the third transistor may be coupled to the control terminal of the first transistor and the control terminal of the second transistor.

In one or more embodiments, the third transistor may have the same size as the first transistor. The first switch, the second switch, and the third switch may have the same conductivity when in the closed state. The first, second and third resistive elements may have the same resistance value.

In one or more embodiments, the fourth switch may be disposed between the second terminal of the electronic power transistor switch and a node intermediate the first switch and the first resistive element. The fourth switch is controllable to be closed in response to the electronic power transistor switch being non-conductive and to be opened in response to the electronic power transistor switch being conductive.

In one or more embodiments, the current mirror circuit may include an enhanced cascode current mirror circuit. The first mirror transistor may have a drain terminal coupled to the first node. The second mirror transistor may be arranged in series to the first mirror transistor and may have a drain terminal coupled to a source terminal of the first mirror transistor. The third mirror transistor may have a drain terminal coupled to the second node. The fourth mirror transistor may be arranged in series to the third mirror transistor and may have a drain terminal coupled to the source terminal of the third mirror transistor. The gate terminal of the first mirror transistor may be connected to the gate terminal of the third mirror transistor, the gate terminal of the second mirror transistor may be connected to the gate terminal of the fourth mirror transistor, and the gate terminal of the fourth mirror transistor may be connected to the second node.

In one or more embodiments, the enhanced cascode current mirror circuit may include a first mirror resistor coupled in series to the second mirror transistor and a second mirror resistor coupled in series to the fourth mirror transistor. The first and second mirror resistances may optionally have the same resistance value.

In one or more embodiments, the bias current generator may include a cascode current generator including tracking transistors arranged in a cross diode configuration and having gate terminals connected to gate terminals of the first and third mirror transistors.

In one or more embodiments, the DC-DC converter may include an electronic power transistor switch disposed between an input node of the converter and an output node of the converter. A current sensing circuit in accordance with one or more embodiments may be coupled to an electronic power transistor switch of a converter. The control circuit of the converter may be configured to operate the electronic power transistor switch, couple the source terminal of the first transistor to the first terminal of the electronic power transistor switch in response to the electronic power transistor switch being conductive, and decouple the source terminal of the first transistor from the first terminal of the electronic power transistor switch in response to the electronic power transistor switch being non-conductive.

In one or more embodiments, the control circuit may be further configured to couple the source terminal of the first transistor to the second terminal of the electronic power transistor switch in response to the electronic power transistor switch not being conductive, and decouple the source terminal of the first transistor from the second terminal of the electronic power transistor switch in response to the electronic power transistor switch being conductive.

Drawings

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

fig. 1 is a timing chart showing waveforms of currents flowing through power switches of a DC-DC converter, and has been described above;

FIG. 2 is an exemplary circuit diagram of a DC-DC converter and a current sensing circuit configured to sense current flowing through a high side switch of the converter;

FIG. 3 is an exemplary circuit diagram of a DC-DC converter and a current sensing circuit configured to sense current flowing through a low side switch of the converter;

fig. 4 is a timing diagram showing a waveform of a current flowing through a power switch of the DC-DC converter and an output signal generated by the current sensing circuit shown in fig. 2 or 3;

fig. 5 is a timing chart showing waveforms of currents flowing through a load of a DC-DC converter operating in a Continuous Conduction Mode (CCM);

FIG. 6 is an exemplary circuit diagram of a current sensing circuit configured to sense current flowing through a high side switch of a DC-DC converter;

FIG. 7 is an exemplary circuit diagram of implementation details of a high-side current sensing circuit;

FIG. 8 is an exemplary circuit diagram of a current sensing circuit configured to sense current flowing through a low side switch of a DC-DC converter;

FIG. 9 is a timing diagram showing a comparison between waveforms of current flowing through a power switch of a DC-DC converter, an output signal generated by the current sensing circuit shown in FIG. 2 or FIG. 3, and an output signal generated by the current sensing circuit according to FIGS. 6-8; and

fig. 10 is a timing diagram showing a comparison between an output signal generated by the current sensing circuit shown in fig. 2 or 3 and an output signal generated by the current sensing circuit according to fig. 6-8, showing a current waveform flowing through a power switch of a DC-DC converter operating in a continuous conduction mode.

Detailed Description

In the following description, one or more specific details are set forth in order to provide a thorough understanding of examples of the embodiments described herein. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

Reference in the framework of this specification to "one embodiment" or "an embodiment" is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may occur in one or more points of the present specification do not necessarily refer to the same embodiment. Furthermore, the particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Headings/references used herein are provided for convenience only and thus do not limit the scope of protection or the scope of the embodiments.

In the drawings attached hereto, identical parts or elements are denoted by identical reference numerals/numerals unless the context indicates otherwise, and the corresponding description will not be repeated for the sake of brevity.

By way of introduction to the detailed description of the exemplary embodiments, reference may first be made to fig. 2, fig. 2 being an example of a DC-DC boost converter 10 and associated current sensing circuit 20, the current sensing circuit 20 being configured to sense current flowing through a high-side switch of the converter 10.

The converter 10 includes a converter circuit configured to receive an input DC voltage V _IN Is provided) and is input to node 102. An inductance L (e.g., an inductor) is disposed between the input node 102 and the intermediate node 104 of the converter 10. A high-side switch HS (e.g., a p-channel power MOS transistor) is arranged between the intermediate node 104 and the output node 106 of the converter 10. A low side switch LS (e.g., an n-channel power MOS transistor) is arranged at the intermediate node 104 and provides a reference voltage V _GND (e.g., 0V) between the reference or ground nodes 108 of the converter 10. Current I _HS Through high-side switch HS, current I _LS Through the low side switch LS. A capacitor (not visible in fig. 2) may be coupled between output node 106 and reference node 108 to operate converter 10. The high-side switch HS and the low-side switch LS are controlled by a control unit (not visible in fig. 2) of the converter 10 according to a known control scheme such that at the output node Generating an output DC voltage V at point 106 _OUT 。

The current sense circuit 20 relies on a replica-based architecture with a closed loop to sense the time-varying current I flowing through the high-side switch HS of the converter 10 _HS Is a waveform of (a). In particular, current sensing circuit 20 includes a replica HSr of high-side switch HS coupled between node 104 (e.g., at the drain terminal of replica power MOS transistor HSr) and an inverting input of operational amplifier 202, such as an error amplifier (e.g., at the source terminal of replica transistor HSr). The replica switch HSr is controlled by the same control signal received by the high-side switch HS: the gate terminals of transistors HS and HSr can be coupled to each other. The non-inverting input of the operational amplifier 202 is coupled downstream of the high-side switch HS (e.g., coupled to the source terminal of the transistor HS). The output signal of the operational amplifier 202 controls the conductivity of the first transistor M1, e.g. it is coupled to the gate terminal of the n-channel MOS transistor M1. The first current mirror circuit is arranged between the replica switch HSr, the source terminal of the transistor M1 and the reference node 108. Specifically, the first current mirror circuit includes an n-channel MOS transistor M2 and an n-channel MOS transistor M3, the n-channel MOS transistor M2 having a drain terminal coupled to the inverting input of the operational amplifier 202 and a source terminal coupled to the reference node 108, the n-channel MOS transistor M3 having a drain terminal coupled to the source terminal of the transistor M1 and a source terminal coupled to the reference node 108. The gate terminals of the transistors M2 and M3 are connected to each other and to the drain terminal of the transistor M3, so that the current flowing through the transistors M1 and M3 is mirrored to flow through the transistor M2. The second current mirror circuit is arranged between the drain terminal of transistor M1, the output node 110 of the current sensing circuit 20 and the output node 106 of the converter 10. Specifically, the second current mirror circuit includes a p-channel MOS transistor M4 and a p-channel MOS transistor M5, the p-channel MOS transistor M4 having a drain terminal coupled to the drain terminal of the transistor M1 and a source terminal coupled to the output node 106, the p-channel MOS transistor M5 having a drain terminal coupled to the output node 110 and a source terminal coupled to the output node 106. The gate terminals of transistors M4 and M5 are connected to each other and to the drain terminal of transistor M4 so that electricity flows through transistors M1 and M4 The flow is mirrored to flow through transistor M5. Resistor element R _S Coupled between the output node 110 of the current sensing circuit 20 and the reference node 108, so as to flow through the transistor M5 and the resistor R _S Generates a voltage V at the output node 110 _SENSE Which indicates the current I flowing through the high side switch HS of the converter 10 _HS 。

By way of further introduction, reference may be made to fig. 3, fig. 3 being an example of a circuit diagram of a DC-DC boost converter 10 and associated current sensing circuit 30, the current sensing circuit 30 being configured to sense current flowing through a low side switch of the converter 10.

The converter 10 is substantially the same as described with reference to fig. 2 and comprises the same components HS, LS, L and a capacitor coupled to the output node 106.

The current sensing circuit 30 relies on a replica-based architecture with a closed loop to sense the time-varying current I flowing through the low-side switch LS of the converter 10 _LS Is a waveform of (a). In particular, current sensing circuit 30 includes a replica LSr of low-side switch LS coupled between node 108 (e.g., at a source terminal of replica power MOS transistor LSr) and an inverting input of operational amplifier 302, such as an error amplifier (e.g., at a drain terminal of replica transistor LSr). The replica switch LSr is controlled by the same control signal of the low-side switch LS: although not visible in fig. 3 for ease of illustration only, the gate terminals of transistors LS and LSr may be coupled to each other. The non-inverting input of the operational amplifier 302 is coupled upstream of the low-side switch LS (e.g., coupled to the drain terminal of the transistor LS). The output signal of the operational amplifier 302 controls the conductivity of the first transistor M1, e.g., it is coupled to the gate terminal of the n-channel MOS transistor M1. The source terminal of transistor M1 is coupled to the inverting input of operational amplifier 302. The current mirror circuit comprising transistors M4 and M5 is arranged between the drain terminal of transistor M1, the output node 110 of the current sensing circuit 30 and the output node 106 of the converter 10, as described with reference to fig. 2. Similarly, a resistance element R _S Coupled between the output node 110 of the current sensing circuit 30 and the reference node 108 so as to flow through the transistor M5 and the resistor R _S Generates a voltage V at the output node 110 _SENSE Which indicates the current I flowing through the low side switch LS of the converter 10 _LS 。

The current sensing circuits 20 and 30 illustrated in fig. 2 and 3 may have one or more of the disadvantages discussed below.

A first disadvantage is that the bandwidth of such current sensing circuits may be limited in order to provide the necessary closed loop stability. This may result in distortion of the sensed trapezoidal current waveform as illustrated in fig. 4, fig. 4 being a graph illustrating the current (I _HS Or I _LS ) And the output signal V generated by the current sensing circuit 20 or 30 _SENSE A timing diagram of the comparison between. Due to bandwidth limitation, the output signal V _SENSE (solid line in FIG. 4) can be compared with the actual current waveform I _HS Or I _LS (dashed line in fig. 4) is substantially smoothed, resulting in poor accuracy of current sensing.

To increase the bandwidth of the current sensing circuit 20 or 30, the op-amp and replica branch may be biased with a large current. However, this approach may lead to a second disadvantage, namely that the high quiescent current consumption may not meet the design constraints of the low power DC-DC converter and/or the efficiency requirements under light loads.

A third disadvantage is that the current sensing circuit 20 or 30 requires an operational amplifier, a replica switch (e.g., replica transistor) and a replica branch, which results in a high silicon area footprint.

A fourth disadvantage is that the current sensing circuit 20 or 30 can only sense positive current flowing from node 104 to either output node 106 (high-side sensing) or to reference node 108 (low-side sensing). The inability to sense the reverse (negative) current flowing from the output node 106 (high-side sensing) or from the reference node 108 (low-side sensing) to the node 104 results in a loss of accuracy of the DC-DC converter operating in the forced Continuous Conduction Mode (CCM) where current reversal occurs with a light load. FIG. 5 is a diagram illustrating a clock period T _CK Load current I in upper unseen light load CCM _LOAD A timing diagram of a portion of (a): the positive area 51 is correctly sensed, while the negative area 52 is not.

Accordingly, one or more embodiments may provide different current sensing architectures (e.g., for applications in DC-DC converters) with the aim of alleviating one or more of the above-described drawbacks.

Fig. 6 is an exemplary circuit diagram of certain components of DC-DC boost converter 10 (see, e.g., high-side switch HS disposed between nodes 104 and 106) and associated current sensing circuit 60 configured to sense current flowing through high-side switch HS of converter 10. Other components of the converter 10 (e.g., the low-side switch LS, the inductor L, and the output capacitor) may be arranged substantially as discussed with reference to fig. 2, and are not shown in fig. 6 for ease of illustration only.

The current sensing circuit 60 includes a sensing circuit 62 (e.g., the "core" of the sensing portion) and a biasing circuit 64 (e.g., the reference arm). The sensing circuit 62 is configured to sense the current I flowing through the high-side switch HS _HS And generates an indication current I at a respective output node 620 _HS Voltage signal V of (2) _SENSE . The bias circuit 64 is configured to generate a fixed bias voltage for the sense circuit 62, as described below.

The sensing circuit 62 includes a first transistor P1 (e.g., a P-channel MOS transistor) having a source terminal that is selectively coupleable to the node 104 (e.g., to the drain terminal of the transistor HS). For example, the sensing circuit 62 may include a first resistor R1 (e.g., a resistor) coupled between the source terminal of the transistor P1 and the first terminal of the switch SW1 a. A second terminal of switch SW1a may be coupled to node 104. In addition, the sensing circuit 62 may include a second switch SW1b disposed between the resistor R1 and the output node 106 such that the source terminal of the transistor P1 may be selectively coupled to the output node 106 (e.g., to the source terminal of the transistor HS).

The sensing circuit 62 includes a second transistor P2 (e.g., a P-channel MOS transistor) having a source terminal that may be coupled to the output node 106 (e.g., to the source terminal of transistor HS). For example, the sensing circuit 62 may include a second resistor R2 (e.g., a resistor) coupled between the source terminal of the transistor P2 and the first terminal of the switch SW 2. A second terminal of the switch SW2 may be coupled to the output node 106. The gate terminals of transistors P1 and P2 may be coupled to each other to receive the same bias voltage.

The sense circuit 62 includes a current mirror circuit 66 disposed between the drain terminals of transistors P1 and P2 and a reference node 108. In particular, current mirror circuit 66 may include an n-channel MOS transistor 662 and an n-channel MOS transistor 664, with the drain terminal of n-channel MOS transistor 662 coupled to the drain terminal of transistor P1 (i.e., at node 620) and the source terminal coupled to reference node 108, the drain terminal of n-channel MOS transistor 664 coupled to the drain terminal of transistor P2 and the source terminal coupled to reference node 108. The gate terminals of transistors 662 and 664 are connected to each other and to the drain terminal of transistor 664 (e.g., to the drain terminal of transistor P2). It is further noted that a simple current mirror is described herein as an example of a possible implementation, and that any type of suitable current mirror architecture may be implemented in the current mirror circuit 66.

In one or more embodiments, the switches SW1a, SW1b, SW2, resistors R1, R2, transistors P1, P22, and current mirror 66 are sized to match such that when no current flows through the high-side switch HS (e.g., because the high-side switch HS is open), the same amount of current flows in both branches of the sensing circuit 62 (i.e., the same current flows through transistors P1 and P2). For example, in one or more embodiments, switches SW1a, SW1b, and SW2 may be substantially equal and may have the same resistance value in the closed state; resistors R1 and R2 may be substantially equal and may have the same resistance value R _IN The method comprises the steps of carrying out a first treatment on the surface of the The current mirror 66 may have a 1: a mirror factor of 1. Alternatively, resistors R1 and R2 may be different (e.g., their resistance ratio is equal to N), and current mirror 66 may have a value of 1: the mirror factor of N, thereby compensating for the different values of R1 and R2. Other combinations of the resistance values of switches SW1a, SW1b and SW2, as well as the resistance values of resistors R1 and R2 and the mirror factor of current mirror 66 are possible as long as the two branches of sensing circuit 62 match such that transistor 662 is configured to sink a current from node 620 that is equal to the current flowing through transistor P2.

In addition, the sensing circuit 62 includes a logic circuit coupled between the node 620 and the nodeOutput resistance R between reference nodes 108 _OUT (e.g., resistors). Thus, a current generated by the difference between the current flowing through transistor P1 and the current absorbed by transistor 662 is forced to flow through resistor R _OUT And generates an output signal V _SENSE . The sense circuit 62 may additionally include a trimmed current generator 68 coupled between a power rail (e.g., node 106) and a node 620 and configured to source a current I _TRIM Into node 620 (and thus through resistor R) _OUT ). Thus, the current generator 68 may output the signal V _SENSE Generates offset voltage V _OS ＝I _TRIM 〃R _OUT 。

The bias circuit 64 is configured to generate a fixed bias voltage for the (gate) terminals of the transistors P1 and P2. Specifically, biasing circuit 64 may include a third transistor P3 (e.g., a P-channel MOS transistor) having a source terminal that may be coupled to output node 106 (e.g., to the source terminal of transistor HS). For example, the biasing circuit 64 may include a third resistor R3 (e.g., a resistor) coupled between the source terminal of the transistor P3 and the first terminal of the switch SW 3. A second terminal of the switch SW3 may be coupled to the output node 106. The gate terminal of transistor P3 may be coupled to the gate terminals of transistors P1 and P2 and to the drain terminal of transistor P3 (i.e., P3 may be in a trans-diode configuration). The bias circuit 64 may include a current generator circuit 642 disposed between the drain terminal of the transistor P3 and the reference node 108. The current generator circuit 642 may be configured to set a fixed current I1 flowing through the transistor P3 such that the switch SW3, the resistor R3, the transistor P3 and the circuit 642 are at the output node 106 (wherein the voltage is fixed at V _OUT At) and a reference node 108 (where the voltage is fixed at V _GND Where) generates the gate voltages (e.g., bias voltages) of transistors P1 and P2.

In one or more embodiments as illustrated in FIG. 6, resistor R3 may be substantially equal to resistors R1 and R2, and thus may have a resistance value R _IN The method comprises the steps of carrying out a first treatment on the surface of the The switch SW3 may be substantially equal to the switches SW1a and SW2 and may have the same resistance value in the closed state. In this arrangementIn the middle, when no current flows through the high-side switch HS, the current flowing through the transistors P1 and P2 may be equal to I ₁ . Alternatively, the transistor P3 and the resistor R3 may be different in size from the transistors P1, P2 and the resistors R1, R2. For example, when R3>R1 and R3>R2 is a current higher than I through transistors P1 and P2 ₁ 。

The switches SW1a, SW1b may be controlled by a control circuit (not visible in fig. 6) of the converter 10, which control circuit also controls the operation of the high side switch HS. Thus, when the high side switch HS is closed (e.g., on) and current I _HS When flowing through switch SW1a, switch SW1a may be closed and switch SW1b may be opened, thereby creating a voltage drop V between node 104 and node 106 _DS ^HS . Conversely, when the high-side switch HS is open (e.g., open), the switch SW1a may be open and the switch SW1b may be closed. The switches SW2 and SW3 may remain permanently closed so that the switch HS is open at the high side (and correctly generates the zero output signal V _SENSE ＝V _OS ) The hold sense circuit 62 is also powered. The switches SW2 and SW3 may be sized to improve matching of the current flow lines (or branches) of the transistors P1, P2 and P3.

In essence, the sensing circuit 62 operates as an equivalent differential input stage comprising a series arrangement of P1, R1 and P2, R2. Equivalent transconductance g seen from node 104 _m ^EQ Can be calculated as g _m ^EQ ＝(1/g _m ^P +R _IN ) ^-1 Wherein g _m ^P Is the transconductance of transistors P1 and P2, R _IN Is the resistance value of the resistors R1 and R2. In one or more embodiments, the value R _IN Can be far more than 1/g _m ^P (e.g., by design) such that g _m ^EQ ≈1/R _IN (e.g., R _IN ＞10*1/g _m ^P ). Switches SW2 and SW3 may remain permanently closed (e.g., their control terminals may be open), providing a good match between the two branches of sensing circuit 62 and biasing circuit 64. As a result of the good matching, the voltage drop V across the high-side switch HS _DS ^HS Zero (i.e. when I _HS When=0),the same current I _UP Flows through both branches of the sensing circuit 62. According to various embodiments, the amount of current I _UP May be equal to or different from the current amount I ₁ 。

Thus, in one or more embodiments, when the high side switch HS is in an on state, switch SW1a may be closed and switch SW1b may be opened such that current I _UP Through transistor P1, where I _UP It can be calculated as:

thus, at voltage V _SENSE Dependent on voltage V _DS ^HS In the case of (a), the output signal V at node 620 _SENSE Can indicate the current I flowing through the high-side switch HS _HS ：

V _SENSE ＝I _TRIM ·R _OUT +(I _UP -I ₁ )·R _OUT

Wherein:

V _Os ＝I _TRIM ·R _OUT

thus, the output voltage V _SENSE Is fine tuning offset (V) _OS ) Adding a voltage V amplified by a constant gain G _DS ^HS And (3) summing. The gain G may also be independent of process, corner and temperature variations insofar as the gain G is the ratio between two resistors of the same type.

When the high-side switch HS is in a non-conductive state (e.g., open), the switch SW1a may be open and the switch SW1b may be closed such that the current I _UP And output voltage V _SENSE May have the following values:

I _UP ＝I ₁

V _SENSE ＝I _TRIM ·R _OUT ＝V _OS

in one or more embodiments, an offset voltage V is generated _OS The provision of the trimmed current generator 68 sets the dynamics of the output branches of the current mirror circuit 66, so it facilitates operation of the current mirror circuit 66 as an appropriate current mirror.

In addition, by appropriately setting the offset voltage V _OS One or more embodiments are also capable of detecting negative current in the high-side switch HS (i.e., current flowing from node 106 to node 104). As long as the output voltage V _SENSE The negative current I may be performed at a value above a minimum voltage (e.g., a lower threshold) that allows saturation of the output branch of the current mirror circuit 66 (e.g., saturation of the transistor 662) _HS Is a proper sensing of (a).

Fig. 7 is an exemplary circuit diagram of possible implementation details of current sensing circuit 60. Specifically, fig. 7 illustrates details of the current mirror circuit 66 and the bias circuit 64.

As shown in fig. 7, in one or more embodiments, the current mirror circuit 66 may include an enhanced (or modified) cascode current mirror. The n-channel MOS transistor 662a has a drain terminal coupled to the drain terminal of transistor P1 (i.e., at node 620) and a source terminal coupled to the drain terminal of another n-channel MOS transistor 662 b. A resistor 666 (e.g., a resistor) is coupled between the source terminal of transistor 662b and the reference node 108. n-channel MOS transistor 664a has a drain terminal coupled to the drain terminal of transistor P2 and a source terminal coupled to the drain terminal of another n-channel MOS transistor 664 b. A resistor 668 (e.g., a resistor) is coupled between the source terminal of transistor 664b and reference node 108. Resistances 666 and 668 may be equal. The gate terminals of the transistors 662a and 664a are connected to each other. The gate terminals of the transistors 662b and 664b are connected to each other and to the drain terminal of the transistor 664a (i.e., to the drain terminal of the transistor P2). Furthermore, the enhanced current mirror 66 and the components P1, P2, R1, R2, SW1a, SW1b, and SW2 may be sized to provide two matched legs in the sense circuit 62 Such that current mirror 66 is configured to sink a current from node 620 equal to the current flowing through transistor P2. Implementing the current mirror circuit 66 as an enhanced cascode current mirror as illustrated in fig. 7 may help reduce the voltage V _SENSE Error of the current mirror of the function of (c) and/or the output voltage V _SENSE Is extended dynamically. In addition, the resistors 666, 668 for degrading the current mirror can improve the current mirror matching and can be further reduced as the voltage V _SENSE Is a function of the current mirror error of (c).

In one or more embodiments, as shown in fig. 7, the bias circuit 64 may comprise a cascode bias circuit. Transistor 702 (e.g., an n-channel MOS transistor) in a cross-diode configuration has a drain terminal and a gate terminal coupled to the gate terminals of transistors 662a and 664 a. A resistor 704 matching (e.g., equal to) resistors 666 and 668 is coupled between the source terminal of transistor 702 and reference node 108. A cascode current mirror is coupled to the drain terminal of transistor 702 to force current through transistor 702. In particular, the cascode current mirror includes a p-channel MOS transistor 706 having a drain terminal coupled to the drain terminal of transistor 702 and a source terminal coupled to the drain terminal of another p-channel MOS transistor 708. The source terminal of transistor 708 is coupled to a supply voltage rail (e.g., node 106). The cascode current mirror includes a p-channel MOS transistor 710 having a source terminal coupled to a supply voltage rail and a drain terminal coupled to a source terminal of another p-channel MOS transistor 712. The gate terminals of transistors 708 and 710 are coupled to each other and to the drain terminal of transistor 710. The gate terminals of transistors 706 and 712 are coupled to each other and to the drain terminal of transistor 712. The cascode bias circuit may be configured to reduce the mirror error by setting the same drain-source voltage to transistors 708 and 710.

As shown in fig. 7, the current generator circuit 714 is configured to generate a current I _IN The drain terminal of the n-channel transistor 716 in the cross-diode configuration is injected. An n-channel transistor 718 has a gate terminal coupled to the gate terminal of transistor 716 and is arranged in series with transistors 710 and 712 such that current I _IN Through crystalBody transistors 710, 712, and 718 are mirrored, and then further mirrored through transistors 706 and 708. n-channel transistor 720 has a gate terminal coupled to the gate terminal of transistor 716 and is arranged in series with transistor P3 such that current I _IN Mirrored through transistor 720 and P3. Additional n- channel transistors 722 and 724 may be coupled in series to transistors 718 and 720, respectively. In the configuration shown in fig. 7, providing a transistor 702 in series with a resistor 704 helps track the corner and temperature variation of the current mirror 66.

Those skilled in the art will appreciate that the particular arrangement of the bias circuit 64 disclosed with reference to fig. 7 is discussed herein by way of non-limiting example only, as long as it is one of many possible implementations of bias circuit suitable for operating the current sensing circuit 60.

Fig. 6 and 7 discussed above are examples of one or more embodiments configured to sense current flowing through the high side switch HS of the DC-DC converter 10. Other embodiments may be configured to sense the current flowing through the low side switch LS of the DC-DC converter 10 by taking a complementary architecture, as illustrated in fig. 8.

Fig. 8 is an exemplary circuit diagram of certain components of DC-DC boost converter 10 (see, e.g., low-side switch LS disposed between nodes 104 and 108 and inductor L disposed between nodes 102 and 104) and associated current sensing circuit 80 configured to sense current flowing through low-side switch LS of converter 10. Other components of the converter 10 (e.g., the high-side switch HS and the output capacitor) may be arranged substantially as discussed with reference to fig. 2, and are not shown in fig. 8 for ease of illustration only. Those skilled in the art will appreciate that the circuit 80 illustrated in fig. 8 is substantially complementary to the circuit 60 illustrated in fig. 6 and operates according to the same principles; however, the circuit 80 will be described below.

The current sensing circuit 80 includes a sensing circuit 82 (e.g., the "core" of the sensing portion) and a biasing circuit 84 (e.g., the reference arm). The sensing circuit 82 is configured to sense the current I flowing through the low side switch LS _LS And generates an indication current I at a respective output node 820 _LS Voltage signal V of (2) _SENSE . The bias circuit 84 is configured to generateThe fixed bias voltage at the sensing circuit 82 is as follows.

The sensing circuit 82 includes a first transistor N1 (e.g., an N-channel MOS transistor) having a source terminal that is selectively coupleable to a node 104 (e.g., to a drain terminal of a transistor LS). For example, the sensing circuit 82 may include a first resistor R1 (e.g., a resistor) coupled between the source terminal of the transistor N1 and the first terminal of the switch SW1 a. A second terminal of switch SW1a may be coupled to node 104. In addition, the sensing circuit 82 may include a second switch SW1b disposed between the resistor R1 and the reference node 108 such that the source terminal of the transistor N1 may be selectively coupled to the reference node 108 (e.g., to the source terminal of the transistor LS).

The sensing circuit 82 includes a second transistor N2 (e.g., an N-channel MOS transistor) having a source terminal that is coupleable to a reference node 108 (e.g., to a source terminal of transistor LS). For example, the sensing circuit 82 may include a second resistor R2 (e.g., a resistor) coupled between the source terminal of the transistor N2 and the first terminal of the switch SW 2. A second terminal of the switch SW2 may be coupled to the reference node 108. The gate terminals of transistors N1 and N2 may be coupled to each other to receive the same bias voltage.

The sensing circuit 82 includes a current mirror circuit 86 disposed between the drain terminals of transistors N1 and N2 and a supply voltage node (e.g., node 106, or a chip input supply node, or a regulated voltage generated thereby). In particular, current mirror circuit 86 may include a p-channel MOS transistor 862 and a p-channel MOS transistor 864, p-channel MOS transistor 862 having a drain terminal coupled to the drain terminal of transistor N1 (i.e., at node 820) and a source terminal coupled to the supply voltage node, p-channel MOS transistor 864 having a drain terminal coupled to the drain terminal of transistor N2 and a source terminal coupled to the supply voltage node. The gate terminals of transistors 862 and 864 are connected to each other and to the drain terminal of transistor 864 (e.g., to the drain terminal of transistor N2). It is further noted that a simple current mirror is described herein as an example of a possible implementation, and that any type of suitable current mirror architecture may be implemented in the current mirror circuit 86.

As previously discussed with reference to fig. 6, in one or more embodiments, the switches SW1a, SW1b, SW2, resistors R1, R2, transistors N1, N2, and current mirror 86 are sized to match such that when no current flows through the low-side switch LS (e.g., because the low-side switch LS is open), the same amount of current flows in both branches of the sensing circuit 82 (i.e., the same current flows through transistors N1 and N2). For example, in one or more embodiments, switches SW1a, SW1b, and SW2 may be substantially equal and may have the same resistance value in the closed state; resistors R1 and R2 may be substantially equal and may have the same resistance value R _IN The method comprises the steps of carrying out a first treatment on the surface of the The current mirror 86 may have a 1: a mirror factor of 1. Alternatively, resistors R1 and R2 may be different (e.g., their resistance ratio is equal to N) and current mirror 86 may have a value of 1: the mirror factor of N, thereby compensating for the different values of R1 and R2. Other combinations of the resistance values of switches SW1a, SW1b and SW2 and the resistance values of resistors R1 and R2 and the resistance value of the mirror factor of current mirror 86 are possible as long as the two branches of sensing circuit 82 match such that transistor 862 is configured to inject a current into node 820 that is equal to the current flowing through transistor N2.

In addition, the sensing circuit 82 includes an output resistor R coupled between the node 820 and the reference node 108 _OUT (e.g., resistors). Thus, the current generated by the difference between the current injected by transistor 862 and the current flowing through transistor N1 is forced to flow through resistor R _OUT And generates an output signal V _SENSE . The sense circuit 82 may additionally include a trimmed current generator 88 coupled between the power rail and the node 820 and configured to source a current I _TRIM Into node 820 (and thus through resistor R) _OUT ). Thus, the current generator 88 may output the signal V _SENSE Generates offset voltage V _OS ＝I _TRIM 〃R _OUT 。

The bias circuit 84 is configured to generate a fixed bias voltage for the (gate) terminals of the transistors N1 and N2. Specifically, the bias circuit 84 may include a third transistor N3 (e.g., an N-channel MOS transistor) having a sourceThe terminal may be coupled to a reference node 108 (e.g., to a source terminal of a transistor LS). For example, the biasing circuit 84 may include a third resistor R3 (e.g., a resistor) coupled between the source terminal of the transistor N3 and the first terminal of the switch SW 3. A second terminal of switch SW3 may be coupled to reference node 108. The gate terminal of transistor N3 may be coupled to the gate terminals of transistors N1 and N2 and to the drain terminal of transistor N3 (i.e., N3 may be in a trans-diode configuration). The bias circuit 84 may include a current generator circuit 842 disposed between the drain terminal of the transistor N3 and the supply voltage node. The current generator circuit 842 may be configured to set a fixed current I flowing through the transistor N3 ₁ So that the circuit 842, the transistor N3, the resistor R3 and the switch SW3 are connected between the supply voltage node and the reference node 108 (wherein the voltage is fixed at V _GND ) The series arrangement therebetween generates the gate voltages (e.g., bias voltages) of transistors N1 and N2.

In one or more embodiments as illustrated in FIG. 8, resistor R3 may be substantially equal to resistors R1 and R2, and thus may have a resistance value R _IN The method comprises the steps of carrying out a first treatment on the surface of the The switch SW3 may be substantially equal to the switches SW1a and SW2 and may have the same resistance value in the closed state. In this configuration, when no current flows through the low-side switch LS, the current flowing through transistors N1 and N2 may be equal to I ₁ . Alternatively, the size of the transistor N3 and the resistor R3 may be different from the size of the transistors N1, N2 and the resistors R1, R2. For example, when R3>R1 and R3>R2 is a current higher than I through transistors N1 and N2 ₁ 。

The switches SW1a, SW1b may be controlled by a control circuit (not visible in fig. 7) of the converter 10, which control circuit also controls the operation of the low side switch LS. Thus, when the low side switch LS is closed (e.g., on) and current I _LS When flowing through switch SW1a, switch SW1a may be closed and switch SW1b may be opened, thereby creating a voltage drop V between node 104 and node 108 _DS ^LS . Conversely, when the low-side switch LS is open (e.g., open), the switch SW1a may be open and the switch SW1b may be closed. Switches SW2 and SW3 may remain permanently closed so that at the low side switch LS is open (and correctly zero is generatedOutput signal V _SENSE ＝V _OS ) The hold sense circuit 82 is also powered. The switches SW2 and SW3 may be sized to improve matching of the current flow lines (or branches) of transistors N1, N2 and N3.

In essence, the sensing circuit 82 operates as an equivalent differential input stage comprising a series arrangement of N1, R1 and N2, R2. Equivalent transconductance g seen from node 104 _m ^EQ Can be calculated as g _m ^EQ ＝(1/g _m ^N +R _IN ) -1, wherein g _m ^N Is the transconductance of transistors N1 and N2, R _IN Is the resistance value of the resistors R1 and R2. In one or more embodiments, the value R _IN Can be far more than 1/g _m ^N (e.g., by design) such that g _m ^EQ ≈1/R _IN (e.g., R _IN >10*1/g _m ^N ). Switches SW2 and SW3 may remain permanently closed (e.g., their control terminals may be open), providing a good match between the two branches of sensing circuit 82 and biasing circuit 84. As a result of the good matching, the voltage drop V across the low-side switch LS _DS ^LS Zero (i.e. when I _LS When=0), the same current I _DOWN Flows through both branches of the sensing circuit 82. According to various embodiments, the amount of current I _DOWN May be equal to or different from the current amount I ₁ 。

Thus, in one or more embodiments, when the low side switch LS is in an on state, switch SW1a may be closed and switch SW1b may be opened such that current I _DOWN Through transistor N1, where I _DOWN Can be calculated as:

thus, at voltage V _SENSE Dependent on voltage V _DS ^LS In the case of (a), the output signal V at node 820 _SENSE Can indicate the current I flowing through the low-side switch LS _LS ：

V _SENSE ＝I _TRIM ·R _OUT +(I ₁ -I _DOWN )·R _OUT

Wherein:

V _OS ＝I _TRIM ·R _OUT

thus, the output voltage V _SENSE Is fine tuning offset (V) _OS ) Adding a voltage V amplified by a constant gain G _DS ^LS A kind of electronic device. The gain G may also be independent of process, corner and temperature variations when it is within the range of the ratio between two resistors of the same type.

When the low side switch LS is in a non-conducting state (e.g., open), the switch SW1a may be open and the switch SW1b may be closed such that the current I _DOWN And output voltage V _SENSE May have the following values:

I _DOWN ＝I ₁

V _SENSE ＝I _TRIM ·R _OUT ＝V _OS

in one or more embodiments, generating an offset voltage V is provided _OS The trimmed current generator 88 of (a) sets the dynamic output of the branches of the current mirror circuit 86 so it facilitates the operation of the current mirror circuit 86 as an appropriate current mirror.

In addition, by appropriately setting the offset voltage V _OS One or more embodiments are also capable of sensing negative current in the low-side switch LS (i.e., current flowing from node 108 to node 104). As long as the output voltage V _SENSE The negative current I may be performed at a value above a minimum voltage (e.g., a lower threshold) that allows saturation of the output branch of the current mirror circuit 86 (e.g., saturation of transistor 862) _LS Is a proper sensing of (a).

Thus, one or more embodiments illustrated herein rely on open loop current sensing structures that have no limitations on loop stability. As a result, the bandwidth of the current sensing circuit is not limited by design constraints and, at least at a first approximation (only) by parasitic capacitance at the node.

One or more embodiments may advantageously provide an open loop current sensing structure that has a bandwidth that is not constrained by design constraints and that is greater than that achievable with known closed loop structures. The tracking of the Voltage Drop (VDS) across the high side switch HS and/or the low side switch LS may be more accurate, thereby helping to more accurately track the waveform of the current flowing in the power switches of the DC-DC converter. FIG. 9 is a current I flowing through a (high side or low side) switch _SW Examples of currents sensed by conventional closed loop structures (dashed lines), and currents sensed by one or more embodiments disclosed herein (solid lines).

One or more embodiments may advantageously facilitate sensing current flowing in a power switch in both directions, and thus may prove accurate in CCM under light load conditions where negative current needs to be sensed. FIG. 10 is a current I flowing through a (high side or low side) switch (dashed line) under certain conditions of CCM operation _SW Examples of waveforms of currents sensed by, for example, the closed loop structures (dot-dash lines) in fig. 2-3, and the current sensed by one or more of the embodiments (solid lines) shown in fig. 6-8.

One or more embodiments may advantageously operate at a lower bias current than that requested by closed loop structures known in the art, where large bandwidths may only be achieved with significant bias currents. Thus, one or more embodiments may provide lower quiescent current consumption.

One or more embodiments may additionally result in lower silicon area footprints if compared to structures known in the art, as long as they do not require dedicated error amplifier circuits and replica branches.

It should be noted that one or more embodiments of the current sensing circuits disclosed herein are applicable not only to boost DC-DC converters, but generally to any DC-DC converter topology (e.g., boost, buck-boost, etc.). More generally, it will be appreciated that one or more embodiments of a current sensing circuit are disclosed herein with reference to possible applications of the current sensing circuit in a DC-DC converter by way of non-limiting example only. The current sensing circuit according to one or more embodiments may be applied to any application (e.g., class D amplifier or over-current protection circuit) where a time-varying current waveform must be accurately sensed.

Additionally, it should be noted that one or more embodiments have been disclosed herein with reference to CMOS technology. It should be appreciated that one or more embodiments may alternatively rely on bipolar technology, such that any reference to the "source", "drain" and "gate" terminals of a "MOS" transistor may also be interpreted as "emitter", "collector" and "base" terminals of a "BJT" transistor.

Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of the protection.

The claims are an integral part of the technical teaching provided herein regarding the embodiments.

The scope of protection is determined by the appended claims.

Claims (17)

1. A circuit, comprising:

a first transistor having a source terminal configured to be selectively coupled to a first terminal of the electronic power transistor switch;

a second transistor having a source terminal configured to be selectively coupled to a second terminal of the electronic power transistor switch;

wherein the first transistor and the second transistor have the same size;

a current mirror circuit coupled between a first node and a second node, wherein a drain terminal of the first transistor is connected to the first node and a drain terminal of the second transistor is connected to the second node, the current mirror circuit configured to sink a current from the first node equal to a current flowing through the second transistor;

A bias circuit coupled to the first transistor and the second transistor, the bias circuit configured to provide the same bias voltage to a control terminal of the first transistor and a control terminal of the second transistor; and

an output resistor having a first terminal directly connected to the first node and a second terminal coupled to a reference voltage node;

wherein the output voltage signal at the first node is indicative of a current flowing through the electronic power transistor switch.

2. The circuit of claim 1, comprising a current generator circuit configured to inject an offset current into the first node to generate a positive offset in the output voltage signal.

3. The circuit of claim 1, comprising:

a first switch and a first resistor coupled in series between a source terminal of the first transistor and a first terminal of the electronic power transistor switch;

a second switch and a second resistor coupled in series between a source terminal of the second transistor and a second terminal of the electronic power transistor switch;

wherein the first switch is controllable to be closed when the electronic power transistor switch is on and to be open when the electronic power transistor switch is not on;

Wherein the first switch, the second switch, the first resistor, the second resistor, and the current mirror circuit are sized such that the same amount of current flows through the first transistor and the second transistor when the current flowing through the electronic power transistor switch is zero.

4. A circuit according to claim 3, wherein:

the first switch and the second switch have the same conductivity when in a closed state;

the first resistor and the second resistor have the same resistance value; and

the current mirror circuit has 1: 1.

5. The circuit of claim 3, wherein the same resistance value of the first resistor and the second resistor is a factor of two greater than the reciprocal of the same transconductance value of the first transistor and the second transistor.

6. The circuit of claim 5, wherein the factor is at least 10.

7. The circuit of claim 5, wherein the factor is at least 20.

8. The circuit of claim 3, wherein the bias circuit comprises:

a third transistor in a cross diode configuration and arranged in series with the bias current generator; and

A third switch and a third resistor coupled in series between a source terminal of the third transistor and a second terminal of the electronic power transistor switch; and

wherein a control terminal of the third transistor is coupled to a control terminal of the first transistor and a control terminal of the second transistor.

9. The circuit of claim 8, wherein:

the third transistor has the same size as the first transistor;

the first switch, the second switch, and the third switch have the same conductivity when in a closed state; and

the first resistor, the second resistor, and the third resistor have the same resistance value.

10. The circuit of claim 8, further comprising a fourth switch coupled between the second terminal of the electronic power transistor switch and a node intermediate the first switch and the first resistor;

wherein the fourth switch is controlled to be closed when the electronic power transistor switch is non-conductive and to be open when the electronic power transistor switch is conductive.

11. The circuit of claim 1, wherein the current mirror circuit comprises:

A first mirror transistor having a drain terminal coupled to the first node;

a second mirror transistor coupled in series to the first mirror transistor and having a drain terminal coupled to a source terminal of the first mirror transistor;

a third mirror transistor having a drain terminal coupled to the second node;

a fourth mirror transistor coupled in series to the third mirror transistor and having a drain terminal coupled to the source terminal of the third mirror transistor;

wherein a gate terminal of the first mirror transistor is connected to a gate terminal of the third mirror transistor, a gate terminal of the second mirror transistor is connected to a gate terminal of the fourth mirror transistor, and a gate terminal of the fourth mirror transistor is connected to the second node.

12. The circuit of claim 11, wherein the current mirror circuit further comprises a first mirror resistor coupled in series to the second mirror transistor and a second mirror resistor coupled in series to the fourth mirror transistor, the first and second mirror resistors having the same resistance value.

13. The circuit of claim 11, wherein the bias current generator comprises a cascode current generator comprising tracking transistors arranged in a cross diode configuration, and the cascode current generator has a gate terminal connected to gate terminals of the first and third mirror transistors.

14. The circuit of claim 1, further comprising a control circuit configured to:

operating the electronic power transistor switch;

coupling the source terminal of the first transistor to a first terminal of the electronic power transistor switch in response to the electronic power transistor switch being turned on; and

the source terminal of the first transistor is decoupled from a first terminal of the electronic power transistor switch in response to the electronic power transistor switch not being conductive.

15. The circuit of claim 14, wherein the control circuit is further configured to:

coupling the source terminal of the first transistor to a second terminal of the electronic power transistor switch in response to the electronic power transistor switch not being conductive; and

the source terminal of the first transistor is decoupled from a second terminal of the electronic power transistor switch in response to the electronic power transistor switch being turned on.

16. A DC-DC converter, comprising:

an electronic power transistor switch coupled between the input node and the output node;

the current sensing circuit of claim 1, coupled to the electronic power transistor switch; and

Control circuitry configured to:

operating the electronic power transistor switch;

coupling a source terminal of a first transistor to a first terminal of the electronic power transistor switch through a first resistor in response to the electronic power transistor switch being turned on; and

the source terminal of the first transistor is decoupled from a first terminal of the electronic power transistor switch in response to the electronic power transistor switch not being conductive.

17. The DC-DC converter of claim 16, wherein the control circuit is further configured to:

coupling the source terminal of the first transistor to a second terminal of the electronic power transistor switch through a second resistor in response to the electronic power transistor switch not being conductive; and

the source terminal of the first transistor is decoupled from a second terminal of the electronic power transistor switch in response to the electronic power transistor switch being turned on.

Images