CN116013967A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a relatively fixed first MOS unit and a second MOS unit; the side of the first MOS unit facing the second MOS unit has a first A drain, the side away from the second MOS unit has a first gate and a first source; the side of the second MOS unit facing the first MOS unit has a second drain, away from the One side of the first MOS unit has a second gate and a second source; wherein, the first drain is connected and fixed to the second drain. The technical solution of the present application can not only greatly reduce the occupied area, but also solve the problem of uneven current density caused by the 90° corner of the current path of the traditional planar double MOS tube, and has low manufacturing cost and high reliability.

Description

Semiconductor device and manufacturing method thereof

technical field

The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

With the rapid development of integrated circuits, the integration of chips is getting higher and higher, and the size of components is getting smaller and smaller. The various effects caused by the high density and small size of components have an increasing impact on the manufacturing process of semiconductor devices. Prominent, new process improvements are often required for small-size components.

A metal oxide semiconductor transistor (MOS transistor) is an important basic component in an integrated circuit, which is mainly composed of a semiconductor substrate, the first layer of polysilicon, the second layer of polysilicon, the sidewall spacer layer of the first layer of polysilicon, the source /Drain doped region and isolation region. In the prior art, multiple MOS units in a MOS device are all located on the same plane, and the reliability is poor.

Contents of the invention

In view of this, the present invention provides a semiconductor device and its manufacturing method, which can not only greatly reduce the occupied area, but also solve the problems of uneven current density caused by the 90° corner of the current path of the traditional planar double MOS tube, and make Low cost and high reliability.

In order to achieve the above object, the application provides the following technical solutions:

A semiconductor device, the semiconductor device comprising:

Relatively fixed first MOS unit and second MOS unit;

A side of the first MOS unit facing the second MOS unit has a first drain, and a side away from the second MOS unit has a first gate and a first source;

The second MOS unit has a second drain on a side facing the first MOS unit, and has a second gate and a second source on a side away from the first MOS unit;

Wherein, the first drain and the second drain are relatively connected and fixed.

Preferably, in the above-mentioned semiconductor device, both the first drain and the second drain are metal;

The first drain and the second drain are fixed by eutectic bonding or reflow soldering bonding.

Preferably, in the above-mentioned semiconductor device, the first MOS unit includes: a first semiconductor substrate; the first drain located on one side of the first semiconductor substrate; the first epitaxial layer on the other side; the first gate and the first source located in the surface of the first epitaxial layer facing away from the first semiconductor substrate;

The second MOS unit includes: a second semiconductor substrate; the second drain on one side of the second semiconductor substrate; a second epitaxial layer on the other side of the second semiconductor substrate; The second epitaxial layer is away from the second gate and the second source in one side surface of the second semiconductor substrate.

Preferably, in the above semiconductor device, the first MOS unit is NMOS, and both the first semiconductor substrate and the first epitaxial layer are N-type doped;

Or, the first MOS unit is PMOS, and both the first semiconductor substrate and the first epitaxial layer are P-type doped.

Preferably, in the above semiconductor device, the second MOS unit is NMOS, and both the second semiconductor substrate and the second epitaxial layer are N-type doped;

Or, the second MOS unit is PMOS, and both the second semiconductor substrate and the second epitaxial layer are P-type doped.

Preferably, in the above semiconductor device, the first gate has two first sub-gates; the surface of the first epitaxial layer away from the first semiconductor substrate has two first trenches; One of the first sub-gates is respectively arranged in the first trench, and there is a first gate dielectric layer between the first sub-gate and the first trench; between the two first trenches There is a first blind hole between them, and the first source is located in the first blind hole;

The second gate has two second sub-gates; the surface of the second epitaxial layer away from the second semiconductor substrate has two second trenches; one For the second sub-gate, there is a second gate dielectric layer between the second sub-gate and the second trench; there is a second blind hole between the two second trenches, and the first Two sources are located in the second blind hole.

Preferably, in the above-mentioned semiconductor device, the two first sub-gates are arranged symmetrically on both sides of the first source;

The two second sub-gates are arranged symmetrically on both sides of the second source.

The present application also provides a method for manufacturing a semiconductor device as described above, the method comprising:

forming a plurality of first MOS units on a first wafer, and forming a plurality of second MOS units on a second wafer;

connecting and fixing the first wafer to the second wafer; connecting and fixing the first MOS unit to the second MOS unit one by one;

Carrying out dicing and dividing the two wafers to form a plurality of the semiconductor devices, the semiconductor devices including the first MOS unit and the second MOS unit which are relatively connected and fixed;

Wherein, the side of the first MOS unit facing the second MOS unit has a first drain, and the side away from the second MOS unit has a first gate and a first source; the second MOS The side of the unit facing the first MOS unit has a second drain, and the side away from the first MOS unit has a second gate and a second source; the first drain and the second drain The poles are fixed relative to the connection.

Preferably, in the above manufacturing method, the first wafer includes: a first semiconductor substrate and a first epitaxial layer located on the surface of the first semiconductor substrate; the first epitaxial layer has a plurality of The first device region corresponding to the first MOS unit one-to-one;

The method for forming the first MOS unit on the first wafer includes:

forming the first source and the first gate in the first device region;

After thinning the surface of the first semiconductor substrate away from the first epitaxial layer, a first metal layer is formed on the surface, and the first metal layer includes a plurality of of the first drain.

Preferably, in the above manufacturing method, the second wafer includes: a second semiconductor substrate and a second epitaxial layer located on the surface of the second semiconductor substrate; the second epitaxial layer has a plurality of The second device area corresponding to the second MOS unit one-to-one;

The method for forming the second MOS unit on the second wafer includes:

forming the second source and the second gate in the second device region;

After thinning the surface of the second semiconductor substrate away from the second epitaxial layer, a second metal layer is formed on the surface, and the second metal layer includes a plurality of of the second drain.

It can be seen from the above description that in the semiconductor device and its manufacturing method provided by the technical solution of the present invention, by designing a 3D double MOS stack structure, the first MOS unit and the second MOS unit are relatively connected and fixed, and are connected by eutectic bonding or reflow soldering. The first drain and the second drain are relatively connected and fixed by means of bonding, so that the current paths of the dual MOS drain terminals are perpendicular to each other. Compared with the prior art, the technical solution of the present invention can not only greatly reduce the occupied area, but also solve the problem of uneven current density caused by the 90° corner of the current path of the traditional planar double MOS tube, and has low manufacturing cost and high reliability.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present application, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

The structures, proportions, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification, for those who are familiar with this technology to understand and read, and are not used to limit the conditions that can be implemented in this application, so Without technical substantive significance, any modification of the structure, change of the proportional relationship or adjustment of the size shall still fall within the technology disclosed in the application without affecting the effect and purpose of the application. within the scope of the content.

Fig. 1 is a sectional view of a planar double MOS tube;

Fig. 2 is the equivalent circuit diagram of the double MOS transistor shown in Fig. 1;

FIG. 3 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

FIG. 4 is a flow chart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention;

5-8 are a flow chart of a process for forming a first MOS unit provided by an embodiment of the present invention;

9-12 are a flow chart of a process for forming a second MOS unit provided by an embodiment of the present invention;

FIG. 13 is a cross-sectional view after the first wafer and the second wafer are connected and fixed according to the embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

Eutectic technology refers to the cooling, solidification, and crystallization of an alloy liquid of a certain composition at the eutectic reaction temperature into a mixture of two or more dense crystals. Simple binary alloys can be represented by the general formula La+β. Alloy structures that deviate from the eutectic composition are hypoeutectic or hypereutectic. The eutectic adopts mutual excitation nucleation, and the dendritic pro-eutectic structure is first precipitated from the liquid, and then the liquid between the dendrites solidifies into a eutectic structure, which grows alternately through branches and bridges, forming a layered shape; by short-range separation and diffusion , grow up, the typical eutectic structure is lamellar or rod-like; the epigenetic structure is striped, dotted or helical; the atypical eutectic is two independent nucleation interfaces. The phase is easy to produce divorced eutectic, that is, one phase in the eutectic grows vertically around the primary phase. The eutectic alloy has a low melting point and is easy to flow and cast; the pressure processing and welding performance is poor, and the cutting performance is good.

The reflow soldering process is that when the circuit board with printed solder paste and good components enters the reflow furnace, the circuit board is driven by the reflow rail transport chain and passes through the preheating zone, heat preservation zone, welding zone, and cooling zone of reflow soldering in sequence. , After the temperature changes in the four temperature zones of reflow soldering, the reflow soldering process of the circuit board is completed.

At present, no "back-to-back" 3D structure has been found in the design of dual MOS transistors in the market. Multiple MOS units in the same MOS device are located on the same plane, and the reliability is poor.

The current technology generally uses a planar double MOS transistor as shown in FIG. 1 , and FIG. 1 is a cut-away view of a planar double MOS transistor. As shown in FIG. 1 , the planar dual MOS transistor includes a first MOS unit M1 and a second MOS unit M2 , and the first MOS unit M1 and the second MOS unit M2 are located on the same plane.

The first MOS unit M1 includes a first semiconductor substrate 01, a first drain 02 located on one side of the first semiconductor substrate 01, and a first epitaxial layer 09 located on the other side of the first semiconductor substrate 01. An epitaxial layer 09 has a first gate 03 and a first source 04 on the side surface away from the first semiconductor substrate 01, wherein the first gate 03 has two first sub-gates, and the first The source 04 is located between the two first sub-gates.

The second MOS unit M2 includes a second semiconductor substrate 05, a second drain 06 located on one side of the second semiconductor substrate 05, and a second epitaxial layer 00 located on the other side of the second semiconductor substrate 05. There is a second gate 07 and a second source 08 in the surface of the second epitaxial layer 00 away from the second semiconductor substrate 05, wherein the second gate 07 has two second sub-gates, and the second The source 08 is located between the two second sub-gates.

Wherein, the first drain 02 and the second drain 06 are of an integral structure, which are different parts of the same metal layer; the first semiconductor substrate 01 and the second semiconductor substrate 05 are of an integral structure, which are the same semiconductor substrate Different parts of the bottom; the first epitaxial layer 09 and the second epitaxial layer 00 are integrated structures, which are different parts of the same epitaxial layer, and corresponding ion doping is performed based on the types of the two MOS units. The arrows shown in Figure 1 indicate the current direction.

In the method shown in Figure 1, the current flowing from the drain terminal of the second MOS unit M2 to the drain terminal of the first MOS unit M1 passes through the equivalent resistance of the epitaxial layer, the equivalent resistance of the substrate and the equivalent resistance of the back drain metal. The latter are connected in parallel to the drain of the first MOS unit M1 to complete the first half of the path. At this time, due to the difference in the distribution of the three resistivities, the difference in resistance value causes uneven current distribution. When the current reaches the area of the first MOS unit M1, the effect of the current in the first half is reversed, and the total drain current is redistributed in the channels and sources of the cells of the first MOS unit M1 according to the principle of the shortest path. The current in the whole process will experience two half-way 90° turnings and uneven current density due to the difference in parallel resistance. The cumulative effect is reflected in the increase of the on-resistance Rdson, which deviates from the theoretical value. A series of reliability problems caused by local heat concentration degrade reliability performance.

As shown in Figure 2, Figure 2 is the equivalent circuit diagram of the double MOS transistor shown in Figure 1. In Figure 2, S1 is the first source, S2 is the second source, G1 is the first gate, and G2 is the second gate. pole, Rg is the gate drive resistor, which means the resistor integrated and connected to the gate of the MOS transistor, multiple diodes are equivalent diodes in the MOS transistor, the drain connection area of the first MOS unit M1 and the second MOS unit M2 is shown in Fig. In the area indicated by the dotted circle in 2, the efficiency of the current path in this area is low, and there are problems such as the above-mentioned current turning point, the difference in the resistivity distribution of the equivalent resistance, and the local concentration of the current.

Therefore, in order to solve the above problems, the present invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprising:

Relatively fixed first MOS unit and second MOS unit;

A side of the first MOS unit facing the second MOS unit has a first drain, and a side away from the second MOS unit has a first gate and a first source;

The second MOS unit has a second drain on a side facing the first MOS unit, and has a second gate and a second source on a side away from the first MOS unit;

Wherein, the first drain and the second drain are relatively connected and fixed.

It can be seen from the above description that in the semiconductor device and its manufacturing method provided by the technical solution of the present invention, by designing a 3D double MOS stack structure, the first MOS unit and the second MOS unit are relatively connected and fixed, and are connected by eutectic bonding or reflow soldering. The first drain and the second drain are relatively connected and fixed by means of bonding, so that the current paths of the dual MOS drain terminals are perpendicular to each other. Compared with the prior art, the technical solution of the present invention can not only greatly reduce the occupied area, but also solve the problem of uneven current density caused by the 90° corner of the current path of the traditional planar double MOS tube, and has low manufacturing cost and high reliability.

In order to make the above objects, features and advantages of the present application more obvious and comprehensible, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

Referring to FIG. 3, FIG. 3 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention. As shown in FIG. 3, the semiconductor device includes:

Relatively fixed first MOS unit 10 and second MOS unit 20;

A side of the first MOS unit 10 facing the second MOS unit 20 has a first drain 11, and a side away from the second MOS unit 20 has a first gate 12 and a first source 13;

The second MOS unit 20 has a second drain 21 on a side facing the first MOS unit 10, and has a second gate 22 and a second source 23 on a side away from the first MOS unit 10;

Wherein, the first drain 11 and the second drain 21 are relatively connected and fixed.

In the embodiment of the present invention, both the first drain 11 and the second drain 21 are metal; the first drain 11 and the second drain 21 can be fixed by eutectic bonding, or Reflow soldering bonding fixation, or conductive adhesive connection fixation.

As shown in FIG. 3, the first MOS unit 10 includes: a first semiconductor substrate 14; the first drain 11 located on one side of the first semiconductor substrate 14; 14 on the other side of the first epitaxial layer 15 ; the first gate 12 and the first source 13 located on the surface of the first epitaxial layer 15 facing away from the first semiconductor substrate 14 .

Wherein, the first gate 12 has two first sub-gates; the surface of the first epitaxial layer 15 away from the first semiconductor substrate 14 has two first grooves; the first groove One of the first sub-gates is respectively arranged inside, and there is a first gate dielectric layer 16 between the first sub-gates and the first trench, and the filling surface of the first sub-gates is covered with the first In the first trenches of the gate dielectric layer 16 ; there is a first blind hole between the two first trenches, and the first source 13 is located in the first blind hole.

Wherein, the two first sub-gates are arranged symmetrically on both sides of the first source 13 . The first source 13 may be formed through an ion implantation process. A first trench is formed by an etching process, and after a gate oxide layer is formed on the surface of the first trench, the first gate 12 is formed in the first groove by an epitaxial process.

The first sub-gate, the first source 13 and the first drain 11 can form a MOS cell, so two identical MOS cells can be formed in the first MOS unit 10 and the second MOS unit 20, which facilitates the process. Preparation and circuit interconnection and driving.

It should be noted that the depth of the first blind hole is smaller than the depth of the first groove. The first blind hole can be in any shape, not limited to the rectangle shown in the figure, and can be set based on requirements.

In the embodiment of the present invention, the first MOS unit 10 may be NMOS, and both the first semiconductor substrate 14 and the first epitaxial layer 15 are N-type doped; or, the first MOS unit 10 may be It is PMOS, and both the first semiconductor substrate 14 and the first epitaxial layer 15 are P-type doped.

As shown in FIG. 3, the second MOS unit 20 includes: a second semiconductor substrate 24; the second drain 21 located on one side of the second semiconductor substrate 24; 24 on the other side of the second epitaxial layer 25 ; the second gate 22 and the second source 23 located on the surface of the second epitaxial layer 25 facing away from the second semiconductor substrate 24 .

Wherein, the second gate 22 has two second sub-gates; the surface of the second epitaxial layer 25 away from the second semiconductor substrate 24 has two second grooves; the second groove One of the second sub-gates is respectively arranged inside, and there is a second gate dielectric layer 26 between the second sub-gates and the second trench, and the filling surface of the second sub-gates is covered with the second In the second trenches of the gate dielectric layer 26 ; there is a second blind hole between the two second trenches, and the second source 23 is located in the second blind hole.

Wherein, the two second sub-gates are arranged symmetrically on both sides of the second source 23 . The second source 23 may be formed through an ion implantation process. A second trench is formed by an etching process, and after a gate oxide layer is formed on the surface of the second trench, the second gate 22 is formed in the second groove by an epitaxial process.

It should be noted that the depth of the second blind hole is smaller than the depth of the second groove. The second blind hole can be in any shape, not limited to the rectangle shown in the figure, and can be set based on requirements.

In the embodiment of the present invention, the second MOS unit 20 may be NMOS, and both the second semiconductor substrate 24 and the second epitaxial layer 25 are N-type doped; or, the second MOS unit 20 may be It is PMOS, and both the second semiconductor substrate 24 and the second epitaxial layer 25 are P-type doped.

The equivalent circuit diagram of the semiconductor device with 3D double MOS transistors in this application is also shown in Figure 2. The equivalent circuit diagram of the semiconductor device in this scheme remains unchanged relative to the existing structure, the current path at the position of the dotted circle becomes shorter, and the impedance decreases. It can improve the current uniformity and increase the current.

In the embodiment of the present invention, the semiconductor device has two three-dimensionally stacked MOS units, the first MOS unit 10 and the second MOS unit 20 are relatively connected and fixed, and the first MOS unit is bonded by eutectic bonding or reflow soldering. The drain of the unit 10 and the drain of the second MOS unit 20 are relatively connected and fixed, so that the current paths of the dual MOS drain terminals are perpendicular to each other. Compared with the existing technology, not only can the occupied area be greatly reduced, but also the problem of uneven current density caused by the 90° corner of the current path of the traditional planar double MOS tube can be solved, and the manufacturing cost is low and the reliability is high.

Through the present invention, the current in the three-dimensionally stacked dual MOS unit body can no longer pass through two 90° phase changes, and the current is directly transmitted vertically downward. In the traditional planar dual MOS unit, the current turning point, the resistivity distribution difference of equivalent resistance and These problems of local concentration of current are solved, and at the same time, the occupied area can be greatly reduced, and the occupied area can also be benefited during application.

Based on the above embodiment, another embodiment of the present invention also provides a method for manufacturing a semiconductor device as described in the above embodiment, as shown in Figure 3 and Figure 4, Figure 4 is a semiconductor device provided by an embodiment of the present invention A flow chart of a production method, the production method comprising:

Step S11: forming a plurality of first MOS units 10 on a first wafer, and forming a plurality of second MOS units 20 on a second wafer;

Step S12: relatively connecting and fixing the first wafer and the second wafer; connecting and fixing the first MOS unit 10 and the second MOS unit 20 one by one;

Step S13: Carry out dicing and division on the two wafers to form a plurality of semiconductor devices, as shown in FIG. 3 , the semiconductor device includes the first MOS unit 10 and the second MOS unit 20 which are relatively connected and fixed. ;

Wherein, the side of the first MOS unit 10 facing the second MOS unit 20 has a first drain 11, and the side away from the second MOS unit 20 has a first gate 12 and a first source 13 The second MOS unit 20 has a second drain 21 on the side facing the first MOS unit 10, and a second gate 22 and a second source 23 on the side away from the first MOS unit 10; The first drain 11 is connected and fixed to the second drain 21 .

Wherein, the first drain 11 and the second drain 21 are both metal; the first drain 11 and the second drain 21 can be fixed by eutectic bonding or reflow soldering Fixed, or conductive glue connection fixed.

In step S11, the method for forming multiple first MOS units 10 on the first wafer is shown in Figures 5-8, Figures 5-8 are a process for forming the first MOS units provided by an embodiment of the present invention Flowchart, including:

First, as shown in FIG. 5 and FIG. 6, FIG. 5 is a top view of the first wafer provided by the embodiment of the present invention, and FIG. 6 is a sectional view of the first wafer shown in FIG. Wafer 30, the first wafer 30 includes: a first semiconductor substrate 14 and a first epitaxial layer 15 located on the surface of the first semiconductor substrate 14; the first epitaxial layer 15 has a plurality of The first MOS units 10 correspond one-to-one to the first device region 10 ′.

Then, as shown in Figure 7, the first source 13 and the first gate 12 are formed in the first device region 10';

Finally, as shown in FIG. 8, after thinning the surface of the first semiconductor substrate 14 away from the first epitaxial layer 15, a first metal layer is formed on the surface, and the first metal layer includes a plurality of The first drains 11 correspond one-to-one to the first MOS units 10 .

In step S11, the method for forming multiple second MOS units 20 on the second wafer is shown in Figures 9-12, Figures 9-12 are a process for forming the second MOS units provided by an embodiment of the present invention Flowchart, including:

First, as shown in FIG. 9 and FIG. 10, FIG. 9 is a top view of the second wafer provided by the embodiment of the present invention, and FIG. 10 is a sectional view of the second wafer in the NN' direction shown in FIG. Wafer 40, the second wafer 40 includes: a second semiconductor substrate 24 and a second epitaxial layer 25 located on the surface of the second semiconductor substrate 24; the second epitaxial layer 25 has a plurality of The second MOS units 20 correspond one-to-one to the second device region 20 ′.

Then, as shown in Figure 11, the second source 23 and the second gate 22 are formed in the second device region 20';

Finally, as shown in FIG. 12, after thinning the surface of the second semiconductor substrate 24 away from the second epitaxial layer 25, a second metal layer is formed on the surface, and the second metal layer includes a plurality of The second drains 21 correspond one-to-one to the second MOS units 20 .

As shown in FIG. 13 , FIG. 13 is a cross-sectional view of the connection and fixation of the first wafer and the second wafer provided by the embodiment of the present invention. The first MOS unit 10 and the second MOS unit 20 are connected and fixed back to back. The first drain 11 and the second drain 21 are relatively connected and fixed by means of crystal bonding or reflow soldering bonding, and are divided by cutting trench A to form a 3D double MOS device structure as shown in FIG. 3 . In this method, the first wafer and the second wafer are fixedly connected, and then divided, and the two wafers are divided at the same time. Only one cutting process is required, and the two wafers can be divided at the same time to form multiple semiconductor devices. , the manufacturing process is simple and the manufacturing cost is low.

In the embodiment of the present invention, the first metal layer and the second metal layer may have a whole-layer structure, and may be fixed by eutectic bonding or reflow soldering bonding. In other ways, before the two wafers are connected and fixed, the first metal layer can be divided into multiple separated first drains by etching, and the second metal layer can be divided into multiple separated second drains, and then The first drain and the second drain are connected and fixed in one-to-one correspondence. In this method, when the two wafers are divided, because the first metal layer and the second metal layer are divided in advance, only the wafer is divided, and there is no need to divide the metal, which avoids When the semiconductor material and the metal material are divided at the same time, the problem of warping and separation of the metal material is avoided.

It can be seen from the above description that in the manufacturing method of the semiconductor device provided by the technical solution of the present invention, by designing a 3D double MOS stack structure, the first MOS unit and the second MOS unit are relatively connected and fixed, and are connected by eutectic bonding or reflow soldering. The first drain and the second drain are relatively connected and fixed in an equivalent manner, so that the current paths of the dual MOS drain terminals are perpendicular to each other. Compared with the prior art, the technical solution of the present invention can not only greatly reduce the occupied area, but also solve the problem of uneven current density caused by the 90° corner of the current path of the traditional planar double MOS tube, and has low manufacturing cost and high reliability.

Each embodiment in this specification is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments Just see it. As for the manufacturing method disclosed in the embodiment, since it corresponds to the semiconductor device disclosed in the embodiment, the description is relatively simple, and for related parts, please refer to the description of the semiconductor device.

It should be noted that, in the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", "inner" and "outer" are based on The orientation or positional relationship shown in the drawings is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as Limitations on this Application. When a component is said to be "connected" to another component, it may be directly connected to the other component or there may be a centered component at the same time.

It should also be noted that in this article, relational terms such as first and second etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations Any such actual relationship or order exists between. Moreover, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that an article or device comprising a set of elements includes not only those elements but also other elements not expressly listed, Or also include elements inherent in the article or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in an article or device comprising the aforementioned element.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A semiconductor device, characterized in that, the semiconductor device comprises: Relatively fixed first MOS unit and second MOS unit; A side of the first MOS unit facing the second MOS unit has a first drain, and a side away from the second MOS unit has a first gate and a first source; The second MOS unit has a second drain on a side facing the first MOS unit, and has a second gate and a second source on a side away from the first MOS unit; Wherein, the first drain and the second drain are relatively connected and fixed. 2. The semiconductor device according to claim 1, wherein both the first drain and the second drain are metal; The first drain and the second drain are fixed by eutectic bonding or reflow soldering bonding. 3. The semiconductor device according to claim 1, wherein the first MOS unit comprises: a first semiconductor substrate; the first drain located on one side of the first semiconductor substrate; The first epitaxial layer on the other side of the first semiconductor substrate; the first gate and the first source located in the surface of the first epitaxial layer away from the first semiconductor substrate; The second MOS unit includes: a second semiconductor substrate; the second drain on one side of the second semiconductor substrate; a second epitaxial layer on the other side of the second semiconductor substrate; The second epitaxial layer is away from the second gate and the second source in one side surface of the second semiconductor substrate. 4. The semiconductor device according to claim 3, wherein the first MOS unit is NMOS, and both the first semiconductor substrate and the first epitaxial layer are N-type doped; Or, the first MOS unit is PMOS, and both the first semiconductor substrate and the first epitaxial layer are P-type doped. 5. The semiconductor device according to claim 3, wherein the second MOS unit is NMOS, and both the second semiconductor substrate and the second epitaxial layer are N-type doped; Or, the second MOS unit is PMOS, and both the second semiconductor substrate and the second epitaxial layer are P-type doped. 6. The semiconductor device according to claim 3, wherein the first gate has two first sub-gates; the surface of the first epitaxial layer away from the first semiconductor substrate has two sub-gates. A first trench; one first sub-gate is respectively arranged in the first trench, and a first gate dielectric layer is provided between the first sub-gate and the first trench; two of the first sub-gates There is a first blind hole between the first grooves, and the first source is located in the first blind hole; The second gate has two second sub-gates; the surface of the second epitaxial layer away from the second semiconductor substrate has two second trenches; one For the second sub-gate, there is a second gate dielectric layer between the second sub-gate and the second trench; there is a second blind hole between the two second trenches, and the first Two sources are located in the second blind hole. 7. The semiconductor device according to claim 6, wherein the two first sub-gates are arranged symmetrically on both sides of the first source; The two second sub-gates are arranged symmetrically on both sides of the second source. 8. A method for manufacturing a semiconductor device according to any one of claims 1-7, wherein the method comprises: forming a plurality of first MOS units on a first wafer, and forming a plurality of second MOS units on a second wafer; connecting and fixing the first wafer to the second wafer; connecting and fixing the first MOS unit to the second MOS unit one by one; Carrying out dicing and dividing the two wafers to form a plurality of the semiconductor devices, the semiconductor devices including the first MOS unit and the second MOS unit which are relatively connected and fixed; Wherein, the side of the first MOS unit facing the second MOS unit has a first drain, and the side away from the second MOS unit has a first gate and a first source; the second MOS The side of the unit facing the first MOS unit has a second drain, and the side away from the first MOS unit has a second gate and a second source; the first drain and the second drain The poles are fixed relative to the connection. 9. The manufacturing method according to claim 8, wherein the first wafer comprises: a first semiconductor substrate and a first epitaxial layer located on the surface of the first semiconductor substrate; the first epitaxial layer The layer has a plurality of first device regions one-to-one corresponding to the first MOS units; The method for forming the first MOS unit on the first wafer includes: forming the first source and the first gate in the first device region; After thinning the surface of the first semiconductor substrate away from the first epitaxial layer, a first metal layer is formed on the surface, and the first metal layer includes a plurality of of the first drain. 10. The manufacturing method according to claim 8, wherein the second wafer comprises: a second semiconductor substrate and a second epitaxial layer located on the surface of the second semiconductor substrate; the second epitaxial layer The layer has a plurality of second device regions one-to-one corresponding to the second MOS units; The method for forming the second MOS unit on the second wafer includes: forming the second source and the second gate in the second device region; After thinning the surface of the second semiconductor substrate away from the second epitaxial layer, a second metal layer is formed on the surface, and the second metal layer includes a plurality of of the second drain.

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