CN116031288A - A kind of semiconductor device and its manufacturing method - Google Patents

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, which relate to the technical field of semiconductors and are used for reducing the parasitic capacitance between a source/drain structure and a gate stack structure and improving the working performance of a transistor. The semiconductor device includes: a semiconductor substrate, and a transistor formed on the semiconductor substrate. Wherein, the transistor includes: a source/drain structure, a channel, a gate stack structure and a first metal-semiconductor contact layer. A source/drain structure is formed on the semiconductor substrate. Along the thickness direction of the semiconductor substrate, the source/drain structure includes a first active region and a second active region on the first active region. The width of the second active region increases linearly along the direction close to the first active region. A channel is located between source/drain structures. A gate stack structure is formed on the periphery of the channel. The first metal-semiconductor contact layer is only formed on the portion of the source/drain structure corresponding to the second active region. The first active region has vertical sidewalls self-aligned with the first metal-semiconductor contact layer.

Description

A kind of semiconductor device and its manufacturing method

technical field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

With the development of semiconductor technology, the critical dimensions of semiconductor devices are getting smaller and smaller. When the process node of semiconductor devices reaches below 28nm, for fin field effect transistors and gate-around transistors, the source-drain epitaxy method can usually be used to increase the stress on the channel, thereby increasing the mobility of carriers, thereby improving semiconductor performance. device performance.

However, the AC characteristic of the semiconductor device formed by the existing source-drain epitaxy process is poor, which is not conducive to improving the working performance of the semiconductor device.

Contents of the invention

The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which are used to reduce the parasitic capacitance between the source/drain structure and the gate stack structure and improve the performance of the transistor when at least the source/drain structure is formed by an epitaxial process. AC characteristics, which in turn help to improve the performance of semiconductor devices.

In order to achieve the above objects, the present invention provides a semiconductor device. The semiconductor device includes: a semiconductor substrate, and a transistor formed on the semiconductor substrate. Wherein, the transistor includes: a source/drain structure, a channel, a gate stack structure and a first metal-semiconductor contact layer.

The above source/drain structure is formed on the semiconductor substrate. Along the thickness direction of the semiconductor substrate, the source/drain structure includes a first active region and a second active region on the first active region. The width of the second active region increases linearly along the direction close to the first active region. A channel is located between source/drain structures. A gate stack structure is formed on the periphery of the channel. The first metal-semiconductor contact layer is only formed on the portion of the source/drain structure corresponding to the second active region. The first active region has vertical sidewalls self-aligned with the first metal-semiconductor contact layer.

In the case of adopting the above-mentioned technical solution, in the actual manufacturing process, since the growth rate of the semiconductor material along the {111} crystal plane is the slowest, at least the epitaxial process is used to form the source/drain pre-process for manufacturing the above-mentioned source/drain structure. In the case of forming the structure, the outer surfaces of the source/drain pre-formed structure may all be {111} crystal planes. At this time, the source/drain preformed structure is a diamond-like structure. Wherein, when the partial region of the upper {111} crystal plane corresponds to the outer surface of the second active region, the width of the second active region can increase linearly along the direction close to the first active region. Moreover, at least the source/drain preformed structure formed by epitaxial process can also increase the stress on the channel, which is beneficial to improve the carrier mobility and improve the driving performance of the transistor.

In addition, the first metal-semiconductor contact layer included in the transistor is only formed on the part of the source/drain structure corresponding to the second active region. And the first active region under the second active region has vertical sidewalls self-aligned with the first metal-semiconductor contact layer. At this time, along the height direction of the source/drain structure, the width of each part of the first active region is the same. In other words, the sidewalls of the first active region located below the second active region do not gradually expand outward along the direction close to the semiconductor substrate like the sidewalls of the second active region. The first metal-semiconductor contact layer on the region is self-aligned. Based on this, in the actual application process, after forming a larger source/drain preformed structure, the first metal-semiconductor contact layer can be used as a self-aligned mask to pattern the source/drain preformed structure The processing removes the part of the source/drain pre-formed structure exposed outside the first metal-semiconductor contact layer along its width direction, so that the lateral width and volume of the source/drain structure obtained after processing become smaller, thereby reducing the source/drain structure. The facing area between the drain structure and the gate stack structure can finally reduce the parasitic capacitance between the source/drain structure and the gate stack structure, improve the AC characteristics of the transistor, and help improve the working performance of the semiconductor device.

The present invention also provides a manufacturing method of a semiconductor device, the manufacturing method of the semiconductor device comprising:

A semiconductor substrate is provided.

Transistors are formed on a semiconductor substrate. Wherein, the transistor includes: a source/drain structure, a channel, a gate stack structure and a first metal-semiconductor contact layer. The above source/drain structure is formed on the semiconductor substrate. Along the thickness direction of the semiconductor substrate, the source/drain structure includes a first active region and a second active region on the first active region. The width of the second active region increases linearly along the direction close to the first active region. A channel is located between source/drain structures. A gate stack structure is formed on the periphery of the channel. The first metal-semiconductor contact layer is only formed on the portion of the source/drain structure corresponding to the second active region. The first active region has vertical sidewalls self-aligned with the first metal-semiconductor contact layer.

Compared with the prior art, the beneficial effects of the manufacturing method of the semiconductor device provided by the present invention can refer to the analysis of the beneficial effects of the semiconductor device described above, and will not be repeated here.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute improper limitations to the present invention. In the attached picture:

FIG. 1 is a structural schematic diagram 1 of a semiconductor device in a manufacturing process provided by an embodiment of the present invention;

FIG. 2 is a second schematic structural view of the semiconductor device during the manufacturing process provided by the embodiment of the present invention;

FIG. 3 is a structural schematic diagram III during the manufacturing process of the semiconductor device provided by the embodiment of the present invention;

FIG. 4 is a schematic view 4 of the structure of the semiconductor device in the manufacturing process provided by the embodiment of the present invention;

FIG. 5 is a schematic diagram five of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention;

FIG. 6 is a schematic diagram six of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention;

FIG. 7 is a schematic structural diagram VII of the semiconductor device during the manufacturing process provided by the embodiment of the present invention;

FIG. 8 is a schematic diagram eighth of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention;

FIG. 9 is a structural schematic diagram 9 of the semiconductor device in the manufacturing process provided by the embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present invention;

FIG. 11 is a structural schematic diagram eleven of the semiconductor device during the manufacturing process provided by the embodiment of the present invention;

FIG. 12 is a schematic structural diagram twelve during the manufacturing process of the semiconductor device provided by the embodiment of the present invention;

FIG. 13 is a schematic structural diagram thirteen during the manufacturing process of the semiconductor device provided by the embodiment of the present invention;

FIG. 14 is a fourteenth schematic structural view of the semiconductor device during the manufacturing process provided by the embodiment of the present invention;

FIG. 15 is a fifteenth schematic structural view of the semiconductor device during the manufacturing process provided by the embodiment of the present invention;

FIG. 16 is a sixteenth schematic structural view of the semiconductor device during the manufacturing process provided by the embodiment of the present invention;

FIG. 17 is a seventeenth schematic structural view of the semiconductor device during the manufacturing process provided by the embodiment of the present invention;

FIG. 18 is a schematic structural diagram eighteenth of the semiconductor device in the manufacturing process provided by the embodiment of the present invention;

FIG. 19 is a nineteenth schematic structural view of the semiconductor device during the manufacturing process provided by the embodiment of the present invention;

FIG. 20 is a schematic structural diagram 20 during the manufacturing process of the semiconductor device provided by the embodiment of the present invention;

FIG. 21 is a twenty-first schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention.

Reference numerals: 11 is a semiconductor substrate, 12 is a shallow trench isolation structure, 13 is a fin structure, 14 is a fin, 15 is a channel, 16 is a sacrificial layer, 17 is a channel layer, 18 is a sacrificial gate, 19 is Side wall, 20 epitaxial formation part, 21 source/drain preformed structure, 22 cover material layer, 23 cover layer, 24 first metal-semiconductor contact layer, 25 epitaxial part, 26 source/drain structure, 27 28 is the second active region, 29 is the third active region, 30 is the dielectric layer, 31 is the gate stack structure, 32 is the second metal-semiconductor contact layer.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on" another layer/element in one orientation, the layer/element can be located "below" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more than one, unless otherwise clearly and specifically defined.

In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it may be mechanical connection or electrical connection; it may be direct connection or indirect connection through an intermediary, and it may be the internal communication of two elements or the interaction relationship between two elements. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

With the development of semiconductor technology, the critical dimensions of semiconductor devices are getting smaller and smaller. When the process node of semiconductor devices reaches below 28nm, for fin field effect transistors and gate-around transistors, the source-drain epitaxy method can usually be used to increase the stress on the channel, thereby increasing the mobility of carriers, thereby improving semiconductor performance. device performance. Exemplarily, for a PMOS transistor, the epitaxial material of the source and drain is usually a semiconductor material with compressive stress, such as silicon germanium or germanium. For NMOS transistors, the source and drain epitaxial material is usually a semiconductor material with tensile stress such as Si:C.

In the actual manufacturing process, the fin field effect transistor is taken as an example for illustration. After forming a fin structure on the semiconductor substrate and forming sacrificial gates and sidewalls straddling the fin structure, the epitaxial process can be used to directly An epitaxial layer is covered on the portion of the fin structure exposed outside the sacrificial gate and the spacer to obtain source/drain regions. Alternatively, the portion of the fin structure exposed outside the sacrificial gate and the sidewall can also be removed first; and then an epitaxial process is used to form source/drain regions on both sides of the remaining fin structure. In the above two cases, in the process of forming the epitaxial layer or directly forming the source/drain region by the epitaxial process, there is no corresponding structure to limit the growth space of the epitaxial layer or the source/drain region, and the finally obtained source/drain region The volume of the fin structure is generally larger than the volume of the part of the original fin structure exposed outside the sacrificial gate and the sidewall, so as to provide corresponding stress to the channel, reduce contact resistance, and improve the driving performance of the device.

However, after the gate stack structure is formed, parasitic capacitance exists between the gate stack structure and the source/drain regions. Based on this, when the volume of the finally obtained source/drain region becomes larger, the facing area between the gate stack structure and the source/drain region becomes larger, so that the above-mentioned parasitic capacitance becomes larger, thereby affecting the AC characteristics of the device.

In order to solve the above technical problems, embodiments of the present invention provide a semiconductor device and a manufacturing method thereof. Wherein, in the semiconductor device provided by the embodiment of the present invention, the width of the second active region included in the source/drain structure increases linearly along the direction close to the first active region. The first metal-semiconductor contact layer is only formed on the portion of the source/drain structure corresponding to the second active region. Moreover, the first active region has a vertical sidewall self-aligned with the first metal-semiconductor contact layer, so as to reduce the parasitic capacitance between the source/drain structure and the gate stack structure, improve the AC characteristics of the transistor, and help improve the performance of the semiconductor device. work performance.

Specifically, the device type of the semiconductor device provided in the embodiment of the present invention may be determined according to an actual application scenario, and is not specifically limited here.

For example: the semiconductor device provided by the embodiment of the present invention may be a CFET (Complementary FET) device. Specifically, the CFET device includes two transistors arranged at intervals along the thickness direction of the semiconductor substrate. Also, the conductivity types of these two transistors are opposite.

Another example: the above-mentioned semiconductor device may also be a Forksheet device. Specifically, the Forksheet device includes two transistors arranged at intervals along a direction parallel to the surface of the semiconductor substrate, and a dielectric isolation wall between the two transistors. The conductivity types of the above two transistors are opposite and are separated by a dielectric isolation wall.

Specifically, as shown in FIG. 17 to FIG. 20 , the semiconductor device provided by the embodiment of the present invention includes: a semiconductor substrate 11 and a transistor formed on the semiconductor substrate 11 .

Wherein, for the above-mentioned semiconductor substrate, the specific structure and material of the above-mentioned semiconductor substrate can be determined according to the device type of the semiconductor device and the actual application scenario, which is not specifically limited here.

For example, when the semiconductor device is a CFET device and the above-mentioned transistors formed on the semiconductor substrate are upper transistors, the semiconductor substrate includes the semiconductor substrate and the lower transistors formed on the semiconductor substrate.

For another example: when the semiconductor device is a CFET device and the transistor formed on the semiconductor substrate is a lower transistor, the semiconductor substrate may be a semiconductor substrate without any structure formed thereon.

As for the above-mentioned transistor, in terms of device type, the above-mentioned transistor may be any three-dimensional transistor formed on a semiconductor substrate. For example: as shown in FIG. 17 , the above-mentioned transistors may be fin field effect transistors. Alternatively, as shown in FIG. 19 , the aforementioned transistors may also be gate-around transistors.

In terms of device structure, as shown in FIGS. 14 to 20 , the above-mentioned transistor includes: a source/drain structure 26 , a channel 15 , a gate stack structure 31 and a first metal-semiconductor contact layer 24 . The aforementioned source/drain structure 26 is formed on the semiconductor substrate 11 . Along the thickness direction of the semiconductor substrate 11 , the source/drain structure 26 includes a first active region 27 and a second active region 28 located on the first active region 27 . The width of the second active region 28 increases linearly along the direction approaching the first active region 27 . Channel 15 is located between source/drain structures 26 . A gate stack structure 31 is formed on the outer periphery of the channel 15 . The first metal-semiconductor contact layer 24 is only formed on the portion of the source/drain structure 26 corresponding to the second active region 28 . The first active region 27 has vertical sidewalls self-aligned with the first metal-semiconductor contact layer 24 .

Wherein, the specific structure of the channel can be determined according to the device type of the transistor and the actual application scenario, and is not specifically limited here.

For example: as shown in FIG. 17 , when the above-mentioned transistor is a fin field effect transistor, the channel 15 is a fin structure formed on the semiconductor substrate 11 .

Another example: as shown in FIG. 19 , when the above-mentioned transistor is a gate-all-around transistor, the channel 15 includes at least one nanostructure formed above the semiconductor substrate 11 . There is a gap between each nanostructure and the semiconductor substrate 11 . Specifically, when the channel 15 includes at least two nanostructures, there are gaps between two adjacent nanostructures. In addition, different nanostructures may be arranged at intervals along the thickness direction of the semiconductor substrate 11 , or may be arranged at intervals along the width direction of the gate stack structure.

Furthermore, the material of the channel may be semiconductor materials such as silicon, silicon germanium, germanium, or III-V compounds.

For the gate stack structure, the gate stack structure may include a gate dielectric layer formed at least around the channel, and a gate formed on the gate dielectric layer. Specifically, the material of the gate dielectric layer may be insulating materials such as HfO ₂ , ZrO ₂ , TiO ₂ or Al ₂ O ₃ . The material of the above-mentioned gate can be a conductive material such as TiN, TaN or TiSiN.

Regarding the above source/drain structure, in terms of structure, the source/drain structure includes a first active region and a second active region located on the first active region. Wherein, the width of the second active region increases linearly along the direction close to the first active region. In this case, in the actual manufacturing process, as shown in Figures 4 to 7, the growth rate of the semiconductor material along the {111} crystal plane is the slowest, so at least the epitaxial process is used to form the above source/drain structure In the case of the source/drain pre-formation structure 21, the outer surfaces of the source/drain pre-formation structure 21 may be all {111} crystal planes. At this time, the source/drain preformed structure 21 is a diamond-like structure. Wherein, when the partial region of the upper {111} crystal plane corresponds to the outer surface of the second active region, the width of the second active region increases linearly along the direction close to the first active region. Moreover, at least the source/drain pre-formation structure 21 is formed by epitaxial process, which can also increase the stress on the channel, which is beneficial to improve the carrier mobility and improve the driving performance of the transistor.

In addition, as shown in FIGS. 12 to 15 , the first metal-semiconductor contact layer 24 included in the above-mentioned transistor is only formed on the portion of the source/drain structure 26 corresponding to the second active region 28 . The first active region 27 located below the second active region 28 has vertical sidewalls self-aligned with the first metal-semiconductor contact layer 24 . At this time, along the height direction of the source/drain structure 26 , the widths of each part of the first active region 27 are the same. In other words, the sidewalls of the first active region 27 located below the second active region 28 do not gradually expand outward along the direction close to the semiconductor substrate 11 like the sidewalls of the second active region 28, but The first metal-semiconductor contact layer 24 on the second active region 28 is self-aligned. Based on this, in the actual application process, as shown in FIGS. 11 to 15, after forming a larger source/drain preformed structure 21, the first metal-semiconductor contact layer 24 can be used as a self-aligned mask , the source/drain preformed structure 21 is patterned, and the part of the source/drain preformed structure 21 exposed outside the first metal-semiconductor contact layer 24 along its width direction is removed, so that the source/drain obtained after processing The lateral width and volume of the structure 26 become smaller, which in turn can reduce the direct facing area between the source/drain structure 26 and the gate stack structure, and finally can reduce the parasitic capacitance between the source/drain structure 26 and the gate stack structure, and improve the performance of the transistor. AC characteristics are beneficial to improve the working performance of semiconductor devices.

It can be seen from the above that, as shown in FIGS. 11 to 15 , the portion of the source/drain preformed structure 21 covered by the first metal-semiconductor contact layer 24 corresponds to the portion of the source/drain structure 26 located in the second active region 28 . Based on this, the maximum value of the width of the second active region 28 is smaller than the maximum value of the width of the source/drain preformed structure 21, so that the part of the source/drain structure 26 corresponding to the first active region 27 has a vertical side after the patterning process. wall. The vertical sidewalls are perpendicular to the surface of the semiconductor substrate 11 . Secondly, the above-mentioned minimum width of the second active region 28 can be determined according to the actual formation process of the source/drain preformed structure 21 used to manufacture the source/drain structure 26 , which is not specifically limited here. For example, as shown in FIG. 6 and FIG. 14 , the top surface of the second active region 28 may be a plane, and the width of the plane is the minimum width of the second active region 28 . Alternatively, as shown in FIG. 7 , the top of the second active region is a straight line formed by the intersection of two side surfaces, and the width of the straight line is the minimum width of the second active region.

In the actual application process, as mentioned above, the outer sides of the source/drain preformed structure used to manufacture the source/drain structure are all {111} crystal planes, and some regions of the upper {111} crystal planes are aligned with the The outer surface of the second active region corresponds. Based on this, as shown in FIG. 14 , in the process of patterning the source/drain preformed structure using the first metal-semiconductor contact layer 24 as a self-aligned mask, if the maximum of the first metal-semiconductor contact layer 24 If the width is less than or equal to the minimum width of the bottom of the source/drain preformed structure, the source/drain structure 26 obtained after patterning includes only the first active region 27 and the second active region 28 .

As shown in FIG. 15 , in the process of patterning the source/drain preformed structure using the first metal-semiconductor contact layer 24 as a self-aligned mask, if the maximum width of the first metal-semiconductor contact layer 24 is larger than the source If the minimum width of the bottom of the structure is preformed, the source/drain structure 26 may further include a third active region 29 located between the semiconductor substrate 11 and the first active region 27 . The width of the third active region 29 increases linearly along the direction close to the first active region 27 , and the third active region 29 is self-aligned with the first metal-semiconductor contact layer 24 . It can be understood that the outer surface of the third active region 29 corresponds to a partial region of the lower {111} crystal plane in the source/drain preformed structure.

In terms of structure, the specific structure of the source/drain structure can be determined according to the actual manufacturing process. For example, as shown in FIG. 13 , the source/drain structure 26 includes a fin portion 14 and an epitaxial portion 25 formed on the periphery of the fin portion 14 . The fins 14 are integrally formed with the channel 15 . In this case, as shown in FIG. 4 and FIG. 13 , the epitaxial forming part 20 can be directly formed on the fin part 14 included in the fin structure by using an epitaxial process, so as to obtain the source/drain of the source/drain structure 26 for manufacturing. The structure 21 is preformed. Moreover, after patterning, the epitaxial formation part 20 forms the above-mentioned epitaxial part 25 , and the source/drain pre-formation structure 21 forms the source/drain structure 26 . It can be understood that the material of the above-mentioned fin portion 14 is the same as that of the channel 15 . The material of the epitaxial portion 25 may be the same as that of the channel 15 or may be different.

Another example: as shown in FIG. 12 , the entire source/drain structure 26 may also be an epitaxial structure. In this case, as shown in FIG. 5 , FIG. 6 and FIG. 12 , under the mask effect of the sacrificial gate 18 and the sidewall 19 , the fins included in the fin structure can be removed. And adopt epitaxy process, form the source/drain pre-formation structure 21 on both sides of the channel along the length direction of the gate stack structure. The source/drain preformed structure 21 forms a source/drain structure 26 after patterning. Wherein, the material of the source/drain structure 26 and the material of the channel may be the same or different.

For the above-mentioned first metal-semiconductor contact layer, the semiconductor material in the first metal-semiconductor contact layer is the same as the material of the part of the source/drain structure corresponding to the second active region. The metal material in the first metal-semiconductor contact layer can be determined according to actual application scenarios. For example, in the case that the material of the part of the source/drain structure corresponding to the second active region is silicon, the material of the first metal-semiconductor contact layer may be nickel silicide or titanium silicide.

The thickness of the first metal-semiconductor contact layer can be set according to actual application scenarios, as long as the first metal-semiconductor contact layer can be used as the above-mentioned self-alignment mask.

In an example, as shown in FIG. 21 , the above-mentioned transistor may further include a second metal-semiconductor contact layer 32 . The second metal-semiconductor contact layer 32 covers the portion of the source/drain structure 26 exposed outside the first metal-semiconductor contact layer 24 . In this case, the periphery of the source/drain structure 26 may be covered by the first metal-semiconductor contact layer 24 and the second metal-semiconductor contact layer 32, so as to reduce the contact resistance between the source/drain structure 26 and the source/drain, Further improve the electrical performance of the transistor.

Specifically, the semiconductor material in the second metal-semiconductor contact layer is the same as that of the part of the source/drain structure corresponding to the first active region. In addition, the metal elements in the second metal-semiconductor contact layer may be the same as or different from the metal elements in the first metal-semiconductor contact layer. For example: when the material of the part of the source/drain structure corresponding to the first active region is silicon, and the metal element in the first metal-semiconductor contact layer is nickel, the material of the second metal-semiconductor contact layer can be nickel silicide, Titanium silicide and the like may also be used.

In some cases, as shown in FIG. 20 and FIG. 21 , the semiconductor device provided by the embodiment of the present invention may further include a shallow trench isolation structure 12 formed on the semiconductor substrate 11 . The shallow trench isolation structure 12 is used to isolate different active regions of the semiconductor substrate 11 to prevent electric leakage. The thickness of the shallow trench isolation structure 12 can be set according to actual conditions. The material of the shallow trench isolation structure 12 may be an insulating material such as SiN, Si ₃ N ₄ , SiO ₂ or SiCO.

In some cases, as shown in FIG. 20 , the transistor provided by the embodiment of the present invention may further include spacer walls 19 and a dielectric layer 30 . The spacers 19 are formed at least on both sides of the gate stack structure 31 along its length direction, so as to isolate the gate stack structure 31 from other conductive structures and improve the electrical characteristics of the transistor. Wherein, the thickness of the part of the spacer 19 located on both sides of the gate stack structure 31 along the length direction may be the same. The material of the side wall 19 may be insulating material such as silicon oxide or silicon nitride. In addition, the above-mentioned dielectric layer 30 covers the semiconductor substrate 11 , and its top is flush with the top of the gate stack structure 31 . In the actual manufacturing process, the existence of the dielectric layer 30 can protect the source/drain structure 26 from subsequent operations such as removing the sacrificial gate and sacrificial layer, and improve the yield of the transistor. The material of the dielectric layer 30 may be insulating materials such as silicon oxide or silicon nitride.

The embodiment of the invention also provides a method for manufacturing a semiconductor device. Hereinafter, the manufacturing process will be described based on perspective views or cross-sectional views of operations shown in FIGS. 1 to 21 . Specifically, the manufacturing method of the semiconductor device includes the following steps:

First, a semiconductor substrate is provided. The structure and material of the semiconductor substrate can be referred to above, and will not be repeated here.

Next, as shown in FIGS. 14 to 21 , transistors are formed on the semiconductor substrate 11 . Wherein, the transistor includes: a source/drain structure 26 , a channel 15 , a gate stack structure 31 and a first metal-semiconductor contact layer 24 . The aforementioned source/drain structure 26 is formed on the semiconductor substrate 11 . Along the thickness direction of the semiconductor substrate 11 , the source/drain structure 26 includes a first active region 27 and a second active region 28 located on the first active region 27 . The width of the second active region 28 increases linearly along the direction approaching the first active region 27 . Channel 15 is located between source/drain structures 26 . A gate stack structure 31 is formed on the outer periphery of the channel 15 . The first metal-semiconductor contact layer 24 is only formed on the portion of the source/drain structure 26 corresponding to the second active region 28 . The first active region 27 has vertical sidewalls self-aligned with the first metal-semiconductor contact layer 24 .

Specifically, information such as the device type of the above-mentioned transistor, and the structure and material of each part included in the transistor can be referred to above, and will not be repeated here.

In an example, forming the transistor on the semiconductor substrate may include the following steps:

As shown in FIGS. 1 and 2 , at least a channel 15 is formed on the semiconductor substrate 11 .

Specifically, only channels can be formed on the semiconductor substrate. Alternatively, as shown in FIGS. 1 and 2 , fin structures 13 may also be formed on the semiconductor substrate 11 . Along the length direction of the fin structure 13 , the fin structure 13 includes a channel 15 and fins 14 located on two sides of the channel 15 .

As mentioned above, when the device types of the transistors are different, the structures of the channels included in the transistors are also different. Based on this, the specific formation process of the channel can be determined according to the device type of the transistor and the actual application scenario.

For example, as shown in FIG. 17, when the transistor is a fin field effect transistor, photolithography and etching processes can be used to directly pattern the semiconductor substrate to form a Fin structure for manufacturing a fin structure. Alternatively, an epitaxial process may also be used to first form a semiconductor layer on a semiconductor substrate and at least perform patterning on the semiconductor layer to form a Fin structure. Finally, as shown in FIG. 1 , a shallow trench isolation structure 12 may be formed on the part of the semiconductor substrate 11 exposed outside the Fin structure by sequentially adopting processes such as deposition and etching. Wherein, the part of the Fin structure exposed outside the shallow trench isolation structure 12 is the above-mentioned fin structure 13 .

Another example: as shown in Figure 19, when the transistor is a gate-all-around transistor, firstly, a process such as epitaxial growth can be used to form alternately stacked sacrificial material layers and channel material layers on the semiconductor substrate along the thickness direction of the semiconductor substrate. layer. Among the alternately stacked sacrificial material layers and channel material layers, the film layer at the bottom layer is the sacrificial material layer; the film layer at the top layer can be either the channel material layer or the sacrificial material layer. The number of channel material layers formed on the semiconductor substrate can be determined with reference to the number of nanostructures included in the channel and the arrangement of different nanostructures, which is not specifically limited here. Next, processes such as photolithography and etching can be used to pattern the alternately stacked sacrificial material layers and channel material layers, as well as part of the semiconductor substrate, to form a Fin structure. Then, as shown in FIG. 2 , the shallow trench isolation structure 12 may be formed in the manner described above. Wherein, the part of the Fin structure exposed outside the shallow trench isolation structure 12 is the above-mentioned fin structure 13 . The fin structure 13 includes sacrificial layers 16 and channel layers 17 stacked alternately.

In one example, the gate stack structure included in the transistor may be formed by using a replacement gate process, so as to prevent the gate stack structure from being affected during the process of forming the source/drain structure and improve the formation quality of the gate stack structure. In this case, after the channel is formed on the semiconductor substrate and before subsequent operations are performed, the above-mentioned semiconductor device manufacturing method may further include a step: as shown in FIG. 3 , processes such as deposition and etching may be used to sequentially form The length direction of the gate stack structure straddles the sacrificial gate 18 and the spacer 19 on the channel. The sidewalls 19 are at least located on both sides of the sacrificial grid 18 along its length. Wherein, the material of the sacrificial gate 18 may be easily removable material such as polysilicon. For the material of the side wall 19, reference may be made to the foregoing.

It should be noted that if the above-mentioned sacrificial gate and sidewall are not formed in the actual application process, after at least the channel is formed and before the source/drain pre-formation structure is formed, processes such as deposition and etching can be used to form A mask layer covering the top of the channel and both sides of the channel along the width direction of the gate stack structure, so that the subsequently formed source/drain preformed structure is only located on both sides of the channel along the length direction of the gate stack structure. The material and thickness of the mask layer can be set according to actual application scenarios, as long as it can be applied to the manufacturing method of the semiconductor device provided by the embodiment of the present invention.

Next, as shown in FIGS. 3 to 7 , at least an epitaxial process is used to form source/drain preformed structures 21 on both sides of the channel along the length direction of the gate stack structure. The source/drain preformed structure 21 has both {111} crystal planes on its outer surfaces.

Specifically, the source/drain preformed structure is used to manufacture the source/drain structure included in the transistor. Based on this, the specific manufacturing process of the source/drain preformed structure can be determined according to the specific structural features of the source/drain structure.

For example: as shown in FIG. 13, in the case where the source/drain structure 26 included in the manufactured transistor has a fin 14 and an epitaxial portion 25, as shown in FIG. The epitaxial formation part 20 . The source/drain pre-formation structure 21 includes the fin portion 14 and the epitaxial formation portion 20 . Wherein, the epitaxial formation part 20 corresponds to the epitaxial part included in the source/drain structure, so the material of the epitaxial formation part 20 can refer to the material of the aforementioned epitaxial part.

Another example: as shown in FIG. 12, in the case where the entire source/drain structure 26 of the fabricated transistor is an epitaxial structure, as shown in FIG. Alternatively, under the mask effect of the above-mentioned mask layer (not shown in the figure), dry etching or wet etching is used to remove the fins located on both sides of the channel. At this time, the two sidewalls of the channel along the length direction of the gate stack structure are exposed. Next, as shown in FIG. 6 and FIG. 7 , a source/drain preformed structure 21 is formed by using an epitaxial process.

Then, as shown in FIG. 11 , a first metal-semiconductor contact layer 24 is formed on top of the source/drain pre-formation structure 21 . The maximum width of the portion of the source/drain preformed structure 21 covered by the first metal-semiconductor contact layer 24 is smaller than the maximum width of the source/drain preformed structure 21 . Wherein, information such as the formation range and material of the first metal-semiconductor contact layer 24 can be referred to above, and will not be repeated here.

In one example, forming the first metal-semiconductor contact layer on the top of the source/drain pre-formation structure may include the following steps: first, as shown in FIG. 9 , forming a cover layer covering part of the source/drain pre-formation structure 21 twenty three. Next, as shown in FIG. 10 , a first metal-semiconductor contact layer 24 is formed on the portion of the source/drain preformed structure 21 exposed from the cover layer 23 . Then, as shown in Fig. 11, the covering layer is removed.

Specifically, processes such as chemical vapor deposition may be used to form a covering material covering the formed structure. Next, as shown in FIG. 8 , a process such as chemical mechanical polishing may be used to planarize the covering material, so as to expose the top of the sacrificial gate 18 (or mask layer). Correspondingly, the remaining covering material forms the covering material layer 22 . Then, as shown in FIG. 9 , dry etching or wet etching may be used to etch back the cover material layer to expose part of the source/drain preformed structure 21 . The remainder of the layer of covering material forms the covering layer 23 . Specifically, the part of the source/drain preformed structure 21 exposed outside the cover layer 23 corresponds to the part where the source/drain structure is formed and located in the second active region. Based on this, according to the size requirements of the part of the source/drain structure located in the second active region in the actual application scenario, and by controlling conditions such as etching time and etching temperature, the treatment degree of the above-mentioned etch-back treatment can be determined. In addition, the material of the above-mentioned covering layer 23 can be any material that has a certain etching selectivity ratio with the material of the source/drain preformed structure 21 and the sacrificial gate 18 (or mask layer), as long as it can be applied to the present invention It can be used in the manufacturing method of the semiconductor device provided in the embodiment. For example: the material of the covering layer 23 may be a dielectric material such as silicon oxide. In addition, after the covering layer is formed, processes such as deposition may be used to form a metal material covering the formed structure. And through processes such as annealing, the metal material reacts with the part of the source/drain pre-formed structure exposed outside the covering layer, so as to form the first metal-semiconductor contact layer. Then, as shown in FIG. 10 and FIG. 11 , processes such as dry etching or wet etching may be used to sequentially remove the unreacted metal material and the covering layer.

As shown in FIGS. 12 to 15 , the source/drain pre-formed structure can be patterned by using dry etching or wet etching and using the first metal-semiconductor contact layer 24 as a self-aligned mask. A source/drain structure 26 is obtained.

Wherein, as shown in FIG. 4 , if the source/drain pre-formation structure 21 includes the fin portion 14 and the epitaxial formation portion 20 , as shown in FIG. 13 , the epitaxial formation portion forms an epitaxial portion 25 after patterning. The resulting source/drain structure 26 includes the fin 14 and the epitaxial portion 25 .

It should be noted that, as shown in FIG. 4 , FIG. 6 and FIG. 7 , although the lateral width and volume of the source/drain preformed structure 21 used to manufacture the source/drain structure are formed by at least the epitaxial process, however, As shown in FIG. 11 to FIG. 15 , after the source/drain pre-formation structure 21 with a large volume is formed, the first metal-semiconductor contact layer 24 is used as a self-aligned mask to pattern the source/drain pre-formation structure 21 Chemical treatment removes the part of the source/drain preformed structure 21 exposed outside the first metal-semiconductor contact layer 24 along its width direction, so that the lateral width and volume of the source/drain structure 26 obtained after the treatment become smaller, and then The direct facing area between the source/drain structure 26 and the subsequently formed gate stack structure can be reduced, and finally the parasitic capacitance between the source/drain structure 26 and the gate stack structure can be reduced, and the AC characteristics of the transistor can be improved, which is conducive to improving the performance of the semiconductor device. work performance.

In addition, it should be noted that, as mentioned above, if the transistor in the manufactured semiconductor device also includes a dielectric layer, after the source/drain structure is formed, as shown in Figure 16, deposition and chemical mechanical planarization, etc. process to form a dielectric layer 30 covering the formed structure. The top of the dielectric layer 30 is flush with the top of the sacrificial gate 18 (or mask layer). The material of the dielectric layer 30 can refer to the above.

Next, if the sacrificial gate and sidewall (or mask layer) across the channel are formed before forming the source/drain pre-formation structure, as shown in Figure 17 and Figure 18, dry etching can be used or wet etching to remove the sacrificial gate (or mask layer) to expose the channel 15 . Wherein, when the manufactured transistor is a gate-around transistor, after removing the sacrificial gate, as shown in FIG. 19 , the sacrificial layer also needs to be removed to release the channel layer.

Next, as shown in FIG. 20 , processes such as atomic layer deposition may be used to form a gate stack structure 31 surrounding the outer periphery of the channel.

In one example, after forming the gate stack structure surrounding the outer periphery of the channel, the above-mentioned manufacturing method of the semiconductor device may further include a step of forming a second metal-semiconductor contact layer 32 as shown in FIG. 21 . The second metal-semiconductor contact layer 32 covers the part of the source/drain structure 26 exposed outside the first metal-semiconductor contact layer 24, so as to reduce the contact resistance between the source/drain structure 26 and the source/drain, and further improve the transistor. electrical properties.

Specifically, in an actual application process, processes such as photolithography and etching may be used to form contact holes penetrating through the dielectric layer. The first metal-semiconductor contact layer and the source/drain structure are exposed outside through the contact hole. Next, processes such as deposition may be used to form metal materials filled in the contact holes. And through processes such as annealing treatment, the metal material reacts with the part of the source/drain structure exposed outside the first metal-semiconductor contact layer to obtain a second metal-semiconductor contact layer.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be advantageously used in combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (15)

1. A semiconductor device, characterized in that it comprises: a semiconductor substrate and a transistor formed on the semiconductor substrate; wherein the transistor comprises: A source/drain structure is formed on the semiconductor substrate; along the thickness direction of the semiconductor substrate, the source/drain structure includes a first active region and a second active region located on the first active region region; the width of the second active region increases linearly along a direction close to the first active region; a channel located between the source/drain structures; a gate stack structure formed on the periphery of the channel; and a first metal-semiconductor contact layer formed only on the portion of the source/drain structure corresponding to the second active region; the first active region has a self-aligned structure with the first metal-semiconductor contact layer Vertical side walls. 2. The semiconductor device according to claim 1, wherein the source/drain structure further comprises a third active region located between the semiconductor substrate and the first active region; The width of the third active region increases linearly along a direction close to the first active region, and the third active region is self-aligned with the first metal-semiconductor contact layer. 3. The semiconductor device according to claim 1, wherein the entire source/drain structure is an epitaxial structure; or, The source/drain structure includes a fin and an extension formed on the periphery of the fin; the fin is integrally formed with the channel. 4. The semiconductor device according to claim 1, wherein a material of the source/drain structure is different from a material of the channel. 5. The semiconductor device according to claim 1, wherein the transistor further comprises a second metal-semiconductor contact layer; the second metal-semiconductor contact layer covers the source/drain structure exposed on the first on the part other than the metal-semiconductor contact layer. 6. The semiconductor device according to claim 5, wherein the metal element in the second metal-semiconductor contact layer is different from the metal element in the first metal-semiconductor contact layer. 7 . The semiconductor device according to claim 1 , wherein the transistor is a gate-all-round transistor or a fin field effect transistor. 8 . The semiconductor device according to claim 1 , wherein the semiconductor device is a CFET device or a Forksheet device. 9. A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate; A transistor is formed on the semiconductor substrate; wherein the transistor includes: A source/drain structure is formed on the semiconductor substrate; along the thickness direction of the semiconductor substrate, the source/drain structure includes a first active region and a second active region located on the first active region region; the width of the second active region increases linearly along a direction close to the first active region; a channel located between the source/drain structures; a gate stack structure formed on the periphery of the channel; and a first metal-semiconductor contact layer formed only on the portion of the source/drain structure corresponding to the second active region; the first active region has a self-aligned structure with the first metal-semiconductor contact layer Vertical side walls. 10. The method for manufacturing a semiconductor device according to claim 9, wherein said forming a transistor on said semiconductor substrate comprises: forming at least the channel on the semiconductor substrate; Using at least an epitaxial process to form a source/drain preformed structure on both sides of the channel along the length direction of the gate stack structure; the source/drain preformed structure has both {111} crystal planes on its outer sides; The first metal-semiconductor contact layer is formed on the top of the source/drain pre-formed structure; the maximum width of the part of the source/drain pre-formed structure covered by the first metal-semiconductor contact layer is smaller than the source/drain the maximum width of the preformed structure; Using the first metal-semiconductor contact layer as a self-aligned mask, the source/drain preformed structure is patterned to obtain the source/drain structure. 11. The method for manufacturing a semiconductor device according to claim 10, wherein forming the first metal-semiconductor contact layer on top of the source/drain preformed structure comprises: forming a covering layer covering part of the source/drain preformed structure; forming the first metal-semiconductor contact layer on a portion of the source/drain preformed structure exposed from the cover layer; The covering layer is removed. 12. The manufacturing method of a semiconductor device according to claim 10, characterized in that, after forming the channel on the semiconductor substrate, forming a source/drain pre-formation on both sides of the channel Before the structure, the manufacturing method of the semiconductor device further includes: forming a sacrificial gate and sidewalls across the channel along the length direction of the gate stack structure; the sidewalls are at least located along the length of the sacrificial gate itself both sides of the direction; After the source/drain structure is obtained, the manufacturing method of the semiconductor device includes: at least removing the sacrificial gate, and forming the gate stack structure surrounding the outer periphery of the channel. 13. The method for manufacturing a semiconductor device according to claim 12, wherein after forming the gate stack structure surrounding the outer periphery of the channel, the method for manufacturing a semiconductor device further comprises: forming a second metal-semiconductor contact layer; the second metal-semiconductor contact layer covers the portion of the source/drain structure exposed outside the first metal-semiconductor contact layer. 14. The method for manufacturing a semiconductor device according to any one of claims 12 or 13, wherein the forming at least the channel on the semiconductor substrate comprises: forming a fin on the semiconductor substrate structure; along the length direction of the fin structure, the fin structure includes the channel and fins located on both sides of the channel; The at least employing an epitaxial process to form a source/drain pre-formed structure on both sides of the channel along the length direction of the gate stack structure includes: removing the fins located on both sides of the channel; and using In the epitaxial process, the source/drain preformed structure is formed. 15. The method for manufacturing a semiconductor device according to any one of claims 10-13, characterized in that, forming at least the channel on the semiconductor substrate comprises: forming a fin on the semiconductor substrate structure; along the length direction of the fin structure, the fin structure includes the channel and fins located on both sides of the channel; The at least using an epitaxial process to form a source/drain preformed structure on both sides of the channel along the length direction of the gate stack structure includes: using the epitaxial process to form an epitaxial formation on the outer periphery of the fin portion; the source/drain pre-formed structure includes the fin portion and the epitaxial formation portion; After the patterning process, the epitaxial forming part forms an epitaxial part; the source/drain structure includes the fin part and the epitaxial part.

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