CN116048177B - Current bias generating circuit with controllable temperature coefficient and radio frequency power amplifier - Google Patents

Abstract

The present invention relates to a current bias generating circuit with a controllable temperature coefficient, comprising: a first current subtractor, whose first and second input terminals are connected to current sources Iz1 and Ip, respectively; an output terminal of the subtractor is connected to a first proportional amplifier and then to the input terminal of a current adder; a second current subtractor, whose first and second input terminals are connected to current sources Iz2 and Ip, respectively; an output terminal of the subtractor is connected to a second proportional amplifier and then to the input terminal of a current adder; the input terminal of the current adder is also connected to a current source Iz3; the output terminal of the current adder outputs a bias current source Io. The present invention provides a bias current Io with a controllable temperature coefficient, and the temperature coefficients of different temperature zones are independently controllable, thereby increasing the flexibility and precision of the bias current, providing more precise bias current control for a radio frequency power amplifier, and improving the performance of the radio frequency power amplifier.

Description

Current bias generating circuit capable of controlling temperature coefficient and radio frequency power amplifier

Technical Field

The invention relates to the field of radio frequency amplifying circuits, in particular to a temperature coefficient controllable current bias generating circuit and a radio frequency amplifier.

Background

The current bias generating circuit generates a bias current to provide stable bias for each module in the integrated circuit. In radio frequency Power Amplifier (PA) designs, the bias current provides a suitable operating point for the PA, enabling high efficiency, high linearity operation of the PA.

Because the current of the power tube (HBT) of the rf PA is shown in equation 1:

equation 1 ic=is exp (Vbe/Vt)

Where Is the reverse saturation current of the HBT tube, vbe Is the base-level bias voltage, and Vt Is the thermal voltage. According to the thermal voltage formula vt=kt/q, T is the thermodynamic temperature, q is the charge quantity per electron, k is the boltzmann constant, and Vt has a positive temperature coefficient.

The transconductance gm of the HBT refers to the ratio between the change in the output current and the change in the input voltage, as shown in equation 2,

Formula 2 gm=dc/dVbe =ic/vt=beta×ib/Vt

Beta is the current gain of the HBT, ib is the base-stage bias current, gm is an important design parameter of the PA, and in order to ensure that the PA is kept constant at different temperatures, ib is required to have a positive temperature coefficient, namely the bias current generated by the current bias generation circuit is required to have a positive temperature coefficient.

Existing current bias generation circuits provide a constant temperature coefficient bias current, i.e. the bias current is kept constant under temperature variations, or a positive temperature coefficient bias current, i.e. the positive temperature coefficient is provided according to the junction voltage difference of two BJT (bipolar transistor) tubes of different current densities in a Bandgap (Bandgap reference) structure, however, such a scheme can only provide a single positive temperature coefficient.

Disclosure of Invention

The invention aims to solve the technical problem of providing a current bias generating circuit with a controllable temperature coefficient and a radio frequency power amplifier aiming at the defects in the prior art.

The invention provides a current bias generating circuit with controllable temperature coefficient, which comprises a first current subtracter, a second current subtracter, a first proportional amplifier, a second proportional amplifier and a current adder;

A first input end of the first current subtracter is connected with a current source Ip, a second input end of the first current subtracter is connected with a current source Iz1, an output end of the first current subtracter is connected with an input end of the first proportional amplifier, and an output end of the first proportional amplifier is connected with an input end of the current adder;

The first input end of the second current subtracter is connected with a current source Iz2, the second input end of the second current subtracter is connected with the current source Ip, the output end of the second current subtracter is connected with the input end of the second proportional amplifier, and the output end of the second proportional amplifier is connected with the input end of the current adder;

the input end of the current adder is also connected with a current source Iz3, and the output end of the current adder outputs a bias current source Io.

In some embodiments, the current source Ip is an original positive temperature coefficient current, and the current sources Iz1, iz2, and Iz3 are three constant temperature coefficient currents.

In some embodiments, the first current subtractor comprises a MOS tube m1a, a MOS tube m2a, a MOS tube m3a, a MOS tube m4a, a MOS tube m5a and a MOS tube m6a;

The drain electrode of the MOS tube m1a is connected with the current source Ip, the grid electrode of the MOS tube m1a is in short circuit with the drain electrode of the MOS tube m1a and is connected with the grid electrode of the MOS tube m2a, and the source electrode of the MOS tube m1a is grounded;

the drain electrode of the MOS tube m2a is connected with the drain electrode of the MOS tube m3a and the input end of the first proportional amplifier, and the source electrode of the MOS tube m2a is grounded;

The source electrode of the MOS tube m3a is connected with the source electrode of the MOS tube m4a and is connected with a system power supply, the grid electrode of the MOS tube m3a is connected with the grid electrode of the MOS tube m4a, and the drain electrode of the MOS tube m4a is in short circuit with the grid electrode of the MOS tube m4a and is connected with the drain electrode of the MOS tube m5 a;

the grid electrode of the MOS tube m5a is connected with the grid electrode of the MOS tube m6a, the source electrode of the MOS tube m5a is grounded, the drain electrode of the MOS tube m6a is connected with the current source Iz1 and is in short circuit with the grid electrode of the MOS tube m6a, and the source electrode of the MOS tube m6a is grounded.

In some embodiments, the second current subtractor comprises a MOS tube m1b, a MOS tube m2b, a MOS tube m3b, a MOS tube m4b, a MOS tube m5b and a MOS tube m6b;

The drain electrode of the MOS tube m1b is connected with the current source Iz2, the grid electrode of the MOS tube m1b is in short circuit with the drain electrode of the MOS tube m1b and is connected with the grid electrode of the MOS tube m2b, and the source electrode of the MOS tube m1b is grounded;

the drain electrode of the MOS tube m2b is connected with the drain electrode of the MOS tube m3b and the input end of the second proportional amplifier, and the source electrode of the MOS tube m2b is grounded;

The source electrode of the MOS tube m3b is connected with the source electrode of the MOS tube m4b and is connected with the system power supply, the grid electrode of the MOS tube m3b is connected with the grid electrode of the MOS tube m4b, and the drain electrode of the MOS tube m4b is in short circuit with the grid electrode of the MOS tube m4b and is connected with the drain electrode of the MOS tube m5 b;

The grid electrode of the MOS tube m5b is connected with the grid electrode of the MOS tube m6b, the source electrode of the MOS tube m5b is grounded, the drain electrode of the MOS tube m6b is connected with the current source Ip and is in short circuit with the grid electrode of the MOS tube m6b, and the source electrode of the MOS tube m6b is grounded.

In some embodiments, the first proportional amplifier comprises a MOS transistor Mo, a MOS transistor m1.

The drain electrode and the grid electrode of the MOS tube Mo are connected with the drain electrodes of the MOS tubes m2a and m3a, and the source electrode of the MOS tube Mo is grounded;

the grid electrodes of the MOS tube M1-MOS tube Mm are connected with the grid electrode of the MOS tube M0, the drain electrodes of the MOS tube M1-MOS tube Mm are connected with the input end of the current adder, and the source electrodes of the MOS tube M1-MOS tube Mm are grounded.

In some embodiments, the second proportional amplifier comprises: MOS tube Qo, MOS tube Q1.. N is a natural number greater than 2;

the drain electrode and the grid electrode of the MOS tube Qo are connected with the drain electrodes of the MOS tubes m2b and m3b, and the source electrode of the MOS tube Qo is connected with the system power supply;

the grid electrodes of the MOS tube Q1-MOS tube Qn are connected with the grid electrode of the MOS tube Q1, the drain electrodes of the MOS tube Q1-MOS tube Qn are connected with the input end of the current adder, and the source electrodes of the MOS tube Q1-MOS tube Qn are connected with the system power supply.

In some embodiments, the current adder includes a MOS tube V1 and a MOS tube V2;

The drain electrode of the MOS tube V1 is connected with the drain electrode of the MOS tube Mm and the drain electrode of the MOS tube Q1., the drain electrode of the MOS tube V1 is also connected with the current source Iz3, the grid electrode of the MOS tube V1 is in short circuit with the drain electrode of the MOS tube V1, the grid electrode of the MOS tube V1 is also connected with the grid electrode of the MOS tube V2, the source electrode of the MOS tube V1 and the source electrode of the MOS tube V2 are grounded, and the drain electrode of the MOS tube V2 outputs the bias current source Io.

The invention also provides a radio frequency power amplifier which comprises the current bias generating circuit with controllable temperature coefficient.

The current bias generating circuit with controllable temperature coefficient has the advantages that the circuit provides the bias current Io with controllable temperature coefficient, the temperature coefficients of different temperature areas are respectively self-controllable, the flexibility and the precision of the bias current are improved, finer bias current control is provided for the radio frequency power amplifier, and the performance of the radio frequency power amplifier is improved.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1 is a schematic diagram of a controllable temperature coefficient current bias generation circuit of the present invention;

FIG. 2 is a graph of the current source of the controllable temperature coefficient current bias generation circuit of the present invention;

FIG. 3 is a circuit diagram of a controllable temperature coefficient current bias generation circuit of the present invention;

FIG. 4 is a circuit diagram of a first current subtractor of the controllable temperature coefficient current bias generation circuit of FIG. 1;

FIG. 5 is a circuit diagram of a second current subtractor of the controllable temperature coefficient current bias generation circuit of FIG. 1;

Fig. 6 is a circuit simulation diagram of the bias current and temperature of the controllable temperature coefficient current bias generation circuit of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

As shown in fig. 1, the temperature coefficient controllable current bias generation circuit of the present invention includes a first current subtractor 100, a second current subtractor 200, a first proportional amplifier 300, a second proportional amplifier 400, and a current adder 500.

Specifically, a first input end of the first current subtractor 100 is connected to a current source Ip, a second input end of the first current subtractor 100 is connected to a current source Iz1, an output end of the first current subtractor 100 is connected to an input end of the first proportional amplifier 300, an output end of the first proportional amplifier 300 is connected to an input end of the current adder 500, a first input end of the second current subtractor 200 is connected to a current source Iz2, a second input end of the second current subtractor 200 is connected to a current source Ip, an output end of the second current subtractor 200 is connected to an input end of the second proportional amplifier 400, an output end of the second proportional amplifier 400 is connected to an input end of the current adder 500, an input end of the current adder 500 is also connected to a current source Iz3, and an output end of the current adder 500 outputs a bias current source Io.

The whole temperature area is divided into a low temperature area, a high temperature area and a normal temperature area, wherein a current source Ip is an original positive temperature coefficient current, current sources Iz1, iz2 and Iz3 are respectively three constant temperature coefficient currents, the value of Iz1 is the highest value of Ip in a low temperature section, the value of Iz2 is the lowest value of Ip in the low temperature section, iz3 is a certain value corresponding to Ip in the normal temperature section, and specifically, the relation of the current sources Ip, iz1, iz2 and Iz3 is shown in figure 2.

The current bias generating circuit with controllable temperature coefficient provides bias current Io with controllable temperature coefficient, and the temperature coefficients of different temperature areas are respectively self-controllable, so that the flexibility and precision of the bias current are improved, finer bias current control is provided for the radio frequency power amplifier, and the performance of the radio frequency power amplifier is improved.

Further, in some embodiments, the first current subtractor 100 employs a simple current mirror circuit, and the first current subtractor 100 includes a MOS transistor m1a, a MOS transistor m2a, a MOS transistor m3a, a MOS transistor m4a, a MOS transistor m5a, and a MOS transistor m6a.

Specifically, as shown in fig. 3, a drain of the MOS transistor m1a (i.e., a first input end of the first current subtractor 100) is connected to a current source Ip, a gate of the MOS transistor m1a is shorted to a drain of the MOS transistor m1a and connected to a gate of the MOS transistor m2a, a source of the MOS transistor m1a is grounded, a drain of the MOS transistor m2a is connected to a drain of the MOS transistor m3a and connected to an input end of the first proportional amplifier 300, a source of the MOS transistor m2a is grounded, a source of the MOS transistor m3a is connected to a source of the MOS transistor m4a and connected to a system power supply Vcc, a gate of the MOS transistor m3a is connected to a gate of the MOS transistor m4a, a drain of the MOS transistor m4a is shorted to a gate of the MOS transistor m4a and connected to a drain of the MOS transistor m5a, a gate of the MOS transistor m5a is connected to a gate of the MOS transistor m6a, a source of the MOS transistor m5a is grounded, and a drain of the MOS transistor m6a (i.e.e., a second input end of the first current subtractor 100) is connected to a current source Iz1 and connected to a gate of the MOS transistor m6 a.

Wherein m1a, m2a, m5a and m6a are N-type MOS transistors, and m3a and m4a are P-type MOS transistors. The MOS tube m1a and the MOS tube m2a, the MOS tube m3a and the MOS tube m4a, and the MOS tube m5a and the MOS tube m6a form 3 groups of current mirror circuits, the MOS tube m1a, the MOS tube m4a and the MOS tube m6a are equivalent to diodes, the MOS tube m2a is conducted and the drain current is Ip, the MOS tube m5a is conducted and the drain current is Iz1, the MOS tube m3a is conducted and the drain current is Iz1, and then the output currents of the drains of the MOS tube m2a and the MOS tube m3a (namely the output end current of the first current subtracter 100) are Iz1-Ip.

Further, in some embodiments, the second current subtractor 200 employs a simple current mirror circuit, and the second current subtractor 200 includes a MOS transistor m1b, a MOS transistor m2b, a MOS transistor m3b, a MOS transistor m4b, a MOS transistor m5b, and a MOS transistor m6b.

Specifically, the second current subtractor 200 employs a simple current mirror circuit, the drain of the MOS transistor m1b (i.e., the first input end of the second current subtractor 200) is connected to the current source Iz2, the gate of the MOS transistor m1b is shorted to the drain of the MOS transistor m1b and connected to the gate of the MOS transistor m2b, the source of the MOS transistor m1b is grounded, the drain of the MOS transistor m2b is connected to the drain of the MOS transistor m3b and connected to the input end of the second proportional amplifier 400, the source of the MOS transistor m2b is grounded, the source of the MOS transistor m3b is connected to the source of the MOS transistor m4b and connected to the system power Vcc, the gate of the MOS transistor m3b is connected to the gate of the MOS transistor m4b, the drain of the MOS transistor m4b is shorted to the gate of the MOS transistor m5b, the gate of the MOS transistor m5b is connected to the gate of the MOS transistor m6b, the source of the MOS transistor m5b is grounded, and the drain of the MOS transistor m6b (i.e.e., the second input end of the second current subtractor 200) is connected to the Ip and connected to the gate of the MOS transistor m6 b.

Wherein, m1b, m2b, m5b and m6b are N type MOS tubes, and m3b and m4b are P type MOS tubes. The MOS tube m1b and the MOS tube m2b, the MOS tube m3b and the MOS tube m4b, and the MOS tube m5b and the MOS tube m6b form 3 groups of current mirror circuits, the MOS tube m1b, the MOS tube m4b and the MOS tube m6b are equivalent to diodes, the MOS tube m2b is conducted and the drain current is Iz2, the MOS tube m5b is conducted and the drain current is Iz2, the MOS tube m3b is conducted and the drain current is Ip, and the output currents of the drains of the MOS tube m2b and the MOS tube m3b (namely the output end current of the second current subtracter 200) are Ip-Iz2.

Further, in some embodiments, the first current subtractor 100 and the second current subtractor 200 employ a current mirror circuit of a cascode.

Further, in some embodiments, the first proportional amplifier 300 includes a MOS transistor Mo, a MOS transistor M1.

The MOS transistor M1-MOS transistor Mm has gates connected with the gates of the MOS transistors Mo (i.e. the output end of the first current subtracter 100), drains of the MOS transistors M1-MOS transistor Mm are connected with the input end of the current adder 500, and sources of the MOS transistors M1-MOS transistor Mm are grounded.

The MOS tube Mo and the MOS tube M1-MOS tube Mm are N-type MOS tubes, and the grid electrode and the drain electrode of the MOS tube Mo are in short circuit, which is equivalent to a diode. The MOS transistors M1-M are conducted and output currents equal to the grid electrodes (i.e. the currents Iz1-Ip at the output ends of the first current subtracter 100) at the drain electrodes, namely, each drain electrode of the MOS transistors M1-M outputs the currents Iz1-Ip, the output end of the first proportional amplifier 300 outputs M paths of currents, and the output current value of the first proportional amplifier 300 is M (Iz 1-Ip).

Further, in some embodiments, the second proportional amplifier 400 includes a MOS transistor Qo, a MOS transistor Q1..

Specifically, the drain electrode and the grid electrode of the MOS transistor Qo are connected with the drain electrodes of the MOS transistors m2b and m3b, the source electrode of the MOS transistor Qo is grounded, the grid electrodes of the MOS transistors Q1-Qn are all connected with the grid electrode of the MOS transistor Qo (namely the output end of the second current subtracter 200), the drain electrodes of the MOS transistors Q1-Qn are all connected with the input end of the current adder 500, and the source electrodes of the MOS transistors Q1-Qn are all grounded.

The MOS tube Qo and the MOS tube Q1-Qn are P-type MOS tubes, and the grid electrode and the drain electrode of the MOS tube Qo are in short circuit, which is equivalent to a diode. The MOS transistors Q1-Qn are conducted and output currents equal to the grid electrode (i.e. the currents Ip-Iz2 at the output end of the first current subtracter 100) at the drain electrodes, i.e. each drain electrode of the MOS transistors Q1-Qn outputs the currents Ip-Iz2, then the output end of the second proportional amplifier 400 outputs n paths of currents, and the output current value of the second proportional amplifier 400 is n (Ip-Iz 2).

Further, in some embodiments, current adder 500 includes MOS transistor V1 and MOS transistor V2.

Specifically, the drain of the MOS tube V1 is connected with the drain of the MOS tube M1. The drain of the MOS tube Mm and the drain of the MOS tube Q1.. The drain of the MOS tube Qn is also connected with a current source Iz3, the grid of the MOS tube V1 is in short circuit with the drain electrode of the MOS tube V1, the grid of the MOS tube V1 is also connected with the grid of the MOS tube V2, the source electrode of the MOS tube V1 and the source electrode of the MOS tube V2 are grounded, and the drain electrode of the MOS tube V2 outputs a bias current source Io.

The MOS tube V1 and the MOS tube V2 are both N-type MOS tubes, the short circuit of the drain electrode and the grid electrode of the MOS tube V1 is equivalent to a diode, the MOS tube V2 is conducted and the drain electrode outputs bias current Io, the value of the current Io is equal to the current value of the grid electrode of the MOS tube V2, namely the input value of the current adder 500, and the value of the bias current Io is shown in formula 3:

Equation 3 Io=Iz3-m (Iz 1-Ip) +n (Ip-Iz 2)

In the low temperature section, the current source Iz2> Iz1> Ip, at this time, the MOS transistor m3b pulls up its own node to the system power supply Vcc, so that Ip-iz2=0, the MOS transistor Qo is turned off, that is, the output current of the second current subtractor 200 is 0, the output current of the second proportional amplifier 400 is 0, and the lower the temperature is, the smaller the Ip value is, (Iz 1-Ip) the larger the difference value is, the larger the output current of the first current subtractor 100 is, and the value of the bias current Io is as shown in formula 4:

Equation 4 io=iz3-m (Iz 1-Ip)

When the value of Ip gradually approaches the normal temperature section lower limit Iz1, the output of the first current subtractor 100 approaches 0, and at this time, the value of the output bias current Io in the low temperature section is io=iz3.

From equation 4, it can be deduced that the temperature coefficient of the bias current source Io of the low temperature section is as shown in equation 5:

Equation 5:

Wherein Ip and Io are currents at normal temperature, the two values are equal, T is temperature, tcp is a positive temperature coefficient value of the current Ip, therefore, the temperature coefficient of the bias current Io in the low temperature section is a positive temperature coefficient, and the value can be controlled to be m times the positive temperature coefficient value of the initial current Ip.

In the high temperature section, ip > Iz2> Iz1, at this time, the MOS transistor m2a pulls down the drain node to the system ground GND, so that Iz 1-ip=0, the MOS transistor Mo is turned off, that is, the output current of the first current subtractor 100 is 0, the output current of the first proportional amplifier 300 is 0, the higher the temperature is, the larger the Ip value is, (Ip-Iz 2) the larger the difference value is, the larger the output value of the second current subtractor 200 is, and the value of the bias current Io is as shown in formula 6:

Equation 6 io=iz3+n (Ip-Iz 2)

When the value of Ip approaches the normal temperature section upper limit Iz2, the output of the second current subtractor 200 approaches 0, and at this time, the value of the output bias current Io in the low temperature section is io=iz3.

From equation 6, it can be deduced that the temperature coefficient of the bias current source Io of the high temperature section is as shown in equation 7:

Equation 7:

wherein Ip and Io are currents at normal temperature, the two values are equal, T is temperature, tcp is a positive temperature coefficient value of the current Ip, therefore, the temperature coefficient of the bias current Io in the high temperature section is a positive temperature coefficient, and the value can be controlled to be n times the positive temperature coefficient value of the initial current Ip.

In the normal temperature range, the output currents of the current source Iz2> Ip > Iz1, the output currents of the first current subtractor 100 and the second current subtractor 200 are both 0, and at this time, the output bias current io=iz3.

It will be appreciated that the upper and lower range values of the normal temperature section may be adjusted by adjusting the magnitudes of Iz1 and Iz2 according to actual needs.

Specifically, as shown in fig. 6, fig. 6 is a circuit simulation diagram of bias current and temperature according to the present invention, wherein in a low temperature section, the temperature coefficient of bias current Io is m times of the positive temperature coefficient value of initial current Ip, that is, the amplification factor of first proportional amplifier 300 is different, the slope of the curve in the low temperature section is different, in a high temperature section, the temperature coefficient of bias current Io is n times of the positive temperature coefficient value of initial current Ip, that is, the amplification factor of second proportional amplifier 400 is different, the slope of the curve in the low temperature section is different, in a normal temperature stage, bias current io=iz3, in a normal temperature stage, is a horizontal line segment, and the two end points of the line segment are the values of Iz1 and Iz 2.

Alternatively, the first current subtractor 100 and the second current subtractor 200 each employ a simple current mirror circuit, and in some embodiments, the first current subtractor 100 and the second current subtractor 200 may also employ a current mirror circuit structure of a cascode.

Specifically, the first current subtractor 100 includes MOS transistors m1A-m6A and MOS transistors m1A-m6A, wherein the MOS transistors m1A, m2A, m A and m6A are N-type MOS transistors, and the MOS transistors m3A and m4A are P-type MOS transistors.

The drain electrode of the MOS tube m1A is connected to the current source Ip and is in short circuit with the grid electrode, the grid electrode of the MOS tube m1A is connected with the grid electrode of the MOS tube m2A, the source electrode of the MOS tube m1A is connected with the drain electrode of the MOS tube m1A, the drain electrode of the MOS tube m1A is in short circuit with the grid electrode of the MOS tube m2A, the source electrode of the MOS tube m1A is grounded, the source electrode of the MOS tube m2A is connected with the drain electrode of the MOS tube m2A, the drain electrode of the MOS tube m2A is connected with the drain electrode of the MOS tube m3A, the drain electrode of the MOS tube m2A is also connected with the input end (namely the drain electrode of the MOS tube Mo) of the first proportional amplifier 300, and the source electrode of the MOS tube m2A is grounded. The drain current of the MOS transistor m2a is the mirror current of the current source Ip.

The drain electrode of the MOS tube m6A is connected with the current source Iz1, the drain electrode of the MOS tube m6A is in short circuit with the grid electrode, the grid electrode of the MOS tube m6A is connected with the grid electrode of the MOS tube m5A, the source electrode of the MOS tube m6A is connected with the drain electrode of the MOS tube m6A, the drain electrode of the MOS tube m6A is in short circuit with the grid electrode of the MOS tube m5A, the source electrode of the MOS tube m6A is grounded, the source electrode of the MOS tube m5A is connected with the drain electrode of the MOS tube m5A, the drain electrode of the MOS tube m5A is connected with the drain electrode of the MOS tube m4A, and the source electrode of the MOS tube m5A is grounded. The drain current of the MOS transistor m5a is the mirror current of the current source Iz 1.

The drain electrode and the grid electrode of the MOS tube m4A are in short circuit, the grid electrode of the MOS tube m3A is connected with the grid electrode of the MOS tube m4A, the source electrode of the MOS tube m4A is connected with the drain electrode of the MOS tube m4A, the drain electrode of the MOS tube m4A is in short circuit with the grid electrode, the grid electrode of the MOS tube m4A is connected with the grid electrode of the MOS tube m3A, the source electrodes of the MOS tube m4A and the MOS tube m3A are connected with the triggering system power supply Vcc, the source electrode of the MOS tube m3A is connected with the drain electrode of the MOS tube m3A, and the drain electrode of the MOS tube m3A is connected with the input end (namely the drain electrode of the MOS tube Mo) of the first proportional amplifier 300. The drain current of the MOS tube m3A is the mirror current of the current source Iz1, and the output current of the first proportional amplifying circuit is Iz1-Ip.

Further, in some embodiments, the second current subtractor 200 includes MOS transistors m1B-m6B and MOS transistors m1B-m6B, wherein the MOS transistors m1B, m2B, m B and m6B are N-type MOS transistors, and the MOS transistors m3B and m4B are P-type MOS transistors.

The drain electrode of the MOS tube m1B is connected to the current source Iz2 and is in short circuit with the grid electrode, the grid electrode of the MOS tube m1B is connected with the grid electrode of the MOS tube m2B, the source electrode of the MOS tube m1B is connected with the drain electrode of the MOS tube m1B, the drain electrode of the MOS tube m1B is in short circuit with the grid electrode of the MOS tube m2B, the source electrode of the MOS tube m1B is grounded, the source electrode of the MOS tube m2B is connected with the drain electrode of the MOS tube m2B, the drain electrode of the MOS tube m2B is connected with the drain electrode of the MOS tube m3B, the drain electrode of the MOS tube m2B is also connected with the input end (namely the drain electrode of the MOS tube Qo) of the second proportional amplifier 400, and the source electrode of the MOS tube m2B is grounded. The drain current of the MOS transistor m2b is the mirror current of the current source Iz 2.

The drain electrode of the MOS tube m6B is connected with a current source Ip, the drain electrode of the MOS tube m6B is in short circuit with the grid electrode, the grid electrode of the MOS tube m6B is connected with the grid electrode of the MOS tube m5B, the source electrode of the MOS tube m6B is connected with the drain electrode of the MOS tube m6B, the drain electrode of the MOS tube m6B is in short circuit with the grid electrode of the MOS tube m5B, the source electrode of the MOS tube m6B is grounded, the source electrode of the MOS tube m5B is connected with the drain electrode of the MOS tube m5B, the drain electrode of the MOS tube m5B is connected with the drain electrode of the MOS tube m4B, and the source electrode of the MOS tube m5B is grounded. The drain current of the MOS transistor m5b is the mirror current of the current source Ip.

The drain electrode and the grid electrode of the MOS tube m4B are in short circuit, the grid electrode of the MOS tube m3B is connected with the grid electrode of the MOS tube m4B, the source electrode of the MOS tube m4B is connected with the drain electrode of the MOS tube m4B, the drain electrode of the MOS tube m4B is in short circuit with the grid electrode, the grid electrode of the MOS tube m4B is connected with the grid electrode of the MOS tube m3B, the source electrodes of the MOS tube m4B and the MOS tube m3B are connected with the triggering system power Vcc, the source electrode of the MOS tube m3B is connected with the drain electrode of the MOS tube m3B, and the drain electrode of the MOS tube m3B is connected with the input end (namely the drain electrode of the MOS tube Qo) of the second proportional amplifier 400. The drain current of the MOS tube m3B is the mirror current of the current source Ip, and the output current of the first proportional amplifying circuit is Ip-Iz1.

Further, the first proportional amplifier 300, the second proportional amplifier 400 and the current adder 500 all adopt simple current mirror circuit structures, and in some embodiments, the first proportional amplifier 300, the second proportional amplifier 400 and the current adder 500 may also adopt a cascode current mirror circuit structure.

The current bias generating circuit with controllable temperature coefficient has the advantages that the circuit provides the bias current Io with controllable temperature coefficient, the temperature coefficients of different temperature areas are respectively self-controllable, the flexibility and the precision of the bias current are improved, finer bias current control is provided for the radio frequency power amplifier, and the performance of the radio frequency power amplifier is improved.

The invention also provides a radio frequency power amplifier, and the bias current of the radio frequency power amplifier is provided by the current bias generating circuit with the controllable temperature coefficient disclosed by the embodiment of the invention.

The above embodiments are provided to illustrate the technical concept and features of the present invention and are intended to enable those skilled in the art to understand the content of the present invention and implement the same according to the content of the present invention, and not to limit the scope of the present invention. All equivalent changes and modifications made with the scope of the claims should be covered by the claims.

It will be understood that modifications and variations will be apparent to those skilled in the art from the foregoing description, and it is intended that all such modifications and variations be included within the scope of the following claims.

Claims (8)

1. The current bias generating circuit with controllable temperature coefficient is characterized by comprising a first current subtracter, a second current subtracter, a first proportional amplifier, a second proportional amplifier and a current adder;

A first input end of the first current subtracter is connected with a current source Ip, a second input end of the first current subtracter is connected with a current source Iz1, an output end of the first current subtracter is connected with an input end of the first proportional amplifier, and an output end of the first proportional amplifier is connected with an input end of the current adder;

The first input end of the second current subtracter is connected with a current source Iz2, the second input end of the second current subtracter is connected with the current source Ip, the output end of the second current subtracter is connected with the input end of the second proportional amplifier, and the output end of the second proportional amplifier is connected with the input end of the current adder;

the input end of the current adder is also connected with a current source Iz3, and the output end of the current adder outputs a bias current source Io;

The first current subtracter and the second current subtracter both adopt a current mirror circuit.

2. The controllable-temperature-coefficient current bias generation circuit according to claim 1, wherein the current source Ip is an original positive-temperature-coefficient current, and the current sources Iz1, iz2, and Iz3 are three constant-temperature-coefficient currents.

3. The controllable temperature coefficient current bias generation circuit according to claim 2, wherein the first current subtractor comprises a MOS tube m1a, a MOS tube m2a, a MOS tube m3a, a MOS tube m4a, a MOS tube m5a and a MOS tube m6a;

The drain electrode of the MOS tube m1a is connected with the current source Ip, the grid electrode of the MOS tube m1a is in short circuit with the drain electrode of the MOS tube m1a and is connected with the grid electrode of the MOS tube m2a, and the source electrode of the MOS tube m1a is grounded;

the drain electrode of the MOS tube m2a is connected with the drain electrode of the MOS tube m3a and the input end of the first proportional amplifier, and the source electrode of the MOS tube m2a is grounded;

The source electrode of the MOS tube m3a is connected with the source electrode of the MOS tube m4a and is connected with a system power supply, the grid electrode of the MOS tube m3a is connected with the grid electrode of the MOS tube m4a, and the drain electrode of the MOS tube m4a is in short circuit with the grid electrode of the MOS tube m4a and is connected with the drain electrode of the MOS tube m5 a;

the grid electrode of the MOS tube m5a is connected with the grid electrode of the MOS tube m6a, the source electrode of the MOS tube m5a is grounded, the drain electrode of the MOS tube m6a is connected with the current source Iz1 and is in short circuit with the grid electrode of the MOS tube m6a, and the source electrode of the MOS tube m6a is grounded.

4. The controllable temperature coefficient current bias generation circuit according to claim 3, wherein the second current subtractor comprises a MOS tube m1b, a MOS tube m2b, a MOS tube m3b, a MOS tube m4b, a MOS tube m5b and a MOS tube m6b;

The drain electrode of the MOS tube m1b is connected with the current source Iz2, the grid electrode of the MOS tube m1b is in short circuit with the drain electrode of the MOS tube m1b and is connected with the grid electrode of the MOS tube m2b, and the source electrode of the MOS tube m1b is grounded;

the drain electrode of the MOS tube m2b is connected with the drain electrode of the MOS tube m3b and the input end of the second proportional amplifier, and the source electrode of the MOS tube m2b is grounded;

The source electrode of the MOS tube m3b is connected with the source electrode of the MOS tube m4b and is connected with the system power supply, the grid electrode of the MOS tube m3b is connected with the grid electrode of the MOS tube m4b, and the drain electrode of the MOS tube m4b is in short circuit with the grid electrode of the MOS tube m4b and is connected with the drain electrode of the MOS tube m5 b;

The grid electrode of the MOS tube m5b is connected with the grid electrode of the MOS tube m6b, the source electrode of the MOS tube m5b is grounded, the drain electrode of the MOS tube m6b is connected with the current source Ip and is in short circuit with the grid electrode of the MOS tube m6b, and the source electrode of the MOS tube m6b is grounded.

5. The controllable temperature coefficient current bias generation circuit of claim 4, wherein the first proportional amplifier comprises a MOS transistor Mo, a MOS transistor m1.

The drain electrode and the grid electrode of the MOS tube Mo are connected with the drain electrodes of the MOS tubes m2a and m3a, and the source electrode of the MOS tube Mo is grounded;

the grid electrodes of the MOS tube M1-MOS tube Mm are connected with the grid electrode of the MOS tube M0, the drain electrodes of the MOS tube M1-MOS tube Mm are connected with the input end of the current adder, and the source electrodes of the MOS tube M1-MOS tube Mm are grounded.

6. The controllable-temperature-coefficient current bias generation circuit of claim 5, wherein the second proportional amplifier comprises a MOS transistor Qo, a MOS transistor Q1..

The drain electrode and the grid electrode of the MOS tube Qo are connected with the drain electrodes of the MOS tubes m2b and m3b, and the source electrode of the MOS tube Qo is connected with the system power supply;

the grid electrodes of the MOS tube Q1-MOS tube Qn are connected with the grid electrode of the MOS tube Q1, the drain electrodes of the MOS tube Q1-MOS tube Qn are connected with the input end of the current adder, and the source electrodes of the MOS tube Q1-MOS tube Qn are connected with the system power supply.

7. The controllable temperature coefficient current bias generation circuit according to claim 6, wherein the current adder comprises a MOS transistor V1 and a MOS transistor V2;

The drain electrode of the MOS tube V1 is connected with the drain electrode of the MOS tube Mm and the drain electrode of the MOS tube Q1., the drain electrode of the MOS tube V1 is also connected with the current source Iz3, the grid electrode of the MOS tube V1 is in short circuit with the drain electrode of the MOS tube V1, the grid electrode of the MOS tube V1 is also connected with the grid electrode of the MOS tube V2, the source electrode of the MOS tube V1 and the source electrode of the MOS tube V2 are grounded, and the drain electrode of the MOS tube V2 outputs the bias current source Io.

8. A radio frequency power amplifier comprising a controllable temperature coefficient current bias generation circuit as claimed in any one of claims 1-7.