CN116049081B - A SMBus slave digital module design method and device - Google Patents

Abstract

The application discloses a design method and a device of an SMBus slave digital module, wherein the SMBus slave digital module firstly receives a device address, a read-write address and read data sent by master equipment, converts the read-write address and the read data into AHB bus information, then accesses a plurality of intra-chip modules in a chip according to the AHB bus information, and finally receives feedback data returned by the plurality of intra-chip modules. The SMBus slave digital module enables the master device outside the chip to access the content of the SMBus slave digital module and the registers in each on-chip module, and the content is not required to pass through JTAG or SWD interfaces. The SMBus slave digital module can also support multiple access formats, and the master device outside the chip can determine whether to access 1 or multiple words by issuing different command codes, so that the access efficiency of the SMBus read-write register is effectively improved.

Description

A SMBus slave digital module design method and device

Technical Field

The present application relates to the technical field of chip data transmission, and in particular to a method and device for designing an SMBus slave digital module.

Background technique

SMBus is a low-speed communication used in mobile PC or desktop PC systems. It mainly controls the devices on the motherboard and collects corresponding information through a cheap and powerful bus (consisting of two lines). SMBus provides a control bus for tasks such as system and power management. In systems using SMBus, messages are sent and received between devices through SMBus instead of using separate control lines, which can save the number of device pins.

At present, the SMBus module with AMBA APBslave interface generated by Synopsys Design Ware is generally implemented in ASIC chip design. Compared with other SMBus devices, it is an SMBus master. There are also ASIC chip designs that implement SMBus modules, but the access format they support is relatively simple, the read and write efficiency is relatively low, and the AHB interface of AMBA2.0 specification is not implemented. The data received by the SMBus bus is sent out through the AHB interface. If there are other master modules in the chip that also need to access the registers in the chip, they cannot cooperate with the arbitration module that complies with the AMBA 2.0 specification to do a good job of access arbitration.

Summary of the invention

The purpose of this application is to provide a SMBus slave digital module design method and device to overcome the existing technical defects, so that the master device can access the contents of each register in the chip through the SMBus interface, without having to go through the JTAG or SWD interface, and can also support reading and writing multiple words, effectively improving the access efficiency of the SMBus read and write registers.

The purpose of this application is achieved through the following technical solutions:

In a first aspect, the present application proposes a SMBus slave digital module design method, characterized in that the method is applied to an SMBus slave digital module in a chip chip, the chip chip is connected to a master device, and the SMBus slave digital module is connected to multiple on-chip modules in the chip chip, including:

The SMBus slave digital module receives the device address, read/write address and read data sent by the master device;

The SMBus slave digital module converts the read/write address and the read data into AHB bus information;

The SMBus slave digital module accesses multiple on-chip modules in the chip according to the AHB bus information;

The SMBus slave digital module receives feedback data returned by the multiple on-chip modules.

Optionally, the SMBus slave digital module includes an SMBus control component and an AHB_CTRL control component, and the step of the SMBus slave digital module converting the read/write address and the read data into AHB bus information includes:

The SMBus control component sends the received read/write address to the AHB_CTRL control component via the ADDR bus;

The SMBus control component sends the received read data to the AHB_CTRL control component via the WDATA bus;

The AHB_CTRL control component converts the read/write address and the read data into AHB bus information. Optionally, the AHB bus information complies with the AMBA 2.0 timing specification.

Optionally, the step of the SMBus slave digital module receiving a device address, a read/write address, and read data sent by a master device includes:

The master device sends a startup instruction to start the SMBus slave digital module;

The master device sends a device address to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal;

If the read/write bit in the device address is 0, it indicates that a write operation is to be performed, the master device sends a command code, and the SMBus slave digital module feeds back an ACK signal;

The master device sends a byte count code, and the SMBus slave digital module feeds back an ACK signal;

The master device sends a read/write address, and the SMBus slave digital module feeds back an ACK signal;

If the read/write bit in the device address is 1, it indicates that a read operation is to be performed, and the SMBus slave digital module feeds back an ACK signal;

The AHB_CTRL control component initiates a read request to multiple on-chip modules to obtain read data according to the read and write addresses sent by the master device.

Optionally, after the master device sends a command code and the SMBus slave digital module feeds back an ACK signal, the following further comprises:

If the check bit in the command code is 1, the master device sends a check code, and the SMBus slave digital module feeds back an ACK signal.

In a second aspect, the present application further proposes an SMBus slave digital module design device, which is applied to an SMBus slave digital module in a chip chip, the chip chip is connected to a master device, and the SMBus slave digital module is connected to multiple on-chip modules in the chip chip, including:

The SMBus slave digital module receives the device address, read/write address and read data sent by the master device;

The SMBus slave digital module converts the read/write address and the read data into AHB bus information;

The SMBus slave digital module accesses multiple on-chip modules in the chip according to the AHB bus information;

The SMBus slave digital module receives feedback data returned by the multiple on-chip modules.

In a third aspect, the present application further proposes a computer device, comprising a processor and a memory, wherein the memory stores a computer program, and the computer program is loaded and executed by the processor to implement the SMBus slave digital module design method as described in any one of the first aspects.

In a fourth aspect, the present application further proposes a computer-readable storage medium, wherein a computer program is stored in the storage medium, and the computer program is loaded and executed by a processor to implement the SMBus slave digital module design method as described in any one of the first aspects.

The above main scheme of the present application and its further options can be freely combined to form multiple schemes, all of which are schemes that can be adopted and claimed for protection in the present application; and in the present application, (non-conflicting options) can also be freely combined with each other and with other options. After understanding the scheme of the present application, those skilled in the art can understand that there are many combinations based on the prior art and common knowledge, all of which are technical schemes to be protected by the present application, and they are not exhaustively listed here.

The beneficial effects of this application are:

First, the SMBus slave digital module proposed in the embodiment of the present application enables a master device outside the chip to access the contents of the registers in the SMBus slave digital module and each on-chip module within the chip, without necessarily going through a JTAG or SWD interface.

Second, the SMBus slave digital module proposed in the embodiment of the present application can support multiple access formats, and the master device outside the chip can decide whether to access one or multiple words by issuing different command codes, thereby effectively improving the access efficiency of the SMBus read and write registers.

Third, due to the existence of the AHB interface of the AMBA 2.0 specification, data is transmitted through the AHB interface. If there are other master modules in the chip that also need to access the registers in the chip, they can cooperate with the arbitration module that complies with the AMBA 2.0 specification to perform access arbitration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the connection relationship between the SMBus module and other modules in the prior art.

FIG. 2 shows a schematic diagram of the connection between the SMBus slave digital module and the master device proposed in an embodiment of the present application.

FIG3 shows an internal schematic diagram of an SMBus slave digital module provided in an embodiment of the present application.

FIG. 4 is a schematic diagram showing a master device reading a register word in an SMBus slave digital module.

FIG. 5 shows a schematic diagram of the access format of function=011.

FIG. 6 shows a schematic diagram of the access format of function=100.

FIG. 7 shows a schematic diagram of the access format of function=101.

FIG. 8 shows a schematic diagram of the access format of function=110.

FIG. 9 is a schematic diagram showing the access format of function=111.

Detailed ways

The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

Please refer to Figure 1, which shows the connection relationship between the SMBus module and other modules in the prior art. In the prior art, the SMBus in the chip is a slave module relative to the off-chip SMBus device, and the off-chip SMBus device is a slave device relative to the SMBus in the chip. The master-slave relationship between the two is that the SMBus in the chip is the master, and the off-chip SMBus device is the slave. Other modules in the chip configure the SMBus module through the APB bus interface, and then the SMBus actively initiates access requests to other SMBus devices outside the chip. Compared with other SMBus devices, the access format supported by the off-chip SMBus device is relatively simple and the read and write efficiency is relatively low. In addition, since the SMBus in the chip uses the APB bus interface to communicate with each on-chip module of the chip chip, the AHB interface of the AMBA 2.0 specification cannot be implemented. The data received by the SMBus bus is sent out through the AHB interface. If there are other master modules in the chip that also need to access the registers in the chip, it is impossible to cooperate with the arbitration module that complies with the AMBA 2.0 specification to do a good job of access arbitration.

Therefore, in order to solve the above-mentioned problems, the present application proposes a SMBus slave digital module design method, so that the on-chip Bus module is an SMBus slave digital module relative to the SMBus device outside the chip, with the SMBus device outside the chip as the master and the on-chip Bus module as the slave, which is different from the master-slave relationship in the prior art. It not only supports multiple access formats, but also effectively improves the read and write efficiency of the host to other modules in the chip through the SMBus, and realizes the AHB interface of the AMBA 2.0 specification. The SMBus slave digital module design method is described in detail below.

Please refer to FIG. 2 , which shows a schematic diagram of the connection between the SMBus slave digital module and the master device proposed in an embodiment of the present application. The chip chip includes the SMBus slave digital module, which is connected to the SMBus bus interface of the chip chip using a data line and a clock line. The other end of the interface is connected to the master device, which is another SMBus device. The on-chip SMBus slave digital module is also connected to multiple on-chip modules in the chip chip through the AHBbus. The SMBus slave digital module design method includes the following steps:

The SMBus slave digital module receives the device address, read/write address and read data sent by the master device;

The SMBus slave digital module converts the read/write address and read data into AHB bus information;

The SMBus slave digital module accesses multiple on-chip modules in the chip according to the AHB bus information;

The SMBus slave digital module receives feedback data returned by multiple on-chip modules.

Based on FIG. 2, please refer to FIG. 3, which shows an internal schematic diagram of an SMBus slave digital module provided in an embodiment of the present application. The SMBus slave digital module includes an SMBus control component and an AHB_CTRL control component. The SMBus control component and the AHB_CTRL control component are connected via an ADDR bus, a read data bus, and a write data bus. The steps of converting the read/write address and the read data into AHB bus information include:

The SMBus control component sends the received read and write addresses to the AHB_CTRL control component via the ADDR bus;

The SMBus control component sends the received read data to the AHB_CTRL control component via the WDATA bus;

The AHB_CTRL control component converts the read and write addresses and read data into AHB bus information.

The Smaster device outside the chip uses the data line and clock line to send read and write addresses and read data to the SMBus bus interface of the chip chip, and converts them into AHB bus information that complies with the AMBA 2.0 timing specification through the AHB_CTRL control component. The AHB bus information then accesses multiple on-chip modules in the chip chip, and the on-chip modules will feedback the read data and pass it to the SMBus bus interface through the SMBus slave digital module until it finally reaches the master device.

Optionally, the sub-steps of the SMBus slave digital module receiving the device address, read/write address, and read data sent by the master device include:

The master device sends a startup command to start the SMBus slave digital module;

The master device sends the device address to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal;

If the read/write bit in the device address is 0, it indicates that a write operation is to be performed. The master device sends a command code, and the SMBus slave digital module feeds back an ACK signal.

The master device sends a byte count code, and the SMBus slave digital module feeds back an ACK signal;

The master device sends the read/write address, and the SMBus slave digital module feeds back an ACK signal;

If the read/write bit in the device address is 1, it indicates that a read operation is to be performed, and the SMBus slave digital module feeds back an ACK signal;

The AHB_CTRL control component initiates read requests to multiple on-chip modules to obtain read data based on the read and write addresses sent by the master device.

If the check bit in the command code is 1, the master device sends a check code and the SMBus slave digital module feeds back an ACK signal.

It is worth noting that the SMBus slave digital module proposed in the embodiment of the present application can support multiple access formats. The off-chip SMBus device can decide to access 1 word (32 bits), 2 words (64 bits), 4 words (128 bits) or multiple words by issuing different command codes. Please refer to Figure 4, which shows a schematic diagram of a master device reading a register 1 word in the SMBus slave digital module, and combined with Table 1, Table 1 shows the fields corresponding to the command code.

Table 1

The white background data in Figure 4 is sent by the master device, and the gray background data is fed back to the master device by the SMBus slave digital module. Table 2 shows the fields corresponding to another command code:

Table 2

In combination with FIG. 4 , Table 1 and Table 2, taking FUCTION=3'b110 as an example, the access format flow is as follows:

1. The master device initiates the START command to start the SMBus slave digital module;

2. The master device sends the device address slave address (7'h20) to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal to the master device;

3. Since the read/write bit (W/R bit) is 0, it indicates that a write operation is to be performed. At this time, the master device sends an 8-bit command code. The 0th END bit of the command code is 0, and the 1st START bit is 1, indicating the first transaction in a command across multiple transactions. The 2nd to 4th bits indicate FUCTION = 010 for a short format read word operation. The 7th PEC check is 1, the master device sends a check code, and the SMBus slave digital module feeds back an ACK signal.

4. The master device sends an 8-bit byte count code (byte count) to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal;

5. The master device sends four 8-bit read/write addresses (offset bytes) to the SMBus slave digital module. The SMBus slave digital module feeds back an ACK signal each time it receives an 8-bit read/write address.

6. Since the 7th PEC checksum in the 8-bit command code sent by the master device is 1, the master device continues to send an 8-bit pec checksum to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal.

7. The master device sends a STOP command.

8. Since the second to fourth bits of the 8-bit command code sent by the master device indicate FUCTION = 010 for a short-format read operation, the master device initiates a START start command to start the SMBus slave digital module;

9. The device address slave address (7’h20) is sent to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal to the master device;

10. If the read/write bit (W/R bit) is 0, it indicates that a write operation is to be performed. At this time, the master device sends an 8-bit command code. The 0th END bit of the command code is 1, and the 1st START bit is 0, indicating the last transaction in a command spanning multiple transactions. The 2nd to 4th bits indicate FUCTION = 010 for a short format read word operation. The 7th PEC check is 1, the master device sends a check code, and the SMBus slave digital module feeds back an ACK signal.

11. The master device initiates the START command to start the SMBus slave digital module.

12. The master device sends the device address slave address (7’h20) to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal to the master device;

13. If the read/write bit (W/R bit) is 1, it indicates that a read operation is to be performed, and the SMBus slave digital module feeds back an ACK signal;

14. The SMBus slave digital module sends the four 8-bit read/write addresses (offset bytes) in step 5 to multiple on-chip modules in the chip through the AHBCTRL control component, obtains the corresponding 32-bit read data RDATA and stores it;

15. The SMBus slave digital module sends the 8-bit byte count code (byte count) in step 4 to the master device, and the master device feeds back an ACK signal;

16. The SMBus slave digital module sends the stored 32-bit read data RDATA to the master device. Every time an 8-bit read data RDATA is sent, the master device will feedback an ACK signal.

17. Repeat step 14. The SMBus slave digital module adds 4 to the 32-bit read/write address, initiates an AHB read request to multiple on-chip modules in the chip through the AHB CTRL control component, obtains the corresponding 32-bit read data RDATA and stores it. The SMBus slave digital module sends the stored 32-bit read data RDATA to the master device. Every time an 8-bit read data RDATA is sent, the master device can feedback an ACK signal.

18. Repeat step 14. The SMBus slave digital module adds 8 to the 32-bit read/write address, initiates an AHB read request to multiple on-chip modules in the chip through the AHB CTRL control component, obtains the corresponding 32-bit read data RDATA and stores it. The SMBus slave digital module sends the stored 32-bit read data RDATA to the master device. Every time an 8-bit read data RDATA is sent, the master device can feedback an ACK signal.

19. Repeat step 14. The SMBus slave digital module adds 12 to the 32-bit read/write address, initiates an AHB read request to multiple on-chip modules in the chip through the AHB CTRL control component, obtains the corresponding 32-bit read data RDATA and stores it. The SMBus slave digital module sends the stored 32-bit read data RDATA to the master device. Every time an 8-bit read data RDATA is sent, the master device can feedback an ACK signal.

20. Since the 7th PEC checksum in the 8-bit command code sent by the master device is 1, the master device continues to send an 8-bit pec checksum to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal.

21. The master device sends a STOP command.

In addition, since FUCTION has different fields, Figures 5 to 9 show schematic diagrams of access formats under different FUCTION fields. Figure 5 shows a schematic diagram of the access format of function=011, where the master device writes one word of the register in the SMBus slave digital module; Figure 6 shows a schematic diagram of the access format of function=100, where the master device continuously reads two words of the register in the SMBus slave digital module; Figure 7 shows a schematic diagram of the access format of function=101, where the master device continuously writes two words of the register in the SMBus slave digital module; Figure 8 shows a schematic diagram of the access format of function=110, where the master device continuously reads four words of the register in the SMBus slave digital module; Figure 9 shows a schematic diagram of the access format of function=111, where the master device continuously writes four words of the register in the SMBus slave digital module. The process of this access format is as shown above and will not be repeated here.

Compared with the prior art, the embodiments of the present application have the following beneficial effects:

First, the SMBus slave digital module proposed in the embodiment of the present application enables a master device outside the chip to access the contents of the registers in the SMBus slave digital module and each on-chip module within the chip, without necessarily going through a JTAG or SWD interface.

Second, the SMBus slave digital module proposed in the embodiment of the present application can support multiple access formats, and the master device outside the chip can decide whether to access one or multiple words by issuing different command codes, thereby effectively improving the access efficiency of the SMBus read and write registers.

Third, due to the existence of the AHB interface of the AMBA 2.0 specification, data is transmitted through the AHB interface. If there are other master modules in the chip that also need to access the registers in the chip, they can cooperate with the arbitration module that complies with the AMBA 2.0 specification to perform access arbitration.

In addition, an embodiment of the present application also provides an SMBus slave digital module design device, which is applied to the SMBus slave digital module in the chip chip, the chip chip is connected to the master device, and the SMBus slave digital module is connected to multiple on-chip modules in the chip chip.

The SMBus slave digital module receives the device address, read/write address and read data sent by the master device;

The SMBus slave digital module converts the read/write address and read data into AHB bus information;

The SMBus slave digital module accesses multiple on-chip modules in the chip according to the AHB bus information;

The SMBus slave digital module receives feedback data returned by multiple on-chip modules.

The embodiment of the present application provides a computer device, which can implement the steps in any embodiment of the SMBus slave digital module design method provided in the embodiment of the present application. Therefore, the beneficial effects of the SMBus slave digital module design method provided in the embodiment of the present application can be achieved. Please refer to the previous embodiment for details, which will not be repeated here.

Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling related hardware through instructions, and the instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. To this end, an embodiment of the present application provides a storage medium, which stores multiple instructions, and the instructions can be loaded by a processor to execute the steps of any embodiment of the SMBus slave digital module design method provided in the embodiment of the present application.

The storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

Since the instructions stored in the storage medium can execute the steps in any SMBus slave digital module design method embodiment provided in the embodiments of the present application, the beneficial effects that can be achieved by any SMBus slave digital module design method provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (6)

1. The SMBus slave digital module design method is characterized in that the method is applied to an SMBus slave digital module in a chip, the chip is connected with a master device, the SMBus slave digital module is connected with a plurality of on-chip modules in the chip, and the SMBus slave digital module comprises an SMBus control component and an AHB_CTRL control component, and comprises the following steps:

the master device sends a starting instruction to enable the SMBus slave digital module to be started;

the master device sends a device address to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal;

If the read-write bit in the device address is 0, indicating that writing operation is to be performed, the master device sends a command code, and the SMBus slave digital module feeds back an ACK signal;

The master device sends byte count numbers, and the SMBus slave digital module feeds back ACK signals;

the master device sends a read-write address, and the SMBus slave digital module feeds back an ACK signal;

if the read-write bit 1 in the equipment address indicates that the read operation is to be performed, the SMBus slave digital module feeds back an ACK signal;

the AHB_CTRL control component initiates a read request to a plurality of intra-chip modules according to the read-write address sent by the master device to obtain read data;

the SMBus control part sends the received read-write address to the AHB_CTRL control part through an ADDR bus;

the SMBus control component sends the received read data to the AHB_CTRL control component over a WDATA bus;

the ahb_ctrl control means converting the read-write address and the read data into AHB bus information;

the SMBus slave digital module accesses a plurality of intra-chip modules in the chip according to the AHB bus information;

The SMBus slave digital module receives feedback data returned by the plurality of intra-chip modules.

2. The SMBus slave digital module design method of claim 1, wherein said AHB bus information complies with AMBA 2.0 timing specification.

3. The SMBus slave digital module design method of claim 1, wherein after said master device sends a command code, said SMBus slave digital module feedback ACK signal further comprises:

And if the check bit in the command code is 1, the master device sends out the check code, and the SMBus slave digital module feeds back an ACK signal.

4. An SMBus slave digital module design apparatus, wherein the apparatus is applied to an SMBus slave digital module in a chip, the chip is connected to a master device, the SMBus slave digital module is connected to a plurality of on-chip modules in the chip, the SMBus slave digital module includes an SMBus control component and an ahb_ctrl control component, and the apparatus comprises:

the master device sends a starting instruction to enable the SMBus slave digital module to be started;

the master device sends a device address to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal;

If the read-write bit in the device address is 0, indicating that writing operation is to be performed, the master device sends a command code, and the SMBus slave digital module feeds back an ACK signal;

The master device sends byte count numbers, and the SMBus slave digital module feeds back ACK signals;

the master device sends a read-write address, and the SMBus slave digital module feeds back an ACK signal;

if the read-write bit 1 in the equipment address indicates that the read operation is to be performed, the SMBus slave digital module feeds back an ACK signal;

the AHB_CTRL control component initiates a read request to a plurality of intra-chip modules according to the read-write address sent by the master device to obtain read data;

the SMBus control part sends the received read-write address to the AHB_CTRL control part through an ADDR bus;

the SMBus control component sends the received read data to the AHB_CTRL control component over a WDATA bus;

the ahb_ctrl control means converting the read-write address and the read data into AHB bus information;

the SMBus slave digital module accesses a plurality of intra-chip modules in the chip according to the AHB bus information;

The SMBus slave digital module receives feedback data returned by the plurality of intra-chip modules.

5. A computer device comprising a processor and a memory, wherein the memory has stored therein a computer program that is loaded and executed by the processor to implement the SMBus slave digital module design method of any of claims 1-3.

6. A computer-readable storage medium, wherein a computer program is stored in the storage medium, and the computer program is loaded and executed by a processor to implement the SMBus slave digital module design method of any one of claims 1-3.