CN116054788B - Signal generating circuit - Google Patents
Signal generating circuit Download PDFInfo
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- CN116054788B CN116054788B CN202310065028.2A CN202310065028A CN116054788B CN 116054788 B CN116054788 B CN 116054788B CN 202310065028 A CN202310065028 A CN 202310065028A CN 116054788 B CN116054788 B CN 116054788B
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- 101100048260 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UBX2 gene Proteins 0.000 description 14
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- G—PHYSICS
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
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Abstract
本申请提供一种信号生成电路，包括触发电路、选择电路和输出电路。触发电路接收目标时钟信号并响应于接收到的初始命令信号，生成与初始命令信号相对应的第一命令信号。选择电路接收模式寄存器的编码信号，生成第一选择信号和第二选择信号，编码信号对应于不同突发长度模式。输出电路接收第一命令信号并响应于接收到的第一选择信号和第二选择信号，生成目标命令信号，目标命令信号的有效电平长度与突发长度模式对应。因此，信号生成电路对于不同突发长度模式能够生成不同有效电平长度的目标命令信号，不同有效电平长度的目标命令信号控制ODT打开不同时间，从而有效控制ODT的打开时间。
The present application provides a signal generating circuit, including a trigger circuit, a selection circuit and an output circuit. The trigger circuit receives a target clock signal and generates a first command signal corresponding to the initial command signal in response to the received initial command signal. The selection circuit receives a coding signal of a mode register, generates a first selection signal and a second selection signal, and the coding signal corresponds to different burst length modes. The output circuit receives the first command signal and generates a target command signal in response to the received first selection signal and the second selection signal, and the effective level length of the target command signal corresponds to the burst length mode. Therefore, the signal generating circuit can generate target command signals with different effective level lengths for different burst length modes, and target command signals with different effective level lengths control the ODT to open at different times, thereby effectively controlling the opening time of the ODT.
Description
Technical Field
The present application relates to the field of semiconductor memory technologies, and in particular, to a signal generating circuit.
Background
ODT (On Die Termination, on-die termination resistance) is a function provided in DRAM technology to reduce termination signal reflection. When data is written, in order to achieve impedance matching of input signals, the quality of the input signals is guaranteed, ODT is turned on after a write control signal is received, and the quality of the write signals of the DRAM is directly affected at the time point when the ODT is turned on.
How to effectively control the time to turn on ODT is thus a significant issue.
Disclosure of Invention
The application provides a signal generating circuit which generates a target command signal corresponding to an effective level length according to a burst length and effectively controls the ODT opening time.
In a first aspect, the present application provides a signal generating circuit comprising:
A trigger circuit configured to receive a target clock signal and, in response to a received initial command signal, generate a first command signal corresponding to the initial command signal;
a selection circuit configured to receive encoded signals of the mode register, the encoded signals corresponding to different burst length modes, and to generate corresponding first and second selection signals;
And an output circuit configured to receive the first command signal and generate a target command signal in response to the received first and second selection signals, the target command signal having an effective level length corresponding to the burst length mode.
In some embodiments, the trigger circuit includes N cascaded triggers;
The clock input end of the trigger of each stage receives the target clock signal, the trigger input end of the trigger of the first stage receives an initial command signal, the non-inverting output end of the trigger of the previous stage is connected with the trigger input end of the trigger of the next stage, and the non-inverting output end of the trigger of each stage outputs the first command signal.
In some embodiments, the output circuit includes a first SR latch having an S input connected to a non-inverting output of the flip-flop of the first stage, an R input connected to a non-inverting output of the flip-flop of the nth stage, and a Q output outputting the target command signal.
In some embodiments, the output circuit further comprises a first selector and a second selector;
The control end of the first selector receives a first selection signal, the first input end of the first selector is connected with the positive phase output end of the second-stage trigger, and the second input end of the first selector is connected with the positive phase output end of the N-1-th-stage trigger;
The control end of the second selector receives a second selection signal, the first input end of the second selector is connected with the positive phase output end of the trigger of the second stage, and the second input end of the second selector is connected with the positive phase output end of the trigger of the M-th stage, wherein M is 2< N-1.
In some embodiments, the output circuit includes a first output circuit configured to receive the first command signal and a first sub-command signal, the first sub-command signal having an effective level length twice as long as the first command signal, the first sub-command signal being delayed by a period of one target clock signal by the first command signal, and generate an intermediate command signal.
In some embodiments, the output circuit further includes a second output circuit configured to receive the intermediate command signal and generate a second command signal in response to the first select signal and/or a second select signal;
If the received first selection signal or the second selection signal is valid, the second command signal is an inverse signal of the intermediate command signal.
In some embodiments, the output circuit further comprises a third output circuit configured to receive the second command signal, generate a target command signal;
In some embodiments, the first output circuit includes a first nand gate, a second nand gate, a third nand gate, and a fourth nand gate;
The first input end of the first NAND gate is connected with the normal phase output end of the trigger of the first stage, the second input end of the first NAND gate is connected with the normal phase output end of the trigger of the second stage, and the output end of the first NAND gate outputs a first intermediate command signal;
the first input end of the second NAND gate is connected with the positive phase output end of the trigger of the third stage, the second input end of the second NAND gate is connected with the positive phase output end of the trigger of the fourth stage, and the output end of the second NAND gate outputs a second intermediate command signal;
the first input end of the third NAND gate is connected with the positive phase output end of the trigger of the fifth stage, the second input end of the third NAND gate is connected with the positive phase output end of the trigger of the sixth stage, and the output end of the third NAND gate outputs a third intermediate command signal;
The first input end of the fourth NAND gate is connected with the positive phase output end of the trigger of the seventh stage, the second input end of the fourth NAND gate is connected with the positive phase output end of the trigger of the eighth stage, and the output end of the fourth NAND gate outputs a fourth intermediate command signal.
In some embodiments, the second output circuit includes a fifth nand gate, a sixth nand gate, a seventh nand gate, and an eighth nand gate;
the first input end and the second input end of the fifth NAND gate are connected with the output end of the first NAND gate, the output end of the fifth NAND gate outputs a fifth intermediate command signal, and the fifth intermediate command signal is an inverted signal of the first intermediate command signal;
The first input end of the sixth NAND gate is connected with the output end of the second NAND gate, the second input end of the sixth NAND gate receives a first selection signal, the output end of the sixth NAND gate outputs a sixth intermediate command signal, and if the first selection signal is valid, the sixth intermediate command signal is an inverted signal of the second intermediate command signal;
the first input end of the seventh NAND gate is connected with the output end of the third NAND gate, the second input end of the seventh NAND gate receives a second selection signal, the output end of the seventh NAND gate outputs a seventh intermediate command signal, and if the second selection signal is valid, the seventh intermediate command signal is an inverted signal of the third intermediate command signal;
the first input end of the eighth NAND gate is connected with the output end of the fourth NAND gate, the second input end of the eighth NAND gate receives a second selection signal, the output end of the eighth NAND gate outputs an eighth intermediate command signal, and if the second selection signal is valid, the eighth intermediate command signal is an inversion signal of the fourth intermediate command signal.
In some embodiments, the third output circuit includes a ninth nand gate, a tenth nand gate, a first nor gate;
The first input end of the ninth NAND gate is connected with the output end of the fifth NAND gate, the second input end of the ninth NAND gate is connected with the output end of the sixth NAND gate, and the output end of the ninth NAND gate outputs a ninth intermediate command signal;
The first input end of the tenth NAND gate is connected with the output end of the seventh NAND gate, the second input end of the tenth NAND gate is connected with the output end of the eighth NAND gate, and the output end of the tenth NAND gate outputs a tenth intermediate command signal;
The first input end of the first NOR gate is connected with the output end of the ninth NAND gate, the second input end of the first NOR gate is connected with the output end of the tenth NAND gate, and the output end of the first NOR gate outputs the target command signal.
In some embodiments, the trigger circuit includes a first trigger having a clock input that receives the target clock signal, a trigger input that receives the initial command signal, and a non-inverting output that outputs the first command signal.
In some embodiments, the output circuit includes a second flip-flop, a third flip-flop, and a fourth flip-flop;
the clock input end of the second trigger receives the first command signal, the trigger input end of the second trigger is connected with the negative phase output end, and the positive phase output end of the second trigger outputs a first sub-target command signal;
The clock input end of the third trigger is connected with the positive phase output end of the second trigger, the trigger input end of the third trigger is connected with the negative phase output end, the control end of the third trigger receives the first selection signal, and the positive phase output end of the third trigger outputs a second sub-target command signal;
The clock input end of the fourth trigger is connected with the positive phase output end of the third trigger, the trigger input end of the fourth trigger is connected with the negative phase output end, the control end of the fourth trigger receives the second selection signal, and the positive phase output end of the fourth trigger outputs a third sub-target command signal;
If the first selection signal is invalid, the second selection signal is invalid, and a first sub-target command signal is output as a target command signal;
If the first selection signal is valid, the second selection signal is invalid, and a second sub-target command signal is output as a target command signal;
and if the first selection signal is valid, the second selection signal is valid, and a third sub-target command signal is output as a target command signal.
In some embodiments, a gating circuit is further included and is configured to receive an initial clock signal and, in response to a received first gating signal, generate a target clock signal corresponding to the first gating signal.
In some embodiments, the gating circuit includes an eleventh nand gate, a first input terminal of the eleventh nand gate receiving the initial clock signal, a second input terminal receiving the first gating signal, and if the first gating signal is valid, triggering the outputting of the target clock signal.
The signal generating circuit provided by the application comprises a trigger circuit, a selection circuit and an output circuit. The trigger circuit receives the target clock signal and generates a first command signal corresponding to the initial command signal in response to the received initial command signal. The selection circuit receives the encoded signals of the mode register, generates a first selection signal and a second selection signal, and the encoded signals correspond to different burst length modes. The output circuit receives the first command signal and generates a target command signal in response to the received first and second selection signals, the effective level length of the target command signal corresponding to the burst length mode. Therefore, the signal generating circuit can generate target command signals with different effective level lengths for different burst length modes, and the target command signals with different effective level lengths control the ODT to be opened for different times, so that the opening time of the ODT is effectively controlled.
Drawings
In order to more clearly illustrate the application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a signal generating circuit according to an embodiment of the present application;
Fig. 2 is a schematic circuit diagram of a signal generating circuit according to an embodiment of the present application;
FIG. 3 is a timing diagram of a signal generating circuit according to an embodiment of the present application;
fig. 4 is a schematic circuit diagram of another signal generating circuit according to an embodiment of the present application;
Fig. 5 is a timing diagram of a signal generating circuit according to an embodiment of the present application;
FIG. 6 is a schematic circuit diagram of a signal generating circuit according to an embodiment of the present application;
fig. 7 is a schematic circuit diagram of a gate control circuit according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
Fig. 1 is a schematic circuit diagram of a signal generating circuit according to an embodiment of the present application. Referring to fig. 1, a signal generating circuit provided in an embodiment of the present application includes a trigger circuit 101, a selection circuit 102, and an output circuit 103. The trigger circuit 101 is configured to receive the target clock signal CLK and, in response to the received initial command signal CMD, generate a first command signal CMD1 corresponding to the initial command signal CMD. The selection circuit 102 is configured to receive the encoded signals of the mode register, generate the first selection signal SEL0 and the second selection signal SEL1, and the encoded signals correspond to different burst length modes. The output circuit 103 is configured to receive the first command signal CMD1 and generate a target command signal ODT CMD in response to the received first and second selection signals SEL0 and SEL1, the effective level length of the target command signal ODT CMD corresponding to the burst length mode. Therefore, the signal generating circuit can generate target command signals with different effective level lengths according to different burst length modes, the target command signals with different effective level lengths control different ODT opening times, the ODT opening time is effectively controlled, and electric energy is saved. For example, when the burst length corresponding to the burst length mode is smaller, the effective level length of the target command signal is smaller, the control ODT opening time is shorter, and when the burst length corresponding to the burst length mode is larger, the effective level length of the target command signal is larger, and the control ODT opening time is longer.
In practical applications, the clock input terminal of the trigger circuit 101 receives the target clock signal CLK, the trigger input terminal of the trigger circuit 101 receives the initial command signal CMD, and the output terminal of the trigger circuit 101 outputs the first command signal CMD1 corresponding to the initial command signal CMD. The first command signal CMD1 may be understood as a delayed signal of the initial command signal CMD, which is valid in a different clock period than the initial command signal CMD.
The trigger circuit 101 may include N cascaded flip-flops, where N is a positive integer greater than 1, the clock input of each stage of flip-flop receives the target clock signal CLK, the trigger input of the first stage of flip-flop serves as the trigger input of the trigger circuit 101 and receives the initial command signal CMD, the non-inverting output of the previous stage of flip-flop is connected to the trigger input of the next stage of flip-flop, the non-inverting output of each stage of flip-flop outputs the first command signal CMD1, and different delay signals of the initial command signal CMD may be generated according to the number of flip-flops, so that the first command signal CMD1 is valid in different target clock periods.
For example, referring to fig. 2, the trigger circuit 101 may include nine flip-flops, which are respectively denoted as a first stage flip-flop 1011, a second stage flip-flop 1012, a third stage flip-flop 1013, a fourth stage flip-flop 1014, a fifth stage flip-flop 1015, a sixth stage flip-flop 1016, a seventh stage flip-flop 1017, an eighth stage flip-flop 1018, and a ninth stage flip-flop 1019.
The clock input terminal of the flip-flop 1011 of the first stage is used as the clock input terminal of the flip-flop 101 to receive the target clock signal CLK, the trigger input terminal of the flip-flop 1011 of the first stage is used as the trigger input terminal of the flip-flop 101 to receive the initial command signal CMD, the non-inverting output terminal of the flip-flop 1011 of the first stage is connected to the trigger input terminal of the flip-flop 1012 of the second stage, and the non-inverting output terminal of the flip-flop 1011 of the first stage outputs the first command signal Q1. The clock input terminal of the flip-flop 1012 of the second stage receives the target clock signal CLK, the non-inverting output terminal of the flip-flop 1012 of the second stage is connected to the trigger input terminal of the flip-flop 1013 of the third stage, and the non-inverting output terminal of the flip-flop 1012 of the second stage outputs the first command signal Q2. The clock input terminal of the flip-flop 1013 of the third stage receives the target clock signal CLK, the non-inverting output terminal of the flip-flop 1013 of the third stage is connected to the trigger input terminal of the flip-flop 1014 of the fourth stage, and the non-inverting output terminal of the flip-flop 1013 of the third stage outputs the first command signal Q3. The clock input terminal of the flip-flop 1014 of the fourth stage receives the target clock signal CLK, the non-inverting output terminal of the flip-flop 1014 of the fourth stage is connected to the trigger input terminal of the flip-flop 1015 of the fifth stage, and the non-inverting output terminal of the flip-flop 1014 of the fourth stage outputs the first command signal Q4. The clock input terminal of the flip-flop 1015 of the fifth stage receives the target clock signal CLK, the non-inverting output terminal of the flip-flop 1015 of the fifth stage is connected to the trigger input terminal of the flip-flop 1016 of the sixth stage, and the non-inverting output terminal of the flip-flop 1015 of the fifth stage outputs the first command signal Q5. The clock input terminal of the flip-flop 1016 of the sixth stage receives the target clock signal CLK, the non-inverting output terminal of the flip-flop 1016 of the sixth stage is connected to the trigger input terminal of the flip-flop 1017 of the seventh stage, and the non-inverting output terminal of the flip-flop 1016 of the sixth stage outputs the first command signal Q6. The clock input terminal of the flip-flop 1017 of the seventh stage receives the target clock signal CLK, the non-inverting output terminal of the flip-flop 1017 of the seventh stage is connected to the trigger input terminal of the flip-flop 1018 of the eighth stage, and the non-inverting output terminal of the flip-flop 1017 of the seventh stage outputs the first command signal Q7. The clock input terminal of the flip-flop 1018 of the eighth stage receives the target clock signal CLK, the non-inverting output terminal of the flip-flop 1018 of the eighth stage is connected to the trigger input terminal of the flip-flop 1019 of the ninth stage, and the non-inverting output terminal of the flip-flop 1018 of the eighth stage outputs the first command signal Q8. The clock input terminal of the flip-flop 1019 of the ninth stage receives the target clock signal CLK, and the non-inverting output terminal of the flip-flop 1019 of the ninth stage outputs the first command signal Q9. The number of flip-flops in the flip-flop circuit 101 is determined according to the specific case, and is not limited here. In practical applications, the clock input terminals of the flip-flop 1012 of the second stage to the flip-flop 1019 of the ninth stage may be connected to the clock input terminal of the flip-flop 1011 of the first stage, and receive the target clock signal CLK.
Fig. 5 is a timing chart of a signal generating circuit according to an embodiment of the present application, referring to fig. 5, when an initial command signal CMD is valid in a first clock period CLK1, a first command signal Q1 output by a flip-flop 1011 of a first stage is valid in a second clock period CLK2, a first command signal Q2 output by a flip-flop 1012 of a second stage is valid in a third clock period CLK3, a first command signal Q3 output by a flip-flop 1013 of a third stage is valid in a fourth clock period CLK4, a first command signal Q4 output by a flip-flop 1014 of a fourth stage is valid in a fifth clock period CLK5, a first command signal Q5 output by a flip-flop 1015 of a fifth stage is valid in a sixth clock period CLK6, a first command signal Q6 output by a flip-flop 1016 of a sixth stage is valid in a seventh clock period CLK7, a first command signal Q7 output by a flip-flop 1017 of a seventh stage is valid in an eighth clock period CLK8, and a first command signal Q8 output by a flip-flop 1014 of a eighth stage is valid in a ninth clock period CLK 8.
The selection circuit 102 may generate the first selection signal SEL0 and the second selection signal SEL1 upon receiving the encoding signal of the mode register. The encoded signals correspond to different burst length modes, which may include a first burst length mode BL8, a second burst length mode BL16, and a third burst length mode BL32. When the coding information of the mode register is 01, the first burst length mode BL8 is corresponding. When the code signal of the mode register is 00, the second burst length mode BL16 is corresponding. When the code signal of the mode register is 1X (X represents not care), the third burst length mode BL32 is corresponding.
In some embodiments, referring to fig. 2, the output circuit 103 includes a first SR latch 104, an S input terminal of the first SR latch 104 is connected to a non-inverting output terminal of a flip-flop 1011 of the first stage, an R input terminal of the first SR latch 104 is connected to a non-inverting output terminal of a flip-flop of the nth stage, and a Q output terminal of the first SR latch 104 outputs the target command signal ODT CMD, so that a delay period of the initial command signal CMD is controlled by the number of flip-flops connected to the first SR latch 104 to generate the target command signal ODT CMD corresponding to the burst length mode.
For example, the S input terminal of the first SR latch 104 is connected to the non-inverting output terminal of the first stage flip-flop 1011, the R input terminal of the first SR latch 104 is connected to the non-inverting output terminal of the third stage flip-flop 1013, the first command signal Q1 output by the first stage flip-flop 1011 is active (active low) in the second clock cycle CLK2, the first command signal Q3 output by the third stage flip-flop 1013 is active (active low) in the fourth clock cycle CLK4, and the target command signal ODT CMD output by the Q output terminal of the first SR latch 104 is active (active high) in the second clock cycle CLK2 to the fourth clock cycle CLK4, that is, is active in the three clock cycles 3 CLK.
In this embodiment, referring to fig. 2, the output circuit 103 may further include a first not gate 105, where an input terminal of the first not gate 105 is connected to a Q output terminal of the first SR latch 104, receives the target command signal ODT CMD, and outputs an inverted signal of the target command signal ODT CMD. Then when the target command signal ODT CMD output by the first SR latch 104 is active (active high) in the second to fourth clock cycles CLK2 to CLK4, the inverted signal of the target command signal ODT CMD output by the first not gate 105 is also active (active low) in the second to fourth clock cycles CLK2 to CLK 4.
In this embodiment, referring to fig. 2, the output circuit 103 may further include a first selector 106 and a second selector 107, where the control end of the first selector 106 receives the first selection signal SEL0, the first input end of the first selector 106 is connected to the positive output end of the second-stage flip-flop 1012, the second input end of the first selector 106 is connected to the positive output end of the N-1-th stage flip-flop, the control end of the second selector 106 receives the second selection signal SEL1, the first input end of the second selector 107 is connected to the positive output end of the second-stage flip-flop 1012, and the second input end of the second selector 107 is connected to the positive output end of the M-th stage flip-flop, where M is a positive integer greater than 2 and less than N-1. The first selector 106 and the second selector 107 can control the number of use of the flip-flops in the flip-flop circuit 101 under the control of the first selection signal SEL0 and the second selection signal SEL1, thereby adjusting the delay period of the initial command signal CMD to generate the target command signal ODT CMD corresponding to the burst length mode.
Specifically, when the first selection signal SEL0 received by the first selector 106 is a high level signal, the first selector 106 may be connected to the non-inverting output terminal of the flip-flop 1012 of the second stage and the trigger input terminal of the flip-flop of the N-th stage, and when the first selection signal SEL0 received by the first selector 106 is a low level signal, the first selector 106 may be connected to the non-inverting output terminal of the flip-flop of the N-1-th stage and the trigger input terminal of the flip-flop of the N-th stage. Similarly, when the second selection signal SEL1 received by the second selector 107 is a high level signal, the second selector 107 may be connected to the non-inverting output terminal of the flip-flop 1012 of the second stage and the trigger input terminal of the m+1th stage, and when the second selection signal SEL1 received by the second selector 107 is a low level signal, the second selector 107 may be connected to the non-inverting output terminal of the flip-flop of the M-th stage and the trigger input terminal of the flip-flop of the m+1th stage.
For example, referring to fig. 2, when N is 9, the first selector 106 may connect the non-inverting output terminal of the second-stage flip-flop 1012 and the trigger input terminal of the ninth-stage flip-flop 1019 when the first selection signal SEL0 received by the first selector 106 is a high-level signal, and the first selector 106 may connect the non-inverting output terminal of the eighth-stage flip-flop 1018 and the trigger input terminal of the ninth-stage flip-flop 1019 when the first selection signal SEL1 received by the first selector 106 is a low-level signal. When M is 6 and the second selection signal SEL1 received by the second selector 107 is a high level signal, the second selector 107 may be connected to the non-inverting output terminal of the flip-flop 1012 of the second stage and the trigger input terminal of the flip-flop 1017 of the seventh stage, and when the second selection signal SEL1 received by the second selector 107 is a low level signal, the second selector 107 may be connected to the non-inverting output terminal of the flip-flop 1016 of the sixth stage and the trigger input terminal of the flip-flop 1017 of the seventh stage.
Corresponding to different burst length modes, when the selection circuit receives the coding information corresponding to the first burst length mode BL8, the generated first selection signal SEL0 is a high-level signal, the first output circuit generates the effective level length of the target command signal ODT_CMD to be two CLK clock cycles, when the selection circuit receives the coding information corresponding to the second burst length mode BL16, the generated first selection signal SEL0 is a low-level signal, the second selection signal SEL1 is a high-level signal, the first output circuit generates the effective level length of the target command signal ODT_CMD to be four CLK clock cycles, when the selection circuit receives the coding information corresponding to the third burst length mode BL32, the generated first selection signal SEL0 is a low-level signal, the second selection signal SEL1 is a low-level signal, and the effective level length of the first output circuit generates the target command signal ODT_CMD to be 8 clock cycles.
In the third burst length mode BL32, according to the DRAM industry standard, the trigger circuit receives two serially transmitted CMD commands, with an interval of 8 clock cycles, cmd_delay being the output signal at the positive output of the first stage flip-flop, delayed by T1 time compared to the received initial command signal, cmd_shift being the output signal at the positive output of the eighth stage flip-flop, delayed by t2+8clk time compared to the received initial command signal, and the second initial command signal being adjacently transmitted being delayed by 8CLK time compared to the first initial command signal, i.e., the second initial command signal does not have a corresponding target command signal output, as shown in fig. 3.
In other embodiments, referring to fig. 4, the output circuit 103 includes a first output circuit 110, where the first output circuit 110 is configured to receive a first command signal CMD1 and a first sub-command signal, and generate an intermediate command signal having an effective level length twice that of the first command signal CMD1, and the first sub-command signal is obtained by delaying the first command signal CMD1 by one period of the target clock signal CLK.
In the present embodiment, referring to fig. 4, the first output circuit 110 includes a first nand gate 111, a second nand gate 112, a third nand gate 113, and a fourth nand gate 114. A first input of the first nand gate 111 receives the first command signal, a second input of the first nand gate 111 receives the first subcommand signal, and an output of the first nand gate 111 outputs the first intermediate command signal CMD11. For example, a first input terminal of the first nand gate 111 is connected to a non-inverting output terminal of the flip-flop 1011 of the first stage, a second input terminal of the first nand gate 111 is connected to a non-inverting output terminal of the flip-flop 1012 of the second stage, and an output terminal of the first nand gate 111 outputs the first intermediate command signal CMD11. It is understood that the first command signal Q2 output by the flip-flop 1012 of the second stage may be regarded as a first subcommand signal. Referring to fig. 5, when the first command signal Q1 output from the flip-flop 1011 of the first stage is valid in the second clock cycle CLK2 and the first command signal Q2 output from the flip-flop 1012 of the second stage is valid in the third clock cycle CLK3, the first intermediate command signal CMD11 is valid in the second clock cycle CLK2 and the third clock cycle CLK3 (the first intermediate command signal CMD11 is valid at high level), that is, is valid in two clock cycles 2 CLK.
A first input of the second nand gate 112 may receive the first command signal, a second input of the second nand gate 112 receives the first subcommand signal, and an output of the second nand gate 112 outputs the second intermediate command signal CMD12. For example, the first input terminal of the second nand gate 112 is connected to the non-inverting output terminal of the flip-flop 1013 of the third stage, the second input terminal of the second nand gate 112 is connected to the non-inverting output terminal of the flip-flop 1014 of the fourth stage, and the output terminal of the second nand gate 112 outputs the second intermediate command signal CMD12. The first command signal Q4 output from the flip-flop 1014 of the fourth stage may be regarded as a first subcommand signal. Referring to fig. 5, when the first command signal Q3 output from the flip-flop 1013 of the third stage is valid in the fourth clock cycle CLK4 and the first command signal Q4 output from the flip-flop 1014 of the fourth stage is valid in the fifth clock cycle CLK5, the second intermediate command signal CMD12 is valid in the fourth clock cycle CLK4 and the fifth clock cycle CLK5 (the second intermediate command signal CMD12 is valid at high level), that is, is valid in two clock cycles 2 CLK.
A first input of the third nand gate 113 receives the first command signal, a second input of the third nand gate 113 receives the first subcommand signal, and an output of the third nand gate 113 outputs a third intermediate command signal CMD13. For example, the first input terminal of the third nand gate 113 is connected to the non-inverting output terminal of the flip-flop 1015 of the fifth stage, the second input terminal of the third nand gate 113 is connected to the non-inverting output terminal of the flip-flop 1016 of the sixth stage, and the output terminal of the third nand gate 113 outputs the third intermediate command signal CMD13. The first command signal Q6 output from the flip-flop 1016 of the sixth stage may be referred to as a first subcommand signal. Referring to fig. 5, when the first command signal Q5 output from the flip-flop 1015 of the fifth stage is valid in the sixth clock period CLK6 and the first command signal Q6 output from the flip-flop 1016 of the sixth stage is valid in the seventh clock period CLK7, the third intermediate command signal CMD13 is valid in the sixth clock period CLK6 and the seventh clock period CLK7 (the third intermediate command signal CMD13 is valid at a high level), that is, is valid in two clock periods 2 CLK.
A first input of the fourth nand gate 114 receives the first command signal, a second input of the fourth nand gate 114 receives the first subcommand signal, and an output of the fourth nand gate 114 outputs a fourth intermediate command signal CMD14. For example, the first input terminal of the fourth nand gate 114 is connected to the non-inverting output terminal of the flip-flop 1017 of the seventh stage, the second input terminal of the fourth nand gate 114 is connected to the non-inverting output terminal of the flip-flop 1018 of the eighth stage, and the output terminal of the fourth nand gate 114 outputs the fourth intermediate command signal CMD14. The first command signal Q8 output by the flip-flop 1018 of the eighth stage may be a first subcommand signal. The first command signal Q7 output by the flip-flop 1017 of the seventh stage is valid for the eighth clock cycle CLK8, and when the first command signal Q8 output by the flip-flop 1018 of the eighth stage is valid for the ninth clock cycle CLK9, the fourth intermediate command signal CMD14 is valid for the eighth clock cycle CLK8 and the ninth clock cycle CLK9 (the fourth intermediate command signal CMD14 is valid for high level), that is, for two clock cycles 2 CLK.
In some embodiments, the output circuit 103 may further include a second output circuit 120, the second output circuit 120 being configured to receive the intermediate command signal and to generate a second command signal in response to the first selection signal and/or the second selection signal, the second command signal being an inverse of the intermediate command signal if the received first selection signal or second selection signal is valid.
In the present embodiment, referring to fig. 4, the second output circuit 120 includes a fifth nand gate 121, a sixth nand gate 122, a seventh nand gate 123, and an eighth nand gate 124. The first input terminal and the second input terminal of the fifth nand gate 121 are connected to the output terminal of the first nand gate 111, and the output terminal of the fifth nand gate 121 outputs a fifth intermediate command signal ODT CMD11, the fifth intermediate command signal ODT CMD11 being an inverted signal of the first intermediate command signal CMD11, and referring to fig. 5, the fifth intermediate command signal ODT CMD11 is valid for the second clock period CLK2 and the third clock period CLK3 (the fifth intermediate command signal ODT CMD11 is valid at a low level).
The first input terminal of the sixth nand gate 122 is connected to the output terminal of the second nand gate 112, the second input terminal of the sixth nand gate 122 receives the first selection signal SEL0, the output terminal of the sixth nand gate 122 outputs the sixth intermediate command signal ODT CMD12, and if the first selection signal is valid, the sixth intermediate command signal ODT CMD12 is the inverse signal CMD12 of the second intermediate command signal. Referring to fig. 5, the sixth intermediate command signal ODT CMD12 is active during the fourth clock period CLK4 and the fifth clock period CLK5 (the sixth intermediate command signal ODT CMD12 is active low).
The first input end of the seventh nand gate 123 is connected to the output end of the third nand gate 113, the second input end of the seventh nand gate 123 receives the second selection signal SEL1, the output end of the seventh nand gate 123 outputs the seventh intermediate command signal ODT CMD13, and if the second selection signal is valid, the seventh intermediate command signal ODT CMD13 is an inverted signal of the third intermediate command signal CMD 13. Referring to fig. 5, the seventh intermediate command signal ODT CMD13 is active during the sixth clock period CLK6 and the seventh clock period CLK7 (the seventh intermediate command signal ODT CMD13 is active low).
The first input terminal of the eighth nand gate 124 is connected to the output terminal of the fourth nand gate 114, the second input terminal of the eighth nand gate 124 receives the second selection signal SEL1, the output terminal of the eighth nand gate 124 outputs the eighth intermediate command signal ODT CMD14, and if the second selection signal is valid, the eighth intermediate command signal ODT CMD14 is an inverted signal of the fourth intermediate command signal CMD 14. Referring to fig. 5, the eighth intermediate command signal ODT CMD14 is active during the eighth clock period CLK8 and the ninth clock period CLK9 (the eighth intermediate command signal ODT CMD14 is active low).
In some embodiments, referring to fig. 4, output circuit 103 may further include a third output circuit 130, third output circuit 130 configured to receive the second command signal and generate the target command signal ODT CMD.
In the present embodiment, the third output circuit 130 includes a ninth nand gate 131, a tenth nand gate 132, and a first nor gate 133. A first input terminal of the ninth nand gate 131 is connected to the output terminal of the fifth nand gate 121, a second input terminal of the ninth nand gate 131 is connected to the output terminal of the sixth nand gate 122, and the output terminal of the ninth nand gate 131 outputs a ninth intermediate command signal CMD21. A first input terminal of the tenth nand gate 132 is connected to the output terminal of the seventh nand gate 123, a second input terminal of the tenth nand gate 132 is connected to the output terminal of the eighth nand gate 124, and the output terminal of the tenth nand gate 132 outputs a tenth intermediate command signal CMD22. A first input terminal of the first nor gate 133 is connected to an output terminal of the ninth nand gate 131, a second input terminal of the first nor gate 133 is connected to an output terminal of the tenth nand gate 132, and an output terminal of the first nor gate 133 outputs the target command signal ODT CMD. Referring to fig. 5, the ninth intermediate command signal CMD21 is active during the second clock period CLK2 to the fifth clock period CLK5 (the ninth intermediate command signal CMD21 is active high), i.e., is active during the four clock periods 4 CLK. The tenth intermediate command signal CMD22 is active in the sixth clock period CLK6 to the ninth clock period CLK9 (the tenth intermediate command signal ODT CMD22 is active high), that is, in the four clock periods 4 CLK. The target command signal ODT CMD3 output by the first nor gate 133 is valid for the second to ninth clock periods CLK2 to CLK9 (the target command signal ODT CMD3 corresponding to the third burst length mode is valid at a low level), i.e., 8CLK is valid for eight clock periods.
Therefore, as shown in fig. 4 and 5, when the first selection signal and the second selection signal received by the second output circuit 120 are inactive, the target command signal output by the third output circuit 130 is the target command signal corresponding to the first burst length mode BL8, and is also the fifth intermediate command signal ODT CMD11, which is active in the second clock period CLK2 and the third clock period CLK 3. When the first selection signal received by the second output circuit 120 is valid and the second selection signal is not valid, the target command signal output by the third output circuit 130 is the target command signal corresponding to the second burst length mode BL16, and is also the inverted signal ODT CMD21 of the ninth intermediate command signal CMD21, which is valid in the second clock period CLK2 to the fifth clock period CLK 5. When both the first selection signal and the second selection signal received by the second output circuit 120 are valid, the target command signal output by the third output current 130 is the target command signal corresponding to the third burst length mode BL32, that is, ODT CMD3, which is valid for the second clock period CLK2 to the ninth clock period CLK 9.
In other embodiments, the trigger circuit 101 may include a first flip-flop, where a clock input terminal of the first flip-flop receives the target clock signal CLK as the clock input terminal of the trigger circuit 101, a trigger input terminal of the first flip-flop receives the initial command signal CMD as the trigger input terminal of the trigger circuit 101, and a non-inverting output terminal of the first flip-flop outputs the first command signal CMD1 as the output terminal of the trigger circuit 101.
The output circuit 103 may be configured to output the first sub-target command signal as the target command signal if the first selection signal is inactive, output the second sub-target command signal as the target command signal if the first selection signal is active, and output the third sub-target command signal as the target command signal if the first selection signal is active.
Referring to fig. 6, the output circuit 103 may include a second flip-flop 1022, a third flip-flop 1023, and a fourth flip-flop 1024, the clock input terminal of the second flip-flop 1022 receiving the first command signal CMD1, the trigger input terminal of the second flip-flop 1022 being connected to the negative phase output terminal, the positive phase output terminal of the second flip-flop 1022 outputting the first sub-target command signal Out1. The clock input end of the third trigger 1023 is connected to the positive phase output end of the second trigger 1022, the trigger input end of the third trigger 1023 is connected to the negative phase output end, the control end of the third trigger 1023 receives the first selection signal, and the positive phase output end of the third trigger 1023 outputs the second sub-target command signal Out2. The clock input terminal of the fourth flip-flop 1024 is connected to the positive phase output terminal of the third flip-flop 1023, the trigger input terminal of the fourth flip-flop 1024 is connected to the negative phase output terminal, the control terminal of the fourth flip-flop 1024 receives the second selection signal, and the positive phase output terminal of the fourth flip-flop 1024 outputs the third sub-target command signal Out3. The first sub-target command signal Out1 is a target command signal corresponding to the first burst length mode BL8, the second sub-target command signal Out2 is a target command signal corresponding to the second burst length mode BL16, and the third sub-target command signal Out3 is a target command signal corresponding to the third burst length mode BL32, so that target command signals corresponding to different burst length modes can be generated.
In some embodiments, referring to fig. 7, the output circuit may further include a Gating circuit 201, and the Gating circuit 201 may be configured to receive the initial clock signal CLK0 and generate a target clock signal corresponding to the first Gating signal clk_gating in response to the received first Gating signal clk_gating. The Gating circuit 201 can generate the target clock signal CLK according to the first Gating signal clk_gating and the initial clock signal CLK0, and the target clock signal CLK outputs the initial clock signal CLK0 only when the first Gating signal clk_gating is valid, thereby achieving the power saving effect.
In this embodiment, referring to fig. 6, the Gating circuit 201 may include an eleventh nand gate 202 and a second nand gate 203, where a first input terminal of the eleventh nand gate 202 receives the initial clock signal CLK0, a second input terminal of the eleventh nand gate 202 receives the first Gating signal clk_gating, and if the first Gating signal clk_gating is valid, an intermediate clock signal is triggered to be output, and an input terminal of the second nand gate 203 is connected to an output terminal of the eleventh nand gate 202, receives the intermediate clock signal, and outputs the target clock signal CLK.
The signal generating circuit provided by the embodiment of the present application is described in detail above, and the trigger circuit in the signal generating circuit receives the target clock signal and generates the first command signal corresponding to the initial command signal in response to the received initial command signal. The selection circuit receives the encoded signals of the mode register, generates a first selection signal and a second selection signal, and the encoded signals correspond to different burst length modes. The output circuit receives the first command signal and generates a target command signal in response to the received first and second selection signals, the effective level length of the target command signal corresponding to the burst length mode. Therefore, the signal generating circuit can generate target command signals with different effective level lengths for different burst length modes, and the target command signals with different effective level lengths control the ODT to be opened for different times, so that the opening time of the ODT is effectively controlled.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present application, and are not limiting. Although the application has been described in detail with reference to the foregoing embodiments, it will be appreciated by those skilled in the art that variations may be made to the embodiments described, or equivalents may be substituted for elements thereof in part or in whole. Such modifications and substitutions do not depart from the spirit of the application.
Claims (9)
1. A signal generation circuit, comprising:
A trigger circuit configured to receive a target clock signal and, in response to a received initial command signal, generate a first command signal corresponding to the initial command signal;
A selection circuit configured to receive an encoded signal of a mode register, the encoded signal corresponding to a different burst length mode, and to generate a first selection signal and a second selection signal;
an output circuit configured to receive the first command signal and generate a target command signal in response to the received first and second selection signals, the target command signal having an effective level length corresponding to a burst length mode;
The trigger circuit comprises N cascaded triggers;
The clock input end of the trigger of each stage receives the target clock signal, the trigger input end of the trigger of the first stage receives an initial command signal, the positive phase output end of the trigger of the previous stage is connected with the trigger input end of the trigger of the next stage, and the positive phase output end of the trigger of each stage outputs the first command signal;
The output circuit comprises a first output circuit, a second output circuit and a first control circuit, wherein the first output circuit is configured to receive the first command signal and a first sub-command signal, generate an intermediate command signal, the effective level length of the intermediate command signal is twice as long as that of the first command signal, and the first sub-command signal is obtained by delaying the first command signal by one period of a target clock signal;
The output circuit further includes a second output circuit configured to receive the intermediate command signal and generate a second command signal in response to the first selection signal and/or a second selection signal;
If the received first selection signal or the second selection signal is valid, the second command signal is an inverse signal of the intermediate command signal.
2. The signal generating circuit as recited in claim 1, wherein the output circuit further comprises a third output circuit configured to receive the second command signal and generate a target command signal.
3. The signal generating circuit according to claim 2, wherein the first output circuit includes a first nand gate, a second nand gate, a third nand gate, and a fourth nand gate;
The first input end of the first NAND gate is connected with the normal phase output end of the trigger of the first stage, the second input end of the first NAND gate is connected with the normal phase output end of the trigger of the second stage, and the output end of the first NAND gate outputs a first intermediate command signal;
the first input end of the second NAND gate is connected with the positive phase output end of the trigger of the third stage, the second input end of the second NAND gate is connected with the positive phase output end of the trigger of the fourth stage, and the output end of the second NAND gate outputs a second intermediate command signal;
the first input end of the third NAND gate is connected with the positive phase output end of the trigger of the fifth stage, the second input end of the third NAND gate is connected with the positive phase output end of the trigger of the sixth stage, and the output end of the third NAND gate outputs a third intermediate command signal;
The first input end of the fourth NAND gate is connected with the positive phase output end of the trigger of the seventh stage, the second input end of the fourth NAND gate is connected with the positive phase output end of the trigger of the eighth stage, and the output end of the fourth NAND gate outputs a fourth intermediate command signal.
4. The signal generating circuit according to claim 3, wherein the second output circuit includes a fifth nand gate, a sixth nand gate, a seventh nand gate, and an eighth nand gate;
the first input end and the second input end of the fifth NAND gate are connected with the output end of the first NAND gate, the output end of the fifth NAND gate outputs a fifth intermediate command signal, and the fifth intermediate command signal is an inverted signal of the first intermediate command signal;
The first input end of the sixth NAND gate is connected with the output end of the second NAND gate, the second input end of the sixth NAND gate receives a first selection signal, the output end of the sixth NAND gate outputs a sixth intermediate command signal, and if the first selection signal is valid, the sixth intermediate command signal is an inverted signal of the second intermediate command signal;
the first input end of the seventh NAND gate is connected with the output end of the third NAND gate, the second input end of the seventh NAND gate receives a second selection signal, the output end of the seventh NAND gate outputs a seventh intermediate command signal, and if the second selection signal is valid, the seventh intermediate command signal is an inverted signal of the third intermediate command signal;
the first input end of the eighth NAND gate is connected with the output end of the fourth NAND gate, the second input end of the eighth NAND gate receives a second selection signal, the output end of the eighth NAND gate outputs an eighth intermediate command signal, and if the second selection signal is valid, the eighth intermediate command signal is an inversion signal of the fourth intermediate command signal.
5. The signal generating circuit according to claim 4, wherein the third output circuit includes a ninth nand gate, a tenth nand gate, a first nor gate;
The first input end of the ninth NAND gate is connected with the output end of the fifth NAND gate, the second input end of the ninth NAND gate is connected with the output end of the sixth NAND gate, and the output end of the ninth NAND gate outputs a ninth intermediate command signal;
The first input end of the tenth NAND gate is connected with the output end of the seventh NAND gate, the second input end of the tenth NAND gate is connected with the output end of the eighth NAND gate, and the output end of the tenth NAND gate outputs a tenth intermediate command signal;
The first input end of the first NOR gate is connected with the output end of the ninth NAND gate, the second input end of the first NOR gate is connected with the output end of the tenth NAND gate, and the output end of the first NOR gate outputs the target command signal.
6. The signal generation circuit of claim 1, further comprising a gating circuit configured to receive an initial clock signal and, in response to a received first gating signal, generate a target clock signal corresponding to the first gating signal.
7. The signal generating circuit according to claim 6, wherein the gating circuit comprises an eleventh nand gate, a first input terminal of the eleventh nand gate receiving the initial clock signal, a second input terminal receiving the first gating signal, and triggering output of the target clock signal if the first gating signal is valid.
8. A signal generation circuit, comprising:
A trigger circuit configured to receive a target clock signal and, in response to a received initial command signal, generate a first command signal corresponding to the initial command signal;
A selection circuit configured to receive an encoded signal of a mode register, the encoded signal corresponding to a different burst length mode, and to generate a first selection signal and a second selection signal;
an output circuit configured to receive the first command signal and generate a target command signal in response to the received first and second selection signals, the target command signal having an effective level length corresponding to a burst length mode;
The trigger circuit comprises N cascaded triggers;
The clock input end of the trigger of each stage receives the target clock signal, the trigger input end of the trigger of the first stage receives an initial command signal, the positive phase output end of the trigger of the previous stage is connected with the trigger input end of the trigger of the next stage, and the positive phase output end of the trigger of each stage outputs the first command signal;
The output circuit comprises a first SR latch, a first selector and a second selector, wherein the S input end of the first SR latch is connected with the positive output end of the trigger of the first stage, the R input end of the first SR latch is connected with the positive output end of the trigger of the N stage, and the Q output end of the first SR latch outputs the target command signal;
The control end of the first selector receives a first selection signal, the first input end of the first selector is connected with the positive phase output end of the second-stage trigger, and the second input end of the first selector is connected with the positive phase output end of the N-1-th-stage trigger;
The control end of the second selector receives a second selection signal, the first input end of the second selector is connected with the positive phase output end of the trigger of the second stage, and the second input end of the second selector is connected with the positive phase output end of the trigger of the M-th stage, wherein M is 2< N-1.
9. A signal generation circuit, comprising:
A trigger circuit configured to receive a target clock signal and, in response to a received initial command signal, generate a first command signal corresponding to the initial command signal;
A selection circuit configured to receive an encoded signal of a mode register, the encoded signal corresponding to a different burst length mode, and to generate a first selection signal and a second selection signal;
an output circuit configured to receive the first command signal and generate a target command signal in response to the received first and second selection signals, the target command signal having an effective level length corresponding to a burst length mode;
the trigger circuit comprises a first trigger, wherein a clock input end of the first trigger receives a target clock signal, a trigger input end of the first trigger receives an initial command signal, and a non-inverting output end of the first trigger outputs the first command signal;
The output circuit comprises a second trigger, a third trigger and a fourth trigger;
the clock input end of the second trigger receives the first command signal, the trigger input end of the second trigger is connected with the negative phase output end, and the positive phase output end of the second trigger outputs a first sub-target command signal;
The clock input end of the third trigger is connected with the positive phase output end of the second trigger, the trigger input end of the third trigger is connected with the negative phase output end, the control end of the third trigger receives the first selection signal, and the positive phase output end of the third trigger outputs a second sub-target command signal;
The clock input end of the fourth trigger is connected with the positive phase output end of the third trigger, the trigger input end of the fourth trigger is connected with the negative phase output end, the control end of the fourth trigger receives the second selection signal, and the positive phase output end of the fourth trigger outputs a third sub-target command signal;
If the first selection signal is invalid, the second selection signal is invalid, and a first sub-target command signal is output as a target command signal;
If the first selection signal is valid, the second selection signal is invalid, and a second sub-target command signal is output as a target command signal;
and if the first selection signal is valid, the second selection signal is valid, and a third sub-target command signal is output as a target command signal.
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|---|---|---|---|---|
| JP3204384B2 (en) * | 1997-12-10 | 2001-09-04 | エヌイーシーマイクロシステム株式会社 | Semiconductor memory circuit |
| KR100336838B1 (en) * | 1999-06-17 | 2002-05-16 | 윤종용 | Dynamic random access memory device with refresh period selecting circuit and input/output bit width selecting circuit |
| KR20090032281A (en) * | 2007-09-27 | 2009-04-01 | 삼성전자주식회사 | Semiconductor memory device and data input / output method of semiconductor memory device |
| KR101046998B1 (en) * | 2009-05-28 | 2011-07-06 | 주식회사 하이닉스반도체 | Buffer control signal generation circuit and semiconductor memory device using same |
| KR101095007B1 (en) * | 2010-09-30 | 2011-12-20 | 주식회사 하이닉스반도체 | On die termination signal generation circuit, generation method and semiconductor device using same |
| KR101878902B1 (en) * | 2011-10-04 | 2018-07-17 | 에스케이하이닉스 주식회사 | Semiconductor memory device and method of driving the same |
| CN118072787A (en) * | 2022-11-11 | 2024-05-24 | 长鑫存储技术有限公司 | ODT control circuit and memory |
| CN116054788B (en) * | 2023-01-11 | 2025-01-17 | 长鑫存储技术有限公司 | Signal generating circuit |
-
2023
- 2023-01-11 CN CN202310065028.2A patent/CN116054788B/en active Active
- 2023-05-16 WO PCT/CN2023/094564 patent/WO2024148729A1/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112542188A (en) * | 2019-09-20 | 2021-03-23 | 爱思开海力士有限公司 | Signal generating circuit and semiconductor device using the same |
| CN113838496A (en) * | 2020-06-24 | 2021-12-24 | 爱思开海力士有限公司 | Semiconductor memory device including wait time setting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116054788A (en) | 2023-05-02 |
| WO2024148729A1 (en) | 2024-07-18 |
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