CN116054789A - High-speed comparator with multiple working modes - Google Patents

Abstract

The invention provides a high-speed comparator with multiple working modes, including a preamplifier circuit, which is used to amplify the first and second input signals, and output the first and second output signals; at least two working modes Working circuit, the input terminal of each working circuit is used to receive the first and second output signals, the output terminal of each working circuit is added to the non-inverting output terminal of the integrated operational amplifier to form a positive feedback path, and the output terminal of each working circuit is fed back to The first and second output signals; corresponding to the isolating switch of each working circuit, different isolating switches are set in each positive feedback path, when the working circuit of one working mode is working, the isolating switch in the positive feedback path is closed, and the other The isolating switch is opened, so that the rest of the positive feedback path in non-operating mode is isolated. The invention isolates the redundant positive feedback path of the unopened mode through the isolating switch, and can reduce the influence of the grid capacitance of the unopened mode related MOS transistor on the response time of the current working mode.

Description

High-speed comparator with multiple operating modes

technical field

The invention relates to the technical field of semiconductors, in particular to a high-speed comparator with multiple working modes.

Background technique

A comparator is an important part of a modern electronic system, a basic conversion unit between an analog signal and a digital signal, and can be used as a 1-bit analog-to-digital converter. Most of them work in an open-loop state, and usually use internal positive feedback to obtain greater gain or hysteresis effects.

Comparators are widely used in the conversion process of analog signals to digital signals, such as single-threshold comparators with fixed reference voltages in ADCs (analog-to-digital converters) and dual-threshold comparators with two comparison references in complex interference environments . Multiple working modes applicable to different scenarios can be integrated in the comparator, so that the comparator can be used in the above different environments, but this will greatly affect the response speed of the comparator, so the setting of the mode will limit the response speed of the comparator .

For example, Figure 1 shows the structure of a clamped push-pull output comparator, in which NM10-NM13 are NMOS transistors on the positive feedback path, and there are two working modes Mode1 and Mode2.

When working normally, only Mode1 or Mode2 works, and the other mode is redundant. This redundant mode will increase the gate capacitance on the first-stage output nodes A and B, reducing the response speed. In analog circuits, the size of the device is often larger, which brings about a larger gate capacitance. Therefore, designing multiple modes will seriously affect the response speed.

In order to solve the above problems, it is necessary to propose a new high-speed comparator with multiple working modes.

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a high-speed comparator with multiple operating modes, which is used to solve the problem of integrating multiple operating modes applicable to different scenarios in the comparator in the prior art, so that the comparator It is used in the above different environments, but this will greatly affect the response speed of the comparator, and the setting of the mode will limit the response speed of the comparator.

In order to achieve the above purpose and other related purposes, the present invention provides a high-speed comparator with multiple working modes, including:

A preamplifier circuit, the preamplifier circuit is used to amplify the first and second input signals, and output the first and second output signals;

Working circuits with at least two working modes, the input terminals of each of the working circuits are used to receive the first and second output signals, and the output terminals of each of the working circuits are added to the non-inverting output terminals of the integrated operational amplifier to form positive a feedback path, the output end of each of the working circuits is fed back to the first and second output signals;

Corresponding to the isolating switch of each kind of said working circuit, different said isolating switches are arranged on each of said positive feedback paths, when the said working circuit of one working mode works, the said positive feedback path of said The isolating switch is closed, and the rest of the isolating switches are opened, so that the rest of the positive feedback paths in the non-working mode are isolated.

Preferably, the preamplifier circuit is a differential amplifier circuit.

Preferably, the working circuit has a first working mode and a second working mode.

Preferably, the isolation switch includes NMOS, PMOS, transmission gate switch, and gate voltage bootstrap switch.

Preferably, the high-speed comparator is a P-type differential pair.

Preferably, the preamplifier circuit includes a first PMOS, a second PMOS, a third PMOS, a fourth NMOS and a fifth NMOS;

The working circuit in the first working mode includes a sixth NMOS, a tenth NMOS, a seventh NMOS, and an eleventh NMOS; the corresponding isolation switch includes a first switch and a second switch;

The working circuit in the second working mode includes an eighth NMOS, a twelfth NMOS, a ninth NMOS, and a thirteenth NMOS; the corresponding isolation switch includes a third switch and a fourth switch;

in,

The source of the first PMOS is connected to the power supply voltage, the gate of the first PMOS is connected to the bias voltage, the gate of the second PMOS is connected to the first input signal, the gate of the third PMOS is connected to the second input signal, and the gate of the first PMOS is connected to the second input signal. The drain of the second PMOS is respectively connected to the source of the third PMOS, the drain of the second PMOS is connected to the drain of the fourth NMOS, and the drain of the third PMOS is connected to the drain of the fifth NMOS;

The drain of the sixth NMOS is connected to the source of the tenth NMOS, the drain of the eighth NMOS is connected to the source of the twelfth NMOS, the drain of the ninth NMOS is connected to the source of the thirteenth NMOS, and the drain of the eighth NMOS is connected to the source of the thirteenth NMOS. The drain of the seventh NMOS is connected to the source of the eleventh NMOS;

The drain of the tenth NMOS and the drain of the twelfth NMOS are coupled between the drain of the third PMOS and the drain of the fifth NMOS;

The drain of the eleventh NMOS and the drain of the thirteenth NMOS are coupled between the drain of the second PMOS and the drain of the fourth NMOS;

The sources of the fourth NMOS, the sixth NMOS, the eighth NMOS, the ninth NMOS, the seventh NMOS, and the fifth NMOS are sequentially connected to the power ground;

A first switch is connected between the drain and gate of the fourth NMOS and the gate of the sixth NMOS, and a second switch is connected between the gate and drain of the fifth NMOS and the gate of the seventh NMOS;

A third switch is connected between the drain and gate of the fourth NMOS and the gate of the eighth NMOS, and a fourth switch is connected between the gate and drain of the fifth NMOS and the gate of the ninth NMOS.

Preferably, the high-speed comparator is an N-type differential pair.

Preferably, the preamplifier circuit includes a first NMOS, a second NMOS, a third NMOS, a fourth PMOS and a fifth PMOS;

The working circuit in the first working mode includes a sixth PMOS, a tenth PMOS, a seventh PMOS, and an eleventh PMOS; the corresponding isolation switch includes a first switch and a second switch;

The working circuit in the second working mode includes an eighth PMOS, a twelfth PMOS, a ninth PMOS, and a thirteenth PMOS; the corresponding isolation switch includes a third switch and a fourth switch;

in,

The source of the first NMOS is connected to the power ground, the gate of the first NMOS is connected to the bias voltage, the gate of the second NMOS is connected to the first input signal, the gate of the third NMOS is connected to the second input signal, and the gate of the first NMOS The drain of the second NMOS is respectively connected to the source of the third NMOS, the drain of the second NMOS is connected to the drain of the fourth PMOS, and the drain of the third NMOS is connected to the drain of the fifth PMOS;

The drain of the sixth PMOS is connected to the source of the tenth PMOS, the drain of the eighth PMOS is connected to the source of the twelfth PMOS, the drain of the ninth PMOS is connected to the source of the thirteenth PMOS, and the drain of the eighth PMOS is connected to the source of the thirteenth PMOS. The drain of the seventh PMOS is connected to the source of the eleventh PMOS;

The drain of the tenth PMOS and the drain of the twelfth PMOS are coupled between the drain of the third NMOS and the drain of the fifth PMOS;

The drain of the eleventh PMOS and the drain of the thirteenth PMOS are coupled between the drain of the second NMOS and the drain of the fourth PMOS;

The sources of the fourth PMOS, the sixth PMOS, the eighth PMOS, the ninth PMOS, the seventh PMOS, and the fifth PMOS are sequentially connected and connected to the power supply voltage;

A first switch is connected between the drain and gate of the fourth PMOS and the gate of the sixth PMOS, and a second switch is connected between the gate and drain of the fifth PMOS and the gate of the seventh PMOS;

A third switch is connected between the drain and gate of the fourth PMOS and the gate of the eighth PMOS, and a fourth switch is connected between the gate and drain of the fifth PMOS and the gate of the ninth PMOS.

As mentioned above, the high-speed comparator with multiple working modes of the present invention has the following beneficial effects:

The comparator of the present invention isolates the redundant positive feedback path of the unopened mode through the isolating switch, which can reduce the influence of the gate capacitance of the unopened mode related MOS transistor on the response time of the current working mode; when multiple modes are set, If the analog switch is not ideal for other mode isolation, it will increase the subtle mismatch and distortion of the analog signal, but it will not significantly reduce the response time, nor will it affect the hysteresis effect and comparator function; Under this circumstance, many working modes that meet different application scenarios are added, and it is easy for design workers to maintain later.

Description of drawings

FIG. 1 shows a schematic diagram of a clamp push-pull output comparator in the prior art;

Fig. 2 shows a schematic diagram of a high-speed comparator for a P-type differential pair of the present invention;

3 shows a schematic diagram of a high-speed comparator using a transmission gate as a P-type differential pair of an analog switch according to the present invention;

FIG. 4 shows a schematic diagram of a response time comparison table in different modes of a high-speed comparator using a transmission gate as an analog switch of the present invention;

Fig. 5 shows that the high-speed comparator using the transmission gate as an analog switch and the comparator without an isolation switch in the same mode show a schematic diagram of the first or second output signal response comparison curve;

Figure 6 shows an enlarged schematic diagram of the circle in Figure 5;

FIG. 7 is a schematic diagram of a high-speed comparator for an N-type differential pair of the present invention.

Explanation of reference signs:

First PMOS PM1

Second PMOS PM2

The third PMOS PM3

Fourth NMOS NM4

Fifth NMOS NM5

Sixth NMOS NM6

Seventh NMOS NM7

Eighth NMOS NM8

Ninth NMOS NM9

Tenth NMOS NM10

Eleventh NMOS NM11

Twelfth NMOS NM12

Thirteenth NMOS NM13

The first NMOS NM1

Second NMOS NM2

The third NMOS NM3

The fourth PMOS PM4

Fifth PMOS PM5

Sixth PMOS PM6

Seventh PMOS PM7

Eighth PMOS PM8

Ninth PMOS PM9

Tenth PMOS PM10

Eleventh PMOS PM11

Twelfth PMOS PM12

Thirteenth PMOS PM13

first switch S1

Second switch S2

The third switch S3

Fourth switch S4

The first input signal INN

The second input signal INP

Power supply voltage VDD

Power ground GND

Bias voltage VB

The first output signal VOUTP

Second output signal VOUTN

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

The invention provides a high-speed comparator with multiple working modes, including:

A preamplifier circuit, the preamplifier circuit is used to amplify the first and second input signals (INN, INP), and the preamplifier circuit outputs the first and second output signals (VOUTP, VOUTN);

In an embodiment of the present invention, the preamplifier circuit is a differential amplifier circuit.

Working circuits with at least two working modes, the input terminals of each of the working circuits are used to receive the first and second output signals (VOUTP, VOUTN), and the output terminals of each of the working circuits are added to the integrated operational amplifier The non-inverting output terminals form a positive feedback path, and the output terminals of each of the working circuits are fed back to the first and second output signals (VOUTP, VOUTN);

In an embodiment of the present invention, the working circuit includes at least a first working mode and a second working mode. For example, when the first working mode is selected and the second working mode is not selected, the first switch S1 and the second switch S2 are turned on, and the third switch S3 and the fourth switch S4 are turned off. Conversely, when the second working mode is selected and the first working mode is not selected, the third switch S3 and the fourth switch S4 are turned on, and the first switch S1 and the second switch S2 are turned off. It should be noted that the working circuit may also have more working modes.

Corresponding to the isolating switch of each working circuit, different isolating switches are set in each positive feedback path. When the working circuit of one working mode is working, the isolating switch in the positive feedback path is closed, and the remaining isolating switches are opened, so that The rest of the positive feedback path for non-operating mode is isolated.

In an embodiment of the present invention, the isolation switch includes NMOS, PMOS, transmission gate switch, and gate voltage bootstrap switch.

In the embodiment of the present invention, please refer to FIG. 2 , the high-speed comparator is a P-type differential pair.

In an embodiment of the present invention, the preamplifier circuit includes a first PMOS PM1, a second PMOS PM2, a third PMOS PM3, a fourth NMOS NM4 and a fifth NMOS NM5;

The working circuit of the first working mode includes a sixth NMOS NM6, a tenth NMOS NM10, a seventh NMOS NM7 and an eleventh NMOS NM11; the corresponding isolation switch includes a first switch S1 and a second switch S2;

The working circuit of the second working mode includes the eighth NMOS NM8, the twelfth NMOS NM12, the ninth NMOS NM9 and the thirteenth NMOS NM13; the corresponding isolation switches include the third switch S3 and the fourth switch S4;

in,

The source of the first PMOS PM1 is connected to the power supply voltage VDD, the gate of the first PMOS PM1 is connected to the bias voltage VB, the gate of the second PMOS PM2 is connected to the first input signal INN, and the gate of the third PMOS PM3 is connected to the second input Signal INP, the drain of the first PMOSPM1 is connected to the source of the second PMOS PM2 and the third PMOS PM3 respectively, the drain of the second PMOS PM2 is connected to the drain of the fourth NMOS NM4, and the drain of the third PMOS PM3 is connected to the drain of the third PMOS PM3 Fifth NMOS NM5 drain connection;

The drain of the sixth NMOS NM6 is connected to the source of the tenth NMOS NM10, the drain of the eighth NMOS NM8 is connected to the source of the twelfth NMOS NM12, the drain of the ninth NMOS NM9 is connected to the source of the thirteenth NMOS NM13 pole connection, the drain of the seventh NMOS NM7 is connected to the source of the eleventh NMOS NM11;

The drain of the tenth NMOS NM10 and the drain of the twelfth NMOS NM12 are coupled between the drain of the third PMOS PM3 and the drain of the fifth NMOS NM5;

The drain of the eleventh NMOS NM11 and the drain of the thirteenth NMOS NM13 are coupled between the drain of the second PMOS PM2 and the drain of the fourth NMOS NM4;

The sources of the fourth NMOS NM4, the sixth NMOS NM6, the eighth NMOS NM8, the ninth NMOS NM9, the seventh NMOS NM7, and the fifth NMOS NM5 are connected in sequence and connected to the power ground GND;

A first switch S1 is connected between the drain and gate of the fourth NMOS NM4 and the gate of the sixth NMOS NM6, and a second switch is connected between the gate and drain of the fifth NMOS NM5 and the gate of the seventh NMOS NM7 S2;

A third switch S3 is connected between the drain and gate of the fourth NMOS NM4 and the gate of the eighth NMOS NM8, and a fourth switch is connected between the gate and drain of the fifth NMOS NM5 and the gate of the ninth NMOS NM9 S4.

Referring to FIG. 3 , the transmission gates TG1 - TG4 are used as the analog switches S1 - S4 , and Mode1 and Mode1b and Mode2 and Mode2b are control signals with opposite levels. The TG isolation of the analog switch can effectively reduce the impact of other working mode gate capacitances on the response time of the current working mode. The comparison of the simulated response time in different modes is shown in Figure 4, where HYST stands for hysteresis. The larger the HYST, the larger the W/L of the MOS transistor, the larger the gate capacitance, and the greater the impact on the response of other modes. .

It can be seen from Figure 4 that NO means no hysteresis, and 25mV means that the hysteresis is 25mV; there are 5 working modes in the table. The speed of the single working mode is the fastest, and the response speed after the isolation of the transmission gate TG is slightly reduced, but the speed of the single working mode without the isolation of the analog switch TG will be greatly reduced.

Because the analog switch TG is not ideal, its resistance value will always be associated with the conduction channel when it is turned on, resulting in some losses. The greater the impedance and parasitic capacitance of the analog switch or the faster the comparator works, the greater the threshold loss, as shown in Figure 5 and Figure 6, where curve 101 is the first or second output in the same mode without using the analog switch TG Signal response curve, curve 201 is the response curve of the first or second output signal in the same mode using the analog switch TG. However, after simulation analysis, it is found that the isolation of the analog switch TG will not affect the hysteresis effect, which ensures the function of the comparator.

In an embodiment of the present invention, the high-speed comparators are N-type differential pairs.

In an embodiment of the present invention, the preamplifier circuit includes a first NMOS NM1, a second NMOS NM2, a third NMOS NM3, a fourth PMOS PM4 and a fifth PMOS PM5;

The working circuit of the first working mode includes a sixth PMOS PM6, a tenth PMOS PM10, a seventh PMOS PM7 and an eleventh PMOS PM11; the corresponding isolation switch includes a first switch S1 and a second switch S2;

The working circuit of the second working mode includes the eighth PMOS PM8, the twelfth PMOS PM12, the ninth PMOS PM9 and the thirteenth PMOS PM13; the corresponding isolation switch includes the third switch S3 and the fourth switch S4;

in,

The source of the first NMOS NM1 is connected to the power ground GND, the gate of the first NMOS NM1 is connected to the bias voltage VB, the gate of the second NMOS NM2 is connected to the first input signal INN, and the gate of the third NMOS NM3 is connected to the second input signal INP, the drain of the first NMOS NM1 is respectively connected to the source of the second NMOS NM2 and the third NMOS NM3, the drain of the second NMOS NM2 is connected to the drain of the fourth PMOS PM4, and the drain of the third NMOS NM3 is connected to the drain of the third NMOS NM3 Five PMOS PM5 drain connections;

The drain of the sixth PMOS PM6 is connected to the source of the tenth PMOS PM10, the drain of the eighth PMOS PM8 is connected to the source of the twelfth PMOS PM12, and the drain of the ninth PMOS PM9 is connected to the source of the thirteenth PMOS PM13 pole connection, the drain of the seventh PMOS PM7 is connected to the source of the eleventh PMOS PM11;

The drain of the tenth PMOS PM10 and the drain of the twelfth PMOS PM12 are coupled between the drain of the third NMOS NM3 and the drain of the fifth PMOS PM5;

The drain of the eleventh PMOS PM11 and the drain of the thirteenth PMOS PM13 are coupled between the drain of the second NMOS NM2 and the drain of the fourth PMOS PM4;

The sources of the fourth PMOS PM4, the sixth PMOS PM6, the eighth PMOS PM8, the ninth PMOS PM9, the seventh PMOS PM7, and the fifth PMOS PM5 are connected in sequence and connected to the power supply voltage VDD;

A first switch S1 is connected between the drain and gate of the fourth PMOS PM4 and the gate of the sixth PMOS PM6, and a second switch is connected between the gate and drain of the fifth PMOS PM5 and the gate of the seventh PMOS PM7 S2;

A third switch S3 is connected between the drain and gate of the fourth PMOS PM4 and the gate of the eighth PMOS PM8, and a fourth switch is connected between the gate and drain of the fifth PMOS PM5 and the gate of the ninth PMOS PM9 S4.

It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

In summary, the comparator of the present invention isolates the redundant positive feedback path of the unopened mode through the isolation switch, which can reduce the impact of the gate capacitance of the unopened mode-related MOS transistor on the response time of the current working mode; when set When there are multiple modes, if the analog switch isolated from other modes is not ideal, it will increase the subtle mismatch and the distortion of the analog signal, but it will not significantly reduce the response time, nor will it affect the hysteresis effect and comparator function; it can be increased With a very small amount of consumption, many working modes are added to meet different application scenarios, and it is easy for design workers to maintain later. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (8)

1. A high-speed comparator with multiple operating modes, characterized in that it at least includes: A preamplifier circuit, the preamplifier circuit is used to amplify the first and second input signals, and output the first and second output signals; Working circuits with at least two working modes, the input terminals of each of the working circuits are used to receive the first and second output signals, and the output terminals of each of the working circuits are added to the non-inverting output terminals of the integrated operational amplifier to form positive a feedback path, the output end of each of the working circuits is fed back to the first and second output signals; Corresponding to the isolating switch of each kind of said working circuit, different said isolating switches are arranged on each of said positive feedback paths, when the said working circuit of one working mode works, the said positive feedback path of said The isolating switch is closed, and the rest of the isolating switches are opened, so that the rest of the positive feedback paths in the non-working mode are isolated. 2. The high-speed comparator with multiple working modes according to claim 1, wherein the preamplifier circuit is a differential amplifier circuit. 3. The high-speed comparator with multiple working modes according to claim 1, wherein the working circuit at least includes a first working mode and a second working mode. 4 . The high-speed comparator with multiple working modes according to claim 1 , wherein the isolation switch includes NMOS, PMOS, transmission gate switch, and gate voltage bootstrap switch. 5. The high-speed comparator with multiple working modes according to claim 1, wherein the high-speed comparator is a P-type differential pair. 6. the high-speed comparator of multi-working mode according to claim 5, is characterized in that: The pre-amplification circuit includes a first PMOS, a second PMOS, a third PMOS, a fourth NMOS and a fifth NMOS; The working circuit in the first working mode includes a sixth NMOS, a tenth NMOS, a seventh NMOS, and an eleventh NMOS; the corresponding isolation switch includes a first switch and a second switch; The working circuit in the second working mode includes an eighth NMOS, a twelfth NMOS, a ninth NMOS, and a thirteenth NMOS; the corresponding isolation switch includes a third switch and a fourth switch; in, The source of the first PMOS is connected to the power supply voltage, the gate of the first PMOS is connected to the bias voltage, the gate of the second PMOS is connected to the first input signal, the gate of the third PMOS is connected to the second input signal, and the gate of the first PMOS is connected to the second input signal. The drain of the second PMOS is respectively connected to the source of the third PMOS, the drain of the second PMOS is connected to the drain of the fourth NMOS, and the drain of the third PMOS is connected to the drain of the fifth NMOS; The drain of the sixth NMOS is connected to the source of the tenth NMOS, the drain of the eighth NMOS is connected to the source of the twelfth NMOS, the drain of the ninth NMOS is connected to the source of the thirteenth NMOS, and the drain of the eighth NMOS is connected to the source of the thirteenth NMOS. The drain of the seventh NMOS is connected to the source of the eleventh NMOS; The drain of the tenth NMOS and the drain of the twelfth NMOS are coupled between the drain of the third PMOS and the drain of the fifth NMOS; The drain of the eleventh NMOS and the drain of the thirteenth NMOS are coupled between the drain of the second PMOS and the drain of the fourth NMOS; The sources of the fourth NMOS, the sixth NMOS, the eighth NMOS, the ninth NMOS, the seventh NMOS, and the fifth NMOS are sequentially connected to the power ground; A first switch is connected between the drain and gate of the fourth NMOS and the gate of the sixth NMOS, and a second switch is connected between the gate and drain of the fifth NMOS and the gate of the seventh NMOS; A third switch is connected between the drain and gate of the fourth NMOS and the gate of the eighth NMOS, and a fourth switch is connected between the gate and drain of the fifth NMOS and the gate of the ninth NMOS. 7. The high-speed comparator with multiple working modes according to claim 1, wherein the high-speed comparator is an N-type differential pair. 8. the high-speed comparator of multi-working mode according to claim 7, is characterized in that: The pre-amplification stage circuit includes a first NMOS, a second NMOS, a third NMOS, a fourth PMOS and a fifth PMOS; The working circuit in the first working mode includes a sixth PMOS, a tenth PMOS, a seventh PMOS, and an eleventh PMOS; the corresponding isolation switch includes a first switch and a second switch; The working circuit in the second working mode includes an eighth PMOS, a twelfth PMOS, a ninth PMOS, and a thirteenth PMOS; the corresponding isolation switch includes a third switch and a fourth switch; in, The source of the first NMOS is connected to the power ground, the gate of the first NMOS is connected to the bias voltage, the gate of the second NMOS is connected to the first input signal, the gate of the third NMOS is connected to the second input signal, and the gate of the first NMOS The drain of the second NMOS is respectively connected to the source of the third NMOS, the drain of the second NMOS is connected to the drain of the fourth PMOS, and the drain of the third NMOS is connected to the drain of the fifth PMOS; The drain of the sixth PMOS is connected to the source of the tenth PMOS, the drain of the eighth PMOS is connected to the source of the twelfth PMOS, the drain of the ninth PMOS is connected to the source of the thirteenth PMOS, and the drain of the eighth PMOS is connected to the source of the thirteenth PMOS. The drain of the seventh PMOS is connected to the source of the eleventh PMOS; The drain of the tenth PMOS and the drain of the twelfth PMOS are coupled between the drain of the third NMOS and the drain of the fifth PMOS; The drain of the eleventh PMOS and the drain of the thirteenth PMOS are coupled between the drain of the second NMOS and the drain of the fourth PMOS; The sources of the fourth PMOS, the sixth PMOS, the eighth PMOS, the ninth PMOS, the seventh PMOS, and the fifth PMOS are sequentially connected and connected to the power supply voltage; A first switch is connected between the drain and gate of the fourth PMOS and the gate of the sixth PMOS, and a second switch is connected between the gate and drain of the fifth PMOS and the gate of the seventh PMOS; A third switch is connected between the drain and gate of the fourth PMOS and the gate of the eighth PMOS, and a fourth switch is connected between the gate and drain of the fifth PMOS and the gate of the ninth PMOS.

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