CN116075154B

CN116075154B - Method for manufacturing semiconductor device and method for manufacturing memory

Info

Publication number: CN116075154B
Application number: CN202211099471.3A
Authority: CN
Inventors: 杨号号
Original assignee: Zhixun Innovation Technology Wuxi Co ltd; Jones Union Semiconductor Shanghai Co ltd
Current assignee: Zhixun Innovation Technology Wuxi Co ltd; Jones Union Semiconductor Shanghai Co ltd
Priority date: 2022-09-08
Filing date: 2022-09-08
Publication date: 2025-08-12
Anticipated expiration: 2042-09-08
Also published as: CN116075154A

Abstract

The present invention discloses a method for manufacturing a semiconductor device and a memory device. The method comprises: providing a semiconductor substrate; forming an insulating layer on the semiconductor substrate; forming multiple gate structures on the insulating layer; forming an etch barrier layer on the sidewalls of adjacent gate structures and on the exposed insulating layer; dry etching the insulating layer and the semiconductor substrate in the gaps between adjacent gate structures to form multiple trenches; wet etching the surface of the trenches to form an oxide layer on the sidewalls and bottom of the trenches; forming a shallow trench isolation structure extending downward into the semiconductor substrate; chemically mechanically polishing the gate dielectric layer on the gate structure and a portion of the hard mask layer in the gate structure to expose the gate structure; and etching back to remove a portion of the gate dielectric layer in the shallow trench isolation structure to expose a portion of the sidewalls of the gate structure. This method can improve the sidewall damage problem of the gate structure caused by existing two-dimensional memory manufacturing processes.

Description

Method for manufacturing semiconductor device and method for manufacturing memory

Technical Field

The present invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular, to a method for manufacturing a semiconductor device and a method for manufacturing a memory.

Background

Currently, memory fabrication techniques are an important component of semiconductor integrated circuit fabrication. As the device size of memory is continuously shrinking, the gate-to-gate size is becoming smaller. The substrate of a two-dimensional memory (2 DNAND) is generally divided into an edge (PERIPHERY) region and a device (cell) region, on which a plurality of gate structures are formed (also referred to as a cell region). It is found that in the process of dry etching the substrate at the gap between adjacent gate structures in the device region, on one hand, damage to the sidewalls of the stacked gate structures is caused to a certain extent, and even deterioration of electrical performance is seriously caused, and finally, yield and reliability are deteriorated. On the other hand, the tunnel oxide layer (tunnel oxide) is easily damaged by etching ions, thereby affecting the quality of the tunnel oxide layer and causing electrical and reliability failure.

For this reason, it is desirable to provide a new two-dimensional memory manufacturing method that can improve the above-mentioned problems.

Disclosure of Invention

The embodiment of the invention provides a manufacturing method of a semiconductor device and a manufacturing method of a memory, which are used for solving the problem of side wall damage of a grid structure caused by the existing two-dimensional memory manufacturing process.

In a first aspect, the invention provides a method for manufacturing a semiconductor device, which comprises the steps of providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, forming a plurality of gate structures on the insulating layer, forming an etching barrier layer on the side walls of adjacent gate structures and the exposed insulating layer, carrying out dry etching on the insulating layer and the semiconductor substrate at gaps between the adjacent gate structures to form a plurality of grooves, carrying out wet etching on the surfaces of the grooves to enable the bottom feature size of the gate structures to be larger than or equal to the top feature size of an active region, forming an oxide layer on the side walls and the bottom of the grooves, forming a gate dielectric layer on the etching barrier layer and the oxide layer, covering the gaps between the adjacent gate structures to form a shallow trench isolation structure extending downwards into the semiconductor substrate, carrying out chemical mechanical polishing on the gate dielectric layer on the gate structures and part of a hard mask layer in the gate structures to expose the gate structures, and etching back part of the gate dielectric layer in the shallow trench isolation structures to expose part of the gate dielectric layer.

The manufacturing method of the semiconductor device has the advantages that the side wall of the grid structure can be protected by adding the etching barrier layer, particularly the bottom damage of the side wall of the grid structure caused by dry etching is avoided, in addition, the ion damage of the insulating layer caused by dry etching can be repaired by wet etching, the bottom characteristic size of the grid structure of the structure is larger than or equal to the top characteristic size of the active region, and the channel electronic control is facilitated.

Optionally, after exposing a portion of the sidewall of the gate structure, the method further comprises wet cleaning the portion of the sidewall that leaks out to further repair ion damage to the sidewall of the gate structure caused by etching back.

Optionally, forming a plurality of gate structures on the insulating layer comprises sequentially forming a floating gate structure layer and a hard mask layer on the insulating layer, and etching the floating gate structure layer and the hard mask layer to form a plurality of gate structures.

Optionally, the thickness of the etching barrier layer is 1nm to 10nm, and the sidewall of the gate structure is protected by using the high selectivity ratio of the oxide layer.

Optionally, the etching barrier layer and the oxide layer are pad oxide layers, and the pad oxide layers can repair damage caused by dry etching, and can protect a gate structure and avoid damage to a side wall caused by subsequent dry etching.

Optionally, the liner oxide layer is silicon oxide or silicon nitride, or silicon oxynitride.

Optionally, the method further comprises ion implantation of the semiconductor substrate to form an active region and a drain region in the substrate on both sides of the gate structure.

Optionally, the material of the gate dielectric layer is a low dielectric constant material, such as organic spin-on glass.

Optionally, the insulating layer is a tunneling oxide layer, and an end portion of the tunneling oxide layer protrudes and extends into the shallow trench isolation structure.

Optionally, after performing the second wet etching on the sidewalls of the plurality of gate structures and the sidewalls of the trench, a feature size of the channel is less than or equal to a bottom feature size of the gate structure.

Optionally, after performing the second wet etching on the sidewalls of the plurality of gate structures and the sidewalls of the trench, an end portion of the insulating layer under the gate structures is exposed.

In a second aspect, the present invention also provides a method for manufacturing a memory, the method comprising any of the possible implementation methods of the first aspect. Specific advantages may be seen from the description of the first aspect above.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to the prior art;

Fig. 2A to fig. 2I are schematic diagrams illustrating various stages of manufacturing process of a semiconductor device according to an embodiment of the present invention.

Description of element numbers:

100. semiconductor substrate

200. Insulating layer

300. Gate structure 301 floating gate structure layer 302 hard mask layer

400. Etching barrier layer

500. Groove(s)

600. Oxide layer

700. Gate dielectric layer

Detailed Description

In order to make the contents of the present invention more clear and understandable, the contents of the present invention will be further described with reference to the accompanying drawings. Of course, the invention is not limited to this particular embodiment, and common alternatives known to those skilled in the art are also encompassed within the scope of the invention.

In the following detailed description of the embodiments of the present invention, the structures of the present invention are not drawn to a general scale, and the structures in the drawings are partially enlarged, deformed, and simplified, so that the present invention should not be construed as being limited thereto.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention.

It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

A schematic flow diagram of a manufacturing method of a semiconductor device is shown in connection with fig. 1, and fig. 2A to 2H show schematic results of stages of the manufacturing process in this example.

Referring to fig. 1, a process for manufacturing a memory of a semiconductor device according to an embodiment of the present invention includes the steps of:

S101, a semiconductor substrate 100 is provided.

As shown in (a) of fig. 2A, the semiconductor substrate 100 may be an N-type or P-type silicon substrate. The material of the semiconductor substrate 100 includes one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium, and the semiconductor substrate 100 may be a silicon semiconductor substrate on an insulator or a germanium semiconductor substrate on an insulator. The semiconductor substrate 100 may include various doped regions depending on the design requirements of the memory or other semiconductor device. Isolation structures (e.g., shallow trench isolation (shallow trench isolation, STI)) may also be included in the semiconductor substrate 100 to isolate regions.

In this embodiment, the semiconductor substrate 100 may be a silicon substrate, and the semiconductor substrate 100 includes a device region (also referred to as a cell region) and a peripheral region (also referred to as an edge region).

S102, an insulating layer 200 is formed on the semiconductor substrate 100.

Specifically, referring to fig. 2A (b), an insulating layer 200, also referred to as tunnel Oxide (OX), is deposited by physical vapor deposition (Physical Vapor Deposition, PVD) onto the front surface of the semiconductor substrate 100. The oxide of the insulating layer 200 may be at least one oxide of copper oxide, aluminum oxide, hafnium oxide, titanium oxide, and tantalum oxide having a low oxygen content.

S103, forming a plurality of gate structures 300 on the insulating layer.

Specifically, in one possible implementation, as shown in (a) of fig. 2B, a floating gate structure layer 301 and a hard mask layer 302 may be sequentially formed on the insulating layer, and then the floating gate structure layer 301 and the hard mask layer 302 may be patterned and etched to form a plurality of gate structures 300, as shown in (B) of fig. 2B.

And S104, forming an etching barrier layer 400 on the top, the side wall and the exposed insulating layer 200 of the adjacent gate structure 300.

Specifically, the etching barrier layer 400 may be a liner oxide layer (liner oxide), and the liner oxide layer is silicon oxide, silicon nitride or silicon oxynitride. Referring to fig. 2C, a pad oxide layer is grown before etching the semiconductor substrate 100, and the pad oxide layer can repair damage caused by dry etching, and protect the gate structure from damage to the sidewall caused by subsequent dry etching.

S105, dry etching is performed on the insulating layer 200 and the semiconductor substrate 100 at the gaps between the adjacent gate structures 300, to form a plurality of trenches 500.

Specifically, referring to fig. 2D, a plurality of trenches 500 are formed by dry etching the insulating layer 200 and the semiconductor substrate 100 in the window region with the gaps between adjacent gate structures 300 as windows by coating a photoresist.

And S106, carrying out wet etching on the surface of the groove 500 so that the bottom characteristic dimension of the gate structure is larger than or equal to the top characteristic dimension of the active region.

Optionally, referring to fig. 2E, a high temperature semiconductor substrate or diluted TMAH may be used for repair (pull back), where a single side of the repair (pull back) feature size (Critical Dimension, CD) is about 1nm to 3nm, and in addition, the bottom feature size of the gate structure is greater than or equal to the top feature size of the active region, which is beneficial for electronic control of the channel. The CD is the smallest dimension of the semiconductor device in the integrated circuit, and is an important dimension for measuring the design and manufacturing level of the integrated circuit, and this step can expose the end of the insulating layer under the gate structure, and can also effectively repair the damage caused by dry etching of the sidewalls of the gate structure 300 and the trench 500, prevent leakage caused by damage, or prevent electrical failure.

And S107, forming an oxide layer 600 on the side wall and the bottom of the groove 500.

Optionally, referring to fig. 2F, a liner oxide layer 600 is grown on the side wall and the bottom of the trench 500, where the liner oxide layer 600 can repair the damage caused by dry etching, and further protect the side wall of the trench from damage caused by subsequent shallow trench isolation structures.

And S108, forming a gate dielectric layer on the etching barrier layer 400 and the oxide layer 600, wherein the gate dielectric layer covers the gaps between the adjacent gate structures 300 to form shallow trench isolation structures extending downwards into the semiconductor substrate 100.

Optionally, as shown in fig. 2G, a gate dielectric layer 700 is formed on the oxide layer 600, where the material of the gate dielectric layer 700 is a low dielectric constant material, such as organic spin-on glass. The gate dielectric layer 700 extends from top to bottom into the semiconductor substrate 100, thereby forming a shallow trench isolation structure.

And S109, carrying out chemical mechanical polishing on the gate dielectric layer 700 on the gate structure 300 and part of the hard mask layer 302 in the gate structure 300 to expose the gate structure 300.

Optionally, referring to fig. 2H, a chemical mechanical polishing (CHEMICAL MECHANICAL polish, CMP) is performed on the gate dielectric layer 700 on the gate structure 300 and a portion of the hard mask layer 302 in the gate structure 300, thereby leaking out the gate structure 300.

And S110, etching back to remove part of the gate dielectric layer 700 in the shallow trench isolation structure so as to expose part of the side wall of the gate structure.

Optionally, referring to fig. 2I, a device region opening process (cellopen, COPEN) is used to etch back a portion of the gate dielectric layer 700 in the shallow trench isolation structure to expose a portion of the sidewall of the gate structure, where the bottom feature size b of the gate structure is greater than or equal to the top feature size a of the active region. In addition, the thickness of the etching barrier layer c is 1nm to 10nm.

Optionally, the method may further include performing ion implantation on the semiconductor substrate 100 to form an active region and a drain region in the substrate on both sides of the gate structure 300, and then forming a two-dimensional memory based on the method described above.

The foregoing description is only of the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the invention, so that all changes made in the equivalent structures of the present invention described in the specification and the drawings are included in the scope of the invention.

Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

forming an insulating layer on the semiconductor substrate;

forming a plurality of gate structures on the insulating layer;

forming an etch stop layer on the sidewalls of the adjacent gate structure and the exposed insulating layer;

performing dry etching on the insulating layer and the semiconductor substrate at the gaps between adjacent gate structures to form a plurality of trenches;

Wet etching the surface of the trench so that the characteristic size of the bottom of the gate structure is greater than or equal to the characteristic size of the top of the active area;

forming an oxide layer on the sidewalls and bottom of the trench;

forming a gate dielectric layer on the etch stop layer and the oxide layer, wherein the gate dielectric layer covers the gaps between adjacent gate structures to form a shallow trench isolation structure extending downward into the semiconductor substrate;

performing chemical mechanical polishing on the gate dielectric layer on the gate structure and a portion of the hard mask layer in the gate structure to expose the gate structure;

Etching back to remove a portion of the gate dielectric layer in the shallow trench isolation structure to expose a portion of the sidewall of the gate structure;

The leaked portion of the sidewall is wet cleaned.

2. The method according to claim 1, wherein forming a plurality of gate structures on the insulating layer comprises:

forming a floating gate structure layer and a hard mask layer in sequence on the insulating layer;

The floating gate structure layer and the hard mask layer are etched to form a plurality of gate structures.

3. The method according to claim 2, further comprising:

The thickness of the etch stop layer ranges from 1 nm to 10 nm.

The method according to claim 3 , wherein the etch stop layer and the oxide layer are pad oxide layers.

5 . The method according to claim 4 , wherein the pad oxide layer is silicon oxide, silicon nitride or silicon oxynitride.

6. The method according to any one of claims 1 to 5, further comprising:

Ion implantation is performed on the semiconductor substrate to form an active region and a drain region in the substrate on both sides of the gate structure.

7 . The method according to claim 1 , wherein the gate dielectric layer is made of a material with a low dielectric constant.

8 . The method according to claim 1 , wherein the insulating layer is a tunneling oxide layer, and an end portion of the tunneling oxide layer protrudes and extends into the shallow trench isolation structure.

9. A method for manufacturing a memory, comprising the method for manufacturing a semiconductor device according to any one of claims 1 to 8.