CN116185928B - Embedded processor architecture - Google Patents
Embedded processor architectureInfo
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- CN116185928B CN116185928B CN202211612759.6A CN202211612759A CN116185928B CN 116185928 B CN116185928 B CN 116185928B CN 202211612759 A CN202211612759 A CN 202211612759A CN 116185928 B CN116185928 B CN 116185928B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
- G06F9/45529—Embedded in an application, e.g. JavaScript in a Web browser
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
本公开实施例中提供了一种嵌入式处理机体系结构，属于通讯架构的技术领域，在物理单箱体内镜像集成的第一DSP处理模块和第二DSP处理模块，以及高速容错总线应用层和高速容错总线协议层。第一DSP处理模块和第二DSP处理模块形成双通道，该双通道之间相互强独立、弱耦合，为节省空间资源，双通道需要集成在1台箱体内部，且双通道相互之间的工作互不影响，系统接口信号相互独立，即使1个通道的系统连接器断开或不连接也不会影响到另一个通道的正常运行，从外至内最大可能的消除单点故障源。
In the disclosed embodiments, an embedded processor architecture is provided, belonging to the technical field of communication architectures. The architecture includes a first DSP processing module and a second DSP processing module, as well as a high-speed, fault-tolerant bus application layer and a high-speed, fault-tolerant bus protocol layer, mirrored and integrated within a single physical enclosure. The first and second DSP processing modules form a dual channel, which is strongly independent and weakly coupled. To conserve space, the dual channels are integrated within a single enclosure, and their operation does not affect each other. System interface signals are independent, so even if the system connector of one channel is disconnected or unconnected, the normal operation of the other channel will not be affected, thus eliminating single points of failure from the outside in to the greatest extent possible.
Description
Technical Field
The invention belongs to the technical field of aviation onboard computer architectures, and particularly relates to an embedded processor architecture.
Background
The machine-mounted fault-tolerant computer system with a double-channel architecture generally adopts a reliability working model of parallel or serial working between the two channels, wherein 'parallel connection' refers to a backup relation between the two channels, namely, one channel is used for continuously maintaining working by the other channel after failure so as to improve the reliable working characteristic of the whole computer system, and 'serial connection' refers to a monitoring operation relation between the two channels, namely, one channel in the computer is used as a main control channel and the other channel in the computer is used for monitoring, and when any one of the two channels fails or finds out the failure, the external control output of the whole computer is cut off so as to ensure the safe working characteristic of the whole computer system. A set of architecture framework belonging to an airborne computer system of an aviation is designed and used for data interaction among systems.
Disclosure of Invention
In view of this, the architecture of an embedded processor provided in the embodiments of the present disclosure is a new structural design, in which the interior of a single box is composed of two channels, the two channels are mutually strongly independent and weakly coupled, and the single point fault source is eliminated to the greatest extent, and meanwhile, the architecture supports the realization of data communication with a communication system network through a shared high-speed fault-tolerant bus.
An embedded processor architecture, a first DSP processing module and a second DSP processing module that are mirror integrated within a physical single enclosure, and a high-speed fault-tolerant bus application layer and a high-speed fault-tolerant bus protocol layer, wherein:
the first DSP processing module and the second DSP processing module respectively receive a plurality of external system parameters, and process and feed back the external system parameters;
the high-speed fault-tolerant bus application layer is used for acquiring data transmitted by the first DSP processing module and the second DSP processing module, packaging and converting data of a data bus protocol and then transmitting the data to the high-speed fault-tolerant bus protocol layer;
the high-speed fault-tolerant bus protocol layer is used for processing the protocol of the link layer and outputting the external data in a dual-redundancy mode.
The inside of the single box body is composed of two channels, the two channels are mutually independent and weakly coupled, the single point fault source is eliminated to the greatest extent, and meanwhile, the data communication with the communication system network is realized through the shared high-speed fault-tolerant bus. Different from the common serial or parallel dual-redundancy computer architecture, the two channels are mutually strong and independent and weakly coupled, so that the two channels are required to be integrated in the 1 box body to save space resources, the two channels work independently, the system interface signals are mutually independent (even if the system connector of the 1 channel is disconnected or not connected, the normal operation of the other channel is not influenced), the single-point fault source is eliminated from outside to inside to the greatest extent, and simultaneously, the two channels in the computer can realize data communication with a communication system network by sharing the same high-speed fault-tolerant bus.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
FIG. 1 is a frame diagram of the present invention;
FIG. 2 is a schematic diagram of the A data channel.
Detailed Description
Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. It will be apparent that the described embodiments are merely some, but not all embodiments of the present disclosure. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
As shown in fig. 1, the architecture of the embedded processor of the present invention includes a first DSP processing module (a data channel in the corresponding diagram) and a second DSP processing module (B data channel in the corresponding diagram) that are mirror-integrated in a physical single box, and a high-speed fault-tolerant bus application layer and a high-speed fault-tolerant bus protocol layer, where:
The first DSP processing module and the second DSP processing module respectively receive a plurality of external system parameters and process and feed back the external system parameters;
the high-speed fault-tolerant bus application layer is used for acquiring data transmitted by the first DSP processing module and the second DSP processing module, packaging and converting data of a data bus protocol and then transmitting the data to the high-speed fault-tolerant bus protocol layer;
The high-speed fault-tolerant bus protocol layer is used for processing the protocol of the link layer and outputting the external data in a dual-redundancy mode.
As a specific implementation mode provided by the scheme, the first DSP processing module and the second DSP processing module are respectively provided with power supplies (+5V power supplies on the left side and the right side in the corresponding diagram), the power supplies are all provided with overcurrent protection circuits, the power supplies of the second DSP processing module serve as hot backups of the power supplies of the first DSP processing module, after an external system is powered on, the power supplies of the first DSP processing module supply power for the high-speed fault-tolerant bus application layer preferentially through the set selection switch, the power supplies of the second DSP processing module supply power for the high-speed fault-tolerant bus protocol layer through the selection switch, when the power supplies of the first DSP processing module fail in power supply, the selection switch is controlled to switch, and the power supplies power for the high-speed fault-tolerant bus application layer and the high-speed fault-tolerant bus protocol layer through the power supplies of the second DSP processing module, so that normal power supply is maintained.
It should be noted that the +5V power supply is used as a special power supply to only power the high-speed fault-tolerant bus application layer and/or the high-speed fault-tolerant bus protocol layer, and a +15V power supply and a-15V power supply are correspondingly arranged at the left side and the right side in the figure, and the +15V power supply and the-15V power supply are freely selected as power supply by other modules of the first DSP processing module and the second DSP processing module according to own models, so that the specific form is not limited. And after the externally input voltage is subjected to filtering treatment, connecting the power modules with different models.
As a specific implementation mode provided by the scheme, the first DSP processing module and the second DSP processing module are respectively provided with an inter-channel interaction module, and data interaction is carried out between the two inter-channel interaction modules, so that at least state mutual display, data synchronization and data mutual transmission are carried out.
As shown in fig. 2, the first DSP processing module includes a first DSP processor, a control system high-speed bus protocol node, a comprehensive monitoring module, a first data exchange pool, a parallel expansion bus, and a plurality of data interaction modules, where:
the first DSP processor is in data interaction with the comprehensive monitoring module, the first data exchange pool and the plurality of data interaction modules through the parallel expansion bus and is used for data reading, processing and instruction sending;
The first data exchange pool transmits the processing information of the first DSP processor through the parallel expansion bus, and interacts with the high-speed fault-tolerant bus application layer data through the high-speed internal bus, namely, the data received by the first DSP processor and the corresponding processing result are fed back to the first data exchange pool, and then the first data exchange pool transmits the processing information to the high-speed fault-tolerant bus application layer and finally outputs the processing information to the external equipment;
the comprehensive monitoring module is used for monitoring the working state of the configured auxiliary module;
The control system high-speed bus protocol node is connected with a control system high-speed bus of external equipment, and is connected with a parallel expansion bus through a high-speed internal bus to perform protocol conversion of a data interaction mode (the protocol conversion is performed through 'high-speed internal bus conversion' to data which can be identified by the control system high-speed bus protocol node);
the plurality of data interaction modules receive and transmit signals or data by configuring different signal lines.
It should be noted that the structure and the data interaction mode of the second DSP processor are set in a mirror symmetry mode with those of the first DSP processor, only the first DSP processor is described, and the structure of the second DSP processor is not described again.
As the specific implementation mode provided by the scheme, the integrated digital signal processing system further comprises a gating switch, an isolation driver and a D/A converter, wherein the integrated monitoring module and a plurality of power modules are included in the first DSP processing module, the integrated monitoring module comprises a watchdog circuit monitoring module, a channel I D module and an LRU_ I D module, and each power module corresponds to one data interaction module, wherein:
The comprehensive monitoring module monitors working states of the watchdog circuit, the channel I D module, the LRU_ I D and the power supply modules in real time, the LRU_ I D module is used for identifying states of input signals of the LRU_ I D, the comprehensive monitoring module is connected with the gating switch, when the watchdog circuit, the channel I D module or the power supply modules are abnormal, the first DSP processor sends signals and is provided with a D/A converter for conversion, the signals are input into the isolation drive, the comprehensive monitoring module controls the gating switch to output analog quantity so as to monitor whether monitoring information is sent or not, and action results of the gating switch are fed back.
As the specific implementation manner provided by the scheme, the data interaction modules comprise a discrete quantity input/output module, an HB6096 input/output module and an RS422S input/output module, and are communicated with the first DSP processor, wherein:
The discrete quantity input/output module comprises an isolation conversion module, a driving output module and a first internal bus isolator, wherein the isolation conversion module and the driving output module are respectively connected with the first internal bus isolator, the discrete quantity is input into the isolation conversion processing and then is isolated, when the first DSP processor accesses, the first internal bus isolator is opened, when the first internal bus isolator is opened, the isolation conversion module is also opened, and data of the isolation conversion module can enter the first DSP processor through a parallel expansion bus;
when the discrete quantity is output, the discrete quantity is firstly input to a first internal bus isolator, and when the discrete quantity is input to a driving output, the driving output outputs the discrete quantity, namely, when a first DSP processor transmits a processing result, the first internal bus isolator is opened, and the processing result is input to a driving output module and then output;
The RS422S input/output module comprises a second internal bus isolator, a first data buffer module, a serial conversion module and a first terminal, wherein the serial conversion module is used for converting serial and parallel data (serial to parallel when input, parallel to serial when output) and the first data buffer module is used for converting input or output data;
The HB6096 input/output module comprises a third internal bus isolator, a second data buffer module, a string protocol conversion module (string data format conversion of input and output data) and a second terminal for matching, and the HB6096 bus corresponds to data, and the third internal bus isolator protects the parallel expansion bus when the data is input or output.
As a specific embodiment provided in the present application, further, an ac reference power module is further provided, processes the filtered voltage, and outputs ac reference data. The device also comprises a displacement monitoring and converting module, a proportion adjusting module and an A/D converter, wherein the displacement monitoring and converting module and the proportion adjusting module are respectively connected with the A/D converter,
The displacement monitoring and converting module receives an external alternating current reference (alternating current voltage is converted into direct current voltage), is connected and converted by the A/D converter (converted into analog quantity signals) and then is transmitted to the parallel expansion bus, is processed by the first DSP, and is transmitted to the first data exchange pool;
the proportion adjustment module receives an analog input signal transmitted by external equipment, adjusts the analog input signal according to a preset proportion, and inputs the analog input signal to the A/D converter for conversion and then to the parallel expansion bus.
As a specific implementation mode provided by the scheme, the external input voltage is 28V, and power is supplied to each power supply module after path filtering.
1. The physical single box body is internally integrated with a functionally symmetrical A, B channel;
2. the two channels are designed with strong independence and extremely weak coupling characteristics;
3. The double channels eliminate single-point fault sources from outside to inside;
4. The core DSP processing function circuit adopts unequal design for different communication buses;
5. the dual channel support enables data communication with the communication system network through a common high speed fault tolerant bus.
The interior of the single box body is composed of two channels, the two channels are mutually independent and weakly coupled, the single point fault source is eliminated to the greatest extent, and meanwhile, the data communication with a communication system network through a shared high-speed fault-tolerant bus is supported, and the details are as follows.
1. The physical single installation shell integrates 2 functional channels with symmetrical functions, namely an A channel and a B channel, in the single physical shell, and the functional channels are shown in the attached drawing;
the channels A and B are independently designed from outside to inside, input and output system signals and power supplies are independent, independent connectors are adopted to provide physical signal connection channels, the A, B channels are completely physically isolated from a physical signal layer, signals of each channel are divided into 3 types, each channel adopts 3 different connectors to provide physical access, and +28V power supply signals adopt independent power supply connectors; system signals (including output AC reference, displacement sensor input, analog input, RS422 output, HB6096 input, HB6096 output, discrete quantity input, discrete quantity output, analog output, LRU_ID) connector, control system high-speed bus connector;
The internal functions of the A and B channels are identical and independent, and the system electric signal of each channel is crosslinked with the internal related functional circuit after passing through the lightning protection layer function, and the method is as follows:
The power supply of the +28V power supply is respectively connected with an alternating current reference source (with an overcurrent and overvoltage protection function), +15V (with an overcurrent and overvoltage protection function), 15V (with an overcurrent and overvoltage protection function), +5V (with an overcurrent and overvoltage protection function) and other secondary power supply generating circuits after being filtered;
b. the input signal of the displacement sensor is connected with a displacement monitoring and converting functional circuit after passing through a lightning protection layer, converted into a direct current signal and then output and connected with an A/D converting functional circuit;
c. The analog input signal is connected with a 'proportion adjustment' circuit after passing through a 'lightning protection layer', and the 'proportion adjustment' circuit outputs and connects the processed direct-current analog signal to an 'A/D conversion' circuit;
d, the input signal of the RS422 is converted into a parallel signal through a serial conversion function after passing through a lightning protection layer through a terminal matching 1, and then is output to a data buffer 1 function;
e. the RS422 signal to be sent is output by the data buffer 1 function, is converted into a serial signal by the serial conversion function, and is output by the terminal matching 1 through the lightning protection layer;
f, converting an HB6096 input signal into a parallel signal through a lightning protection layer through a terminal matching function 2 and then outputting the parallel signal to a data buffering function 2;
g. The HB6096 output signal to be transmitted is output by the function of 'data buffer 2', converted into a serial signal by the function of 'protocol conversion', and output is realized by the terminal matching 2 'through the lightning protection layer';
h. The discrete quantity input signals are output to an internal bus for isolation after being isolated and converted by a lightning protection layer;
i. the discrete output signals to be output are connected and driven by an internal bus to be output through a lightning protection layer so as to realize output;
The D/A conversion converts the parallel digital quantity into a direct current analog quantity signal, and then the direct current analog quantity signal is connected with a gating switch through an isolation drive, and the analog quantity output is realized by the signal after the gating switch through a lightning protection layer;
k. The processor inputs the complete machine number information LRU_ID signal in the control system to a LRU_ID monitoring part in the comprehensive monitoring function through a lightning protection layer, so that the effectiveness of the LRU_ID signal is identified;
the result signal of the "integrated monitor" function (covering the monitoring of lru_id, watchdog, power supply, channel ID) is connected to a "gating switch" for realizing the control of analog output.
The core DSP processing function realizes data interaction and control through the parallel expansion bus of the processor and the functions of A/D conversion, internal bus isolation, D/A conversion, comprehensive monitoring, data exchange pool, high-speed internal bus conversion, inter-channel interaction and the like;
5. The loose coupling connection among channels, the inter-channel interaction function in A, B channels is connected through bidirectional data interaction, synchronization and state mutual indication, so that the transmission of data information and states among the two channels is realized, but the hard logic monitoring is not participated;
6. The core DSP processing functional circuit adopts an unequal design for different communication buses, and is communicated with a control system high-speed bus to be used as a main control equipment end design, and is communicated with a high-speed fault-tolerant bus to be used as a slave equipment end design.
The function of converting the high-speed internal bus into the high-speed internal bus is connected with a protocol node of a high-speed bus of a control system, the function of converting the high-speed internal bus into the high-speed internal bus is a master control end of the high-speed internal bus communication, and the protocol node of the high-speed internal bus of the control system is a slave node end of the high-speed internal bus communication;
The functions of the main processing function of the high-speed fault-tolerant bus application layer are used as a data exchange pool of a main control node and an A channel of a 3-group high-speed internal bus communication bus, a data exchange pool of a B channel and a high-speed fault-tolerant bus protocol layer of the high-speed fault-tolerant bus, and data interconnection is carried out through the high-speed internal bus, so that A, B channels and the like are communicated with the avionics network equipment through the high-speed fault-tolerant bus;
9. the A port and the B port of the dual-redundancy communication bus of the high-speed fault-tolerant bus are respectively connected with the outside by adopting independent connectors to realize physical butt joint, so as to support external non-same-direction wiring;
The +5V secondary power supplies in the A and B channels are connected with a switch, and the switch function ensures that +5V power supply can be provided for the main processing function of the high-speed fault-tolerant bus application layer and the high-speed fault-tolerant bus protocol layer when any +5V secondary power supply in the A, B channels is normal.
It can be seen that the 2 channels are operated in a coupling relationship, i.e. the state of 1 channel affects the operation mode of the other channel, and 1 is divided into two to be distributed to 2 channels on the external system signal distribution, obviously the 2 channels are not completely independent. In the airborne control system, a completely independent two-channel computer system is needed, two channels are needed to be integrated in 1 box body to save space resources, the two channels work mutually independently, system interface signals are mutually independent (even if a system connector of 1 channel is disconnected or not connected, normal operation of another channel is not influenced), and meanwhile, the two channels in the computer can realize data communication with an airborne avionics system network through the same high-speed fault-tolerant bus, so that a new mutually independent extremely weakly coupled two-channel computer system structure is needed to be designed to meet the use requirement of the airborne system.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the disclosure are intended to be covered by the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (6)
1. An embedded processor architecture characterized by a first DSP processing module and a second DSP processing module mirror integrated within a physical single enclosure, and a high speed fault tolerant bus application layer and a high speed fault tolerant bus protocol layer, wherein:
the first DSP processing module and the second DSP processing module respectively receive a plurality of external system parameters, and process and feed back the external system parameters;
the high-speed fault-tolerant bus application layer is used for acquiring data transmitted by the first DSP processing module and the second DSP processing module, packaging and converting data of a data bus protocol and then transmitting the data to the high-speed fault-tolerant bus protocol layer;
The high-speed fault-tolerant bus protocol layer is used for processing the protocol of the link layer and outputting the external data in a dual-redundancy mode;
The first DSP processing module and the second DSP processing module are respectively provided with an inter-channel interaction module, data interaction is carried out between the two inter-channel interaction modules, at least state interaction, data synchronization and data interaction are carried out, the first DSP processing module comprises a first DSP processor, a control system high-speed bus protocol node, an integrated monitoring module, a first data exchange pool, a parallel expansion bus, a plurality of data interaction modules and a watchdog circuit, the first DSP processor is in data interaction with the integrated monitoring module, the first data exchange pool and the plurality of data interaction modules through the parallel expansion bus and is used for data reading, processing and instruction sending, the first data exchange pool is used for transmitting processing information of the first DSP processor through the parallel expansion bus and is in data interaction with the high-speed fault-tolerant bus application layer through the high-speed internal bus, the integrated monitoring module is used for monitoring the working state of the configured auxiliary module, the control system high-speed bus protocol node is connected with the control system of external equipment at high speed and is connected with the parallel expansion bus through the parallel expansion bus, the data exchange pool is in data interaction with the parallel expansion bus, and the data exchange is carried out through the parallel expansion bus, and the data exchange protocol exchange mode is different in data protocol or multiple data protocol conversion modes and the data exchange mode is received.
2. The architecture of claim 1, wherein the first DSP processing module and the second DSP processing module are respectively provided with a power supply, the power supplies are all provided with an overcurrent protection circuit, the power supply of the second DSP processing module is used as a hot backup of the power supply of the first DSP processing module, after the external system is powered on, the power supply of the first DSP processing module preferentially supplies power to the high-speed fault-tolerant bus application layer through a set selection switch, the power supply of the second DSP processing module supplies power to the high-speed fault-tolerant bus protocol layer through the selection switch, when the power supply of the first DSP processing module fails in power supply, the selection switch is controlled to switch, and the power supply of the second DSP processing module supplies power to the high-speed fault-tolerant bus application layer and the high-speed fault-tolerant bus protocol layer to maintain normal power supply.
3. The embedded processor architecture of claim 2, wherein the first DSP processing module further comprises a gating switch, an isolation driving module, and a D/a converter, and a plurality of power modules, the integrated monitoring module comprising a watchdog circuit monitoring module, a channel ID module, an lru_id, one power module corresponding to each data interaction module, the gating switch being respectively connected to the isolation driving module and the integrated monitoring module, wherein:
The comprehensive monitoring module monitors working states of the watchdog circuit, the channel ID module, the LRU_ID and the power supply modules in real time, signals the first DSP processor when the watchdog circuit, the channel ID module or the power supply modules are abnormal, the first DSP processor performs data processing, a processing result is converted by the D/A converter and then is input to the isolation drive, and the comprehensive monitoring module controls the gating switch to perform analog output so as to monitor whether monitoring information is sent or not.
4. The embedded processor architecture of claim 3, wherein the plurality of data interaction modules comprises a discrete amount input output module, an HB6096 input output module, and an RS422S input output module, and are each in communication with the first DSP processor, wherein:
The discrete quantity input/output module comprises an isolation conversion module, a driving output module and a first internal bus isolator, wherein the isolation conversion module and the driving output module are respectively connected with the first internal bus isolator, and the discrete quantity is input to the first internal bus isolator after the isolation conversion processing and then is input to the first internal bus isolator;
The RS422S input/output module comprises a second internal bus isolator, a first data buffer module, a serial conversion module and a first terminal match, wherein the serial conversion module is used for converting serial and parallel data, and the first data buffer module is used for converting input or output data;
the HB6096 input/output module comprises a third internal bus isolator, a second data buffer module, a serial protocol conversion module and a second terminal, wherein the third internal bus isolator protects the parallel expansion bus when data corresponding to the HB6096 bus is input or output.
5. The embedded processor architecture of claim 4, further comprising a displacement monitoring and conversion module, a scaling module and an a/D converter, wherein the displacement monitoring and conversion module and the scaling module are respectively connected with the a/D converter, and the displacement monitoring and conversion module receives an internal ac quasi-voltage and converts the internal ac quasi-voltage into a dc voltage, and the dc voltage is converted by the a/D converter connection and then is transmitted to the parallel expansion bus;
The proportion adjustment module receives external analog input, adjusts according to a preset proportion, inputs the external analog input to the A/D converter for conversion, and inputs the external analog input to the parallel expansion bus.
6. The embedded processor architecture of claim 5, wherein the external input voltage is 28V and the power supply modules are powered after path filtering.
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| CN105718336A (en) * | 2014-11-30 | 2016-06-29 | 上海航空电器有限公司 | Dual-redundancy dispatching control system for aircraft alarm computer |
| CN111475451A (en) * | 2020-04-16 | 2020-07-31 | 中国电子科技集团公司第五十八研究所 | A 1553B communication bus message monitoring board |
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| WO2015049393A1 (en) * | 2013-10-01 | 2015-04-09 | Wynnertech, S.L. | Flexible digital controller for power converters |
| CN212086093U (en) * | 2020-06-12 | 2020-12-04 | 中车株洲电力机车研究所有限公司 | Transmission control system for multiple motors |
| CN113868077B (en) * | 2021-09-08 | 2024-04-16 | 中国航空工业集团公司西安航空计算技术研究所 | Double-double parallel architecture computer platform |
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| CN105718336A (en) * | 2014-11-30 | 2016-06-29 | 上海航空电器有限公司 | Dual-redundancy dispatching control system for aircraft alarm computer |
| CN111475451A (en) * | 2020-04-16 | 2020-07-31 | 中国电子科技集团公司第五十八研究所 | A 1553B communication bus message monitoring board |
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