CN116187269B - Parasitic capacitance parameter extraction method and device of multi-conductor system and storage medium - Google Patents

Abstract

The present invention discloses a parasitic capacitance parameter extraction method for a multi-conductor system, which is characterized by comprising: constructing a physical model of a two-dimensional geometric structure of an integrated circuit based on integrated circuit layout data, wherein the physical model of the two-dimensional geometric structure includes multiple conductors and multiple dielectrics; calculating a numerical simulation diagram of voltage and charge at any point in the physical model of the two-dimensional geometric structure; determining multiple dielectrics to be candidate for merging based on the numerical simulation diagram of voltage and charge; and judging whether the multiple dielectrics to be candidate for merging meet the following conditions: d_i>K*H(1) wherein d_i is the i-th dielectric in the physical model of the two-dimensional geometric structure. The thickness of the medium, H is the thickness of the conductor, K is the preset proportionality coefficient, max(h_i,h_(i+1))/min(h_i,h_(i+1))>8(2) wherein h_i is the distance from the conductor to the i-th medium, h_(i+1) is the distance from the conductor to the i+1-th medium, if it is determined that the medium i and the medium i+1 satisfy the above conditions (1) and (2), then the medium i and the medium i+1 are merged into one medium; and based on the merged medium, the parasitic capacitance parameters of each conductor in the physical model of the two-dimensional geometric structure of the integrated circuit are solved.

Description

A method, device and storage medium for extracting parasitic capacitance parameters of a multi-conductor system

Technical Field

The present invention belongs to the field of semiconductor integrated circuit automatic design, and more specifically, the present invention relates to a method for rapidly extracting parasitic capacitance parameters of a multi-conductor system by accelerating the capacitance solution speed.

Background technique

Integrated circuit chips are widely distributed with metal interconnects that are only nanometers wide and distributed in multiple layers. Their electromagnetic parasitic effects have become a key factor affecting circuit performance and even determining whether the circuit can work properly. Parasitic parameter extraction is the basis of modeling, analysis, and simulation in chip physical design. Only through parasitic parameter extraction can circuit delay be estimated, signal integrity and power integrity analysis be achieved, and various performance indicators of the entire circuit design can be verified.

In a typical integrated circuit design process, a process called "parasitic extraction" is set between layout design and circuit simulation. The main task of parasitic extraction is to calculate the equivalent resistance and capacitance parameters of interconnects and form a circuit netlist. With the development of process technology and the increase in circuit scale, how to accurately and quickly extract parasitic parameters (especially capacitance extraction) and further accurately simulate or analyze the reliability of circuits with parasitic parameters has become increasingly important for ensuring design quality, improving manufacturing yield, reducing costs and shortening design cycles.

As the industry places increasingly higher demands on the computational accuracy of parasitic parameter extraction, research on parasitic capacitance parameter extraction has evolved from two-dimensional, 2.5-dimensional to three-dimensional. Three-dimensional capacitance parameter extraction usually requires the establishment of a geometric structure model that reflects the three-dimensional interconnect structure, and then uses numerical methods to solve the electrostatic field equations, which is called a "three-dimensional field solver". The three-dimensional field solver has high computational accuracy, but the amount of calculation is relatively large.

The size of the parasitic capacitance parameters of a multi-conductor system directly affects the system's sensitivity to signals and the system's operating speed. Therefore, the extraction of the parasitic capacitance parameters of a multi-conductor system is of great significance. Currently, the mainstream method for extracting the parasitic capacitance parameters of a multi-conductor system is the 2.5-dimensional method. By reading the layout information of the integrated circuit, a two-dimensional physical model is designed, and then the parasitic capacitance parameters extracted from the two-dimensional model are stored in a table. Finally, the capacitance parameters in the table are taken out according to the layout, and the parasitic capacitance parameters of the entire integrated circuit layout are accumulated through the corresponding algorithm. In terms of effect, although splitting the layout into a two-dimensional model will result in a loss of accuracy, it is also within a reasonable range. In terms of performance, the 2.5-dimensional method is nearly 10 times faster than the three-dimensional method.

Summary of the invention

Technical problem to be solved by the invention

Whether the parasitic capacitance parameter extraction of a multi-conductor system uses a two-dimensional or 2.5-dimensional method, it is necessary to construct a two-dimensional geometric structure physical model based on the layout information of the integrated circuit, and then use a numerical method to solve the two-dimensional electrostatic field equation in the generated two-dimensional geometric structure physical model area. The physical model of the two-dimensional geometric structure generated by the existing technology based on the layout information of the integrated circuit is relatively complex, which is not conducive to numerical algorithm calculation.

The present invention is proposed in view of the above problems. The present invention proposes a method for extracting parasitic capacitance parameters of a multi-conductor system. In order to improve the extraction performance, this method performs equivalent dielectric merging on some dielectric graphics. The dielectric constant of the merged dielectric graphics can be recalculated according to the area ratio, thereby accelerating the extraction speed of parasitic capacitance parameters and reducing the calculation complexity.

Solutions for solving problems

In a first aspect of the present invention, a method for extracting parasitic capacitance parameters of a multi-conductor system is provided, characterized by comprising:

Constructing a physical model of a two-dimensional geometric structure of an integrated circuit based on the integrated circuit layout data, wherein the physical model of the two-dimensional geometric structure includes a plurality of conductors and a plurality of dielectrics;

Calculate a numerical simulation diagram of voltage and charge at any point in the physical model of the two-dimensional geometric structure;

Determining a plurality of media to be candidate for merging based on the numerical simulation diagram of the voltage and the charge;

Determine whether multiple media to be merged meet the following conditions:

(1)d_i>K*H

Wherein, d_i is the thickness of the i-th medium in the physical model of the two-dimensional geometric structure, H is the thickness of the conductor, and K is a preset proportionality coefficient.

(2)max(h_i,h_(i+1))/min(h_i,h_(i+1))>8

Wherein, h_i is the distance from the conductor to the i-th medium, h_(i+1) is the distance from the conductor to the i+1-th medium,

If it is determined that the medium i and the medium i+1 satisfy the above conditions (1) and (2), then the medium i and the medium i+1 are merged into one medium; and

The parasitic capacitance parameters of each conductor in the physical model of the two-dimensional geometric structure of the integrated circuit are solved based on the merged medium.

In one implementable manner of the present invention, it also includes using a field solver to solve the parasitic capacitance parameters of each conductor based on the merged medium, wherein the dielectric constant of the merged medium is calculated according to the following formula: er=(s_1*〖er〗_1+s_2*〖er〗_2)/(s_1+s_2), wherein s_i is the area of medium i, and 〖er〗_i is the dielectric constant of medium i.

In an implementable manner of the present invention, the charge values of the plurality of media to be candidate for merging are smaller than a preset value.

In one possible implementation of the present invention, it also includes: for a physical model of the two-dimensional geometric structure of the integrated circuit including the merged medium, using the boundary element method to calculate the amount of charge on each dielectric boundary, and then numerically integrating the amount of charge on each conductor boundary to extract the parasitic capacitance parameters of each conductor.

The second aspect of the present invention provides a parasitic capacitance parameter extraction device for a multi-conductor system, characterized in that it comprises a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the steps of any of the above-mentioned parasitic capacitance parameter extraction methods for a multi-conductor system when running the computer program.

The third aspect of the present invention further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is run, the steps of any of the above-mentioned methods for extracting parasitic capacitance parameters of a multi-conductor system are executed.

Effects of the Invention

The present invention improves the performance of the field solver, reduces the number of iterations of adaptive convergence by merging equivalent media, reduces the number of media, and further reduces the number of elements (i.e., grid units used in the boundary element numerical method), thereby reducing the number of integral calculations and the dimension of the equation, and ultimately improving the calculation performance, greatly accelerating the extraction speed of the parasitic capacitance parameters of the multi-conductor system, and improving the design efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a two-dimensional geometric structure of an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a partial enlarged diagram of an integrated circuit conductor according to an embodiment of the present invention.

FIG. 3 is a conductor medium geometric model according to an embodiment of the present invention.

FIG. 4 is a voltage numerical simulation diagram according to an embodiment of the present invention.

FIG. 5 is a numerical simulation diagram of electric field lines according to an embodiment of the present invention.

FIG. 6 is a flowchart according to an embodiment of the present invention.

FIG. 7 shows the topological information of each medium and conductor in the integrated circuit layout according to the embodiment of the present invention.

Detailed ways

The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and/or" in the specification and claims represents at least one of the connected objects, and the character "/" generally indicates that the objects associated with each other are in an "or" relationship.

In the process of extracting the parasitic capacitance parameters of a multi-conductor system using a two-dimensional or 2.5-dimensional method, a two-dimensional geometric structure physical model of the integrated circuit is usually established based on the layout information of the integrated circuit. The layout information of industrial integrated circuits can be stored in a memory using a variety of storage formats (CFI, GDSⅡ, Oasis). The layout information of the integrated circuit stored in the memory contains relevant information describing the conductor and the medium, and the relevant information of the conductor and the medium includes the thickness and position information of the conductor and the thickness, position and relative dielectric constant of the medium. Based on the layout file of the integrated circuit, the corresponding information describing the conductor and the medium can be extracted to construct the required two-dimensional geometric structure model of the integrated circuit.

Fig. 1 is a cross-sectional view of a two-dimensional geometric structure model of an integrated circuit established according to an embodiment of the present invention. Fig. 2 is a partial enlarged view of a two-dimensional geometric structure model of an integrated circuit established according to an embodiment of the present invention.

1 and 2 , a plurality of (eight in the example) conductors and a number of dielectrics are typically marked inside the two-dimensional geometric structure physical model of the established integrated circuit. The plurality of conductors can be classified into main conductors (satisfying the Dirichlet boundary condition u=1) and ambient conductors (satisfying the Dirichlet boundary condition u=0).

As can be seen from Figures 1 and 2, a plurality of strip-shaped media are distributed along the vertical direction of the two-dimensional geometric structure physical model, and the plurality of strip-shaped media extend along the horizontal direction. The dielectric constants of the plurality of strip-shaped media are different.

For the two-dimensional geometric structure physical model of the integrated circuit shown in Figure 1, solving the parasitic capacitance parameters of the multi-conductor system can be completed as follows:

(1) Establish the physical model equation for the two-dimensional geometric structure physical model:

(a) Equation (1) indicates that the electric potential u satisfies the Laplace equation in each dielectric region of the two-dimensional geometric structure physical model.

(b) Equation (2) indicates that each conductor surface in the two-dimensional geometric structure physical model satisfies the Dirichlet boundary condition (u=1 on the main conductor surface; u=0 on the ambient conductor surface).

(c) Equation (3) indicates that the Neumann boundary conditions are satisfied on the outer boundaries of each medium region of the two-dimensional geometric structure physical model.

(d) Equation (4) represents the electric displacement on multiple dielectric interfaces of the two-dimensional geometric structure physical model, the potential continuity condition, and ε _a and ε _b are the dielectric constants of the media on both sides of the multiple dielectric interfaces, respectively.

(2) Based on the physical model equation established in step (1), the charge on the boundary of each dielectric region is calculated using numerical methods.

For the above physical model equations, commonly used numerical methods for extracting parasitic capacitance parameters include: Finite Difference Method (FDM), Finite Element Method (FEM), Measured Equation of Invariance (MEI), Random Walk Method (Random Walk or Monte Carlo) and Boundary Element Method (BEM).

Among them, the boundary element method is a numerical solution method for partial differential equations developed on the basis of the classical integral equation method and the finite element method. The basic idea of the boundary element method is to transform the differential equations in the calculation area into integral equations on the boundary of the area; then divide the boundary of the area into boundary elements of finite size, thereby discretizing the boundary integral equations into a system of linear algebraic equations, and obtain the physical quantities of the boundary nodes by solving the linear equations.

The boundary element method can be divided into direct boundary element method (DBEM) and indirect boundary element method (IBEM). In a typical example of the present invention, the direct boundary element method (DBEM) is used to extract the parasitic capacitance parameters of the multi-conductor system.

More specifically, in the process of extracting the parasitic capacitance parameters of a multi-conductor system using the direct boundary element method of the present invention, firstly, equation (1) can be converted into the following boundary integral equation according to Green's second formula:

∫uq ^* -u ^* qds＝-c _s u _s (5)

The variable with * in equation (5) is the field distribution function corresponding to the basic solution at the source point s (the midpoint of the grid line segment in the dielectric region), and u _s is the electric potential of the source point s. If the source point s is in the dielectric region of Figure 1, the coefficient c _s = 1; if the source point is on the boundary of the dielectric region of Figure 1, the coefficient c _s = 1/2.

By discretizing formula (5) on each dielectric region of the two-dimensional geometric structure physical model of the integrated circuit shown in FIG. 1 , a discretized integral equation for each dielectric region can be obtained.

The discretized integral equation for each medium region is combined with formula (4) into multiple linear equations. By solving each linear equation, the charge on each medium boundary can be calculated.

(3) Based on the calculated charge on each dielectric boundary, the charge on each conductor boundary of multiple conductors in the two-dimensional geometric structure physical model of the integrated circuit shown in FIG. 1 is numerically integrated to obtain the parasitic capacitance parameter (capacitance value) of each conductor.

In the past, when extracting the parasitic capacitance parameters of a multi-conductor system using two-dimensional or 2.5-dimensional methods, each dielectric region of the two-dimensional geometric structure physical model must be meshed. When using numerical methods to solve the parasitic capacitance parameters of multiple conductors, as the number of grid cells increases, the dimension of the linear equations used in the numerical method also increases, and the solution process is computationally intensive and time-consuming.

In this regard, in the process of extracting parasitic capacitance parameters of a multi-conductor system of the present invention, equivalent dielectric merging is performed for some dielectric regions, and the dielectric constant of the merged dielectric regions can be recalculated according to the area ratio, thereby speeding up the extraction of parasitic capacitance parameters.

The following describes in detail the implementation process of quickly extracting parasitic capacitance parameters of a multi-conductor system according to the present invention.

As shown in FIG. 3 , A, B, and C are three different dielectric regions in the physical model of the two-dimensional geometric structure of the integrated circuit; the four rectangular blocks 1, 2, 3, and 4 illustrated in the dielectric region B are conductors.

In the present invention, the conductors in the dielectric region include a main conductor 2 and environmental conductors 1, 3, 4, and different voltages are set for the main conductor 2 and the environmental conductors 1, 3, 4 respectively.

In a specific embodiment, when the numerical calculation of parasitic capacitance parameters is performed with the rectangular block 2 as the main conductor, for example, using the direct boundary element method, the main conductor 2 is set to a unit voltage of non-zero V, and the rectangular blocks 1, 3, 4 are set as environmental conductors. When the numerical calculation of parasitic capacitance parameters is performed on the environmental conductors 1, 3, 4, for example, using the direct boundary element method, the environmental conductors 1, 3, 4 are all set to a voltage of 0V. By setting the unit voltage and 0V voltage to the main conductor 2 and the environmental conductors 1, 3, 4, respectively, as described above, the charge value solved by, for example, using the numerical algorithm of the direct boundary element method is numerically integrated on each boundary of the main conductor 2 and the environmental conductors 1, 3, 4 to obtain the parasitic capacitance parameters (capacitance values) of the corresponding conductors.

In the present invention, in order to speed up the extraction of parasitic capacitance parameters, a numerical method, such as a boundary element method, is first used to obtain a numerical simulation diagram of the voltage u at any point in the physical model of the two-dimensional geometric structure shown in Figure 3. As shown in Figure 4, the voltage values between conductor 1 and conductor 2, and between conductor 2 and conductor 3 change dramatically, and the changes in the medium A and medium C regions are relatively uniform.

Similarly, according to formula (6):

The numerical simulation diagram of the charge at any point in the two-dimensional geometric structure physical model shown in FIG3 can be obtained, as shown in FIG5 .

It can be seen intuitively from FIG5 that in the dielectric regions A and C which are far away from the main conductor 2 and the environmental conductors 1, 3, 4 on the dielectric region B, the electric field lines are basically vertical.

From the numerical simulation diagram of voltage u in FIG4 and the numerical simulation diagram of charge in FIG5 , the following conclusion can be drawn: in dielectric regions A and C that are far away from the conductors 1, 2, 3, and 4 on dielectric region B, the charge values are very small and vary relatively evenly. Such dielectric regions can be merged if the conditions are met.

As shown in FIG6 , in order to determine whether corresponding dielectric regions in the physical model of the two-dimensional geometric structure of the integrated circuit can be merged, the present invention first calculates the topological information of each dielectric and conductor in the physical model of the two-dimensional geometric structure of the integrated circuit.

In a specific embodiment, the present invention calculates the topological information of each medium and conductor in the physical model of the two-dimensional geometric structure of the integrated circuit, including: calculating the thickness of the main conductor, the thickness of each medium; and the vertical distance between the main conductor and different mediums.

More specifically, in the present invention, the topological information is obtained based on the main conductor, for example, the thickness of the main conductor is calculated as H, the thickness of each medium is calculated as h _i , and the vertical distance between each medium and the main conductor is calculated as d _i . It is determined whether the medium i can be merged only if the necessary conditions are met, that is,

d _i ＞K*H (7)

Here, K is a set proportional coefficient, for example, K is set to 4.

Through experiments, the thickness of the main conductor is selected as a reference in the present invention, and the medium is "far enough away (>4 times the thickness of the main conductor)" from the main conductor, so that the numerical error caused by amputation and merging is small.

The stacked media in the physical model of the two-dimensional geometric structure are sorted from bottom to top. If medium i meets the above necessary conditions, then the adjacent media of medium i (such as the upper layer medium) must also meet the above necessary conditions. Optionally, when medium i meets the distance of four times the thickness of the main conductor, it can be considered that the media i+1 and above meet the above necessary conditions.

The next step is to determine

max( _hi ,hi ₊₁ )/min( _hi ,hi ₊₁ )＞8 (8)

Wherein, _hi , hi ₊₁ are the thickness of the i-layer and i+1-layer dielectrics;

If medium i and medium i+1 also satisfy the above thickness ratio formula (8), the two media can be merged into one medium. Then, for other media distributed in layers in the physical model of the two-dimensional geometric structure, the upper media can be processed in a loop starting from the _hi+1 layer of medium. Finally, the processed physical model of the two-dimensional geometric structure (including all information of the conductor and the medium) is passed to the Solver software to use the field solver to solve the capacitance of each conductor based on the merged medium. In solving the capacitance of each conductor based on the merged medium using the field solver, for the newly merged medium, the dielectric constant is calculated according to the following formula: (Where _si is the area of medium i, er _i is the dielectric constant of medium i.

FIG. 7 shows a flow chart of the present invention for quickly extracting parasitic capacitance parameters of a multi-conductor system.

The following is a flowchart of the present invention for quickly extracting parasitic capacitance parameters of a multi-conductor system, as shown in FIG. 7 , and a method of the present invention for accelerating the capacitance solution speed by merging equivalent dielectrics is described in conjunction with a specific example. The operation process includes the following steps:

(S1) obtaining integrated circuit layout data, and constructing a physical model of the two-dimensional geometric structure of the integrated circuit based on the obtained integrated circuit layout data, wherein the physical model includes information such as various conductors (main conductors, environmental conductors), stacked and distributed media, etc.

It is understandable that the present invention can obtain the topological information of each medium and conductor based on the physical model, such as the corresponding geometric characteristics, electrical characteristics and other information of various conductors and media. The geometric characteristics include thickness, coordinates of geometric points of the medium and conductor (such as the conductor is a rectangle, then the information includes the coordinate information of the four vertices of the conductor (xi, yi)), and the electrical characteristics include voltage, dielectric constant and the like.

In the physical model of the two-dimensional geometric structure of the integrated circuit shown in the example of FIG1 , there are eight conductors inside, one of which is specially marked/set as the main conductor, and a voltage of 1V is set on its boundary, and the remaining seven conductors are marked/set as environmental conductors, and a voltage of 0V is set on their boundaries; except for the above-mentioned conductors, the remaining areas are all stacked strip dielectric areas, and the dielectric constants of the dielectrics are different from each other.

(S2) Calculating topological information of each medium and conductor based on the physical model of the constructed two-dimensional geometric structure of the integrated circuit.

In one implementation of the present invention, as shown in FIG6 : calculating the topological information of each medium and conductor includes: calculating the thickness H of the main conductor d, the thickness h1 and h2 of the medium A and the medium B; and the distance from the main conductor to the medium A, and the distance from the main conductor to the medium B;

(S3) Based on the topological information calculated in step 2, determine whether medium A and medium B meet the following two conditions:

(1)d_i>4*H (7)

(2)max(h_A,h_B)/min(h_A,h_B)>8 (8)

If it is determined that the above two conditions (1) and (2) are met, medium A and medium B are merged into one medium C.

When solving the capacitance of each conductor based on the merged medium using the field solver, the dielectric constant of the medium C is calculated using the following formula: (Where _SA is the area of medium A, Fr _A is the dielectric constant of medium A.

If it is determined that any of the above conditions is not met, medium A and medium B will not be merged.

(S4) The geometric information processed in step 3 (the position information of the conductor, the position information of the medium and the corresponding dielectric constant) is transmitted to the Solver software written by the direct boundary element method to solve the capacitance.

By adopting the equivalent medium merging of the present invention, the number of medium regions can be reduced, thereby reducing the number of grid cells, thereby reducing the number of unknown quantities in the equation group and further improving the performance of the software.

In this regard, in the process of extracting parasitic capacitance parameters of a multi-conductor system of the present invention, equivalent dielectric merging is performed for some dielectric regions, and the dielectric constant of the merged dielectric regions can be recalculated according to the area ratio, thereby speeding up the extraction of parasitic capacitance parameters.

The following table records the comparison of the capacitance results obtained by the Solver software written by the direct boundary element method without merging the dielectrics in the two-dimensional geometric structure model of the integrated circuit and after being processed by the above method of the present invention. The numerical error introduced by merging the dielectrics of "long distance" (i.e., the distance between each dielectric and the main conductor is greater than 4 times the thickness of the main conductor) is negligible, but the software performance is greatly improved. For the geometric structure model shown in Figure 1, the software takes 0.6s before processing, and after being processed by the above method, the software can calculate the capacitance value in only 0.2s, which is 3 times faster.

Table 1 Comparison results of capacitance value error test

Conductor Name default Equivalent medium merger error master 0.256387 0.256492 0.041% c2 -0.001235 -0.00123688 0.178% c3 -0.163498 -0.163526 0.017% c4 -0.002675 -0.00268222 0.281% lbEnv -0.013931 -0.0139611 0.215% ltEnv -0.003196 -0.00317018 -0.816% rbEnv -0.001553 -0.0015659 0.806% rtEnv -0.001112 -0.00110815 -0.316%

The present invention also provides a device for extracting parasitic capacitance parameters of a multi-conductor system, which can be implemented by a general computer or computer system, wherein the computer or computer system has an input device, a display device, an external I/F, a communication I/F, a processor, and a memory. These hardware are connected to each other in a manner that allows communication via a bus.

The processor is a computer's internal CPU, or a dedicated CPU, DSP or other processing unit. The memory device includes a computer-readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

The memory stores a program running on the processor, and the processor executes the process of the parasitic capacitance parameter extraction method of the multi-conductor system when running the program.

The present invention also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, each process of the above-mentioned method for resistance compensation of wiring between multiple groups of parallel ports is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims (6)

1. The parasitic capacitance parameter extraction method of the multi-conductor system is characterized by comprising the following steps of:

Constructing a physical model of a two-dimensional geometry of the integrated circuit based on integrated circuit layout data, wherein the physical model of the two-dimensional geometry comprises a plurality of conductors and a plurality of mediums;

calculating a numerical simulation diagram of voltage and charge at any point in a physical model of the two-dimensional geometric structure;

Determining a plurality of media to be combined candidate based on the numerical simulation diagram of the voltage and the charge;

Judging whether a plurality of media to be combined candidate meets the following conditions:

(1)d_i>K*H

Wherein d_i is the thickness of the i-th medium in the physical model of the two-dimensional geometric structure, H is the thickness of the conductor, K is a preset proportionality coefficient,

(2)max(h_i,h_(i+1))/min(h_i,h_(i+1))>8

Where h_i is the distance of the conductor from the ith medium, h_ (i+1) is the distance of the conductor from the ith+1th medium,

If the medium i and the medium i+1 are judged to meet the conditions (1) and (2), combining the medium i and the medium i+1 into one medium; and

And solving parasitic capacitance parameters of each conductor in a physical model of the two-dimensional geometry of the integrated circuit based on the combined media.

2. The method of extracting parasitic capacitance parameters of a multi-conductor system according to claim 1, further comprising solving, with a field solver, the parasitic capacitance parameters of each conductor based on the combined media, wherein the dielectric constant of the combined media is calculated as follows: where s _i is the area of medium i and er _i is the dielectric constant of medium i.

3. The method for extracting parasitic capacitance parameters of a multi-conductor system according to claim 1, wherein,

And the charge values of the media to be combined candidate are smaller than a preset value.

4. The method for extracting parasitic capacitance parameters of a multi-conductor system according to claim 1, further comprising,

And calculating the charge quantity on each medium boundary by using a boundary element method for a physical model of the two-dimensional geometric structure of the integrated circuit containing the merged medium, and then carrying out numerical integration on the charge quantity on each conductor boundary to extract the parasitic capacitance parameters of each conductor.

5. A parasitic capacitance parameter extraction apparatus of a multi-conductor system, comprising a memory and a processor, the memory having stored thereon a computer program running on the processor, the processor executing the steps of the parasitic capacitance parameter extraction method of a multi-conductor system according to any one of claims 1-4 when the computer program is run.

6. A computer readable storage medium having stored thereon a computer program which, when run, performs the steps of the parasitic capacitance parameter extraction method of a multi-conductor system as claimed in any one of claims 1-4.