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CN116190375B - An electrostatic protection device and its preparation method - Google Patents

An electrostatic protection device and its preparation method

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Publication number
CN116190375B
CN116190375B CN202310052603.5A CN202310052603A CN116190375B CN 116190375 B CN116190375 B CN 116190375B CN 202310052603 A CN202310052603 A CN 202310052603A CN 116190375 B CN116190375 B CN 116190375B
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Prior art keywords
region
well region
implantation
layer
injection
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CN116190375A (en
Inventor
蒋骞苑
赵德益
顾彦国
吕海凤
张啸
郝壮壮
胡亚莉
苏海伟
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Shanghai Wei'an Semiconductor Co ltd
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Shanghai Wei'an Semiconductor Co ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明涉及一种静电保护器件及其制备方法，涉及半导体技术领域，器件包括：衬底、外延层、埋层、依次邻接的第一至第五阱区、至少两个轻掺杂注入区、重阱区、第一至第七注入区、介质层、金属层，第一阱区和第五阱区的底部与衬底、埋层同时接触；第二至第四阱区的底部与埋层接触。本发明所提供的静电保护器件具有较低的触发电压和击穿电压，更强的通流能力，较高的静电泄放能力、较高的稳定性和可靠性，且同时不会增加静电保护器件的面积。

The present invention relates to an electrostatic protection device and a method for preparing the same, and relates to the field of semiconductor technology. The device comprises: a substrate, an epitaxial layer, a buried layer, sequentially adjacent first to fifth well regions, at least two lightly doped injection regions, a heavily doped well region, first to seventh injection regions, a dielectric layer, and a metal layer. The bottoms of the first and fifth well regions are in contact with both the substrate and the buried layer; the bottoms of the second to fourth well regions are in contact with the buried layer. The electrostatic protection device provided by the present invention has lower trigger voltage and breakdown voltage, stronger current flow capacity, higher electrostatic discharge capability, higher stability and reliability, and does not increase the area of the electrostatic protection device.

Description

Electrostatic protection device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to an electrostatic protection device with low trigger voltage and stronger through-current capability and a preparation method thereof.
Background
Electrostatic discharge (Electro-STATIC DISCHARGE, ESD) is a ubiquitous phenomenon that can occur between any two objects. Electrostatic discharge can cause significant damage to the normal operation of integrated circuits in electrical devices, and in severe cases can even burn integrated circuits out, rendering them ineffective. With the development of the integrated circuits toward microminiaturization, ultra-high integration and multifunctionality, the integrated circuits are also more and more sensitive to electrostatic discharge, and it is very important and urgent to improve the electrostatic protection capability of the integrated circuits.
The existing electrostatic protection semiconductor devices are various, and usually devices such as a diode, a triode, a gate-grounded NMOS (GGNMOS) or a silicon controlled rectifier (Silicon Controlled Rectifier, SCR) are used as basic protection units. Compared with a protection device adopting an SCR structure, the basic unit of the electrostatic protection device adopting the triode structure has stronger current capability, and is safer and more flexible to application, because the maintaining voltage and the maintaining current of the SCR device are low, latch-up effect is easy to occur, and a later-stage circuit is damaged.
The current higher requirements for the electrostatic protection device are mainly that on one hand, the trigger voltage of the electrostatic protection device needs to be reduced, especially for an integrated circuit with lower working voltage, in order to avoid the integrated circuit being damaged before the electrostatic protection device is started and current is discharged, the trigger voltage of the electrostatic protection device used should be as low as possible. On the other hand, the current capacity of the device needs to be improved, the chip area is usually increased to obtain larger current capacity in the prior art, but the mode is unfavorable for miniaturization of the device, and the application scene is limited, so that aiming at the problems, it is necessary to design an electrostatic protection device with low trigger voltage and stronger current capacity, and the electrostatic protection device is suitable for miniaturization, and a preparation method thereof, so as to meet the requirements of specific application scenes.
Disclosure of Invention
In order to solve the technical problems, the invention provides an electrostatic protection device and a preparation method thereof, which have lower trigger voltage and stronger through-current capability, do not increase the chip area, and are suitable for miniaturization of devices.
The technical problems solved by the invention can be realized by adopting the following technical scheme:
An electrostatic protection device providing a substrate of a first conductivity type, and an epitaxial layer on the substrate, comprising:
A buried layer of a second conductivity type formed in a predetermined region of the substrate, and upwardly diffused into the epitaxial layer;
The epitaxial layer comprises at least five well regions, a second well region, a fourth well region, a first well region, a second well region, a third well region and a fifth well region, wherein the five well regions are formed in the epitaxial layer in sequence and comprise a first well region, a third well region and a fifth well region which are of a first conductivity type, the bottoms of the first well region and the fifth well region are simultaneously contacted with the upper surface of the substrate and the buried layer in the epitaxial layer;
At least two lightly doped injection regions of the second conductivity type formed in the third well region, including a first lightly doped injection region and a second lightly doped injection region;
A heavy well region of the first conductivity type formed between the first lightly doped implant region and the second lightly doped implant region;
the plurality of heavily doped injection regions comprise first to fifth injection regions of a second conductivity type, wherein the first injection region is formed in the second well region, the second injection region is formed in the first lightly doped injection region, the third injection region is formed in the heavy well region, the fourth injection region is formed in the second lightly doped injection region, and the fifth injection region is formed in the fourth well region;
the dielectric layer is formed above the epitaxial layer, and contact holes corresponding to the first injection region to the seventh injection region are formed in the dielectric layer;
The metal layer comprises a first grounding end metal layer which is respectively connected with the first injection region, the sixth injection region and the second injection region, an IO end metal layer which is connected with the third injection region, and a second grounding end metal layer which is respectively connected with the fourth injection region, the seventh injection region and the fifth injection region.
The electrostatic protection device is characterized in that a first field oxide layer is arranged above a first well region and on the left side edge of a second well region, second to seventh field oxide layers are respectively and sequentially arranged between two adjacent heavily doped injection regions, and an eighth field oxide layer is arranged on the right side edge of a fourth well region and above a fifth well region.
According to the electrostatic protection device, the resistivity of the epitaxial layer is larger than 10Ω×cm, and the thickness is 3-10 μm;
The epitaxial layer is of a first conductivity type or a second conductivity type;
When the first conductivity type is N-type, the second conductivity type is P-type, and
When the first conductivity type is P-type, the second conductivity type is N-type.
According to the electrostatic protection device disclosed by the invention, the distances from the heavy well region to the first lightly doped injection region and the second lightly doped injection region are the same.
The invention also provides a preparation method of the electrostatic protection device, which is used for preparing the electrostatic protection device and comprises the following steps:
Step S1, providing a substrate of a first conductivity type, growing a first thin oxide layer on the substrate, performing photoetching and ion implantation, performing thermal process propulsion to form a buried layer of a second conductivity type, and removing the first thin oxide layer on the surface by wet etching;
step S2, growing an epitaxial layer on the surface, wherein the epitaxial layer is grown at a high temperature so that the buried layer is upwards diffused into the epitaxial layer;
Step S3, sequentially carrying out photoetching and ion implantation of a first well region, a third well region and a fifth well region of a first conductivity type on the surface of the epitaxial layer, carrying out photoetching and ion implantation of a second well region and a fourth well region of a second conductivity type, and then carrying out high-temperature propulsion to enable the first well region to the fifth well region to be sequentially adjacent, enabling the bottoms of the first well region and the fifth well region to be simultaneously contacted with the substrate and the buried layer in the epitaxial layer, and enabling the bottoms of the second well region, the third well region and the fourth well region to be contacted with the buried layer;
step S4, growing a field oxide layer on the surface of the epitaxial layer through a local oxidation process;
S5, forming a first lightly doped injection region and a second lightly doped injection region of a second conductivity type on the surface of the third well region through photoetching and ion injection, and then performing high-temperature propulsion;
S6, forming a heavy well region on the surface of the third well region through photoetching and ion implantation, wherein the distances from the heavy well region to the first lightly doped implantation region and the second lightly doped implantation region are the same, then performing high-temperature propulsion, and after the propulsion, laterally diffusing the heavy well region to the lower part of the field oxide layer;
Step S7, forming first to fifth injection regions of a second conductivity type on the surface through photoetching and ion injection, forming a first injection region in the second well region, forming a second injection region in the first lightly doped injection region, forming a third injection region in the heavy well region, forming a fourth injection region in the second lightly doped injection region, and forming a fifth injection region in the fourth well region;
step S8, forming a sixth injection region and a seventh injection region of the first conductivity type in the third well region through photoetching and ion injection;
Step S9, a dielectric layer is deposited on the upper surface of the epitaxial layer, and then contact holes corresponding to the first injection region to the seventh injection region are formed through photoetching and etching;
And S10, depositing a metal layer on the upper surface of the dielectric layer and in the contact hole so that a first grounding end metal layer is connected with the first injection region, the sixth injection region and the second injection region, an IO end metal layer is connected with the third injection region, and a second grounding end metal layer is connected with the fourth injection region, the seventh injection region and the fifth injection region.
The invention relates to a preparation method of an electrostatic protection device, wherein the growth thickness of the first thin oxide layer is as follows
In the method for manufacturing the electrostatic protection device, in the step S1, the ion implantation element of the buried layer is antimony or arsenic, the implantation energy is 60-100 KeV, the implantation dosage is 5E 14-8E 15 per square centimeter, the implantation angle is 7 ℃, the furnace tube advancing temperature is 1050-1200 ℃ and the time is 60-120 minutes, so that the junction depth of the buried layer in the substrate is 2-3 mu m.
In the method for manufacturing the electrostatic protection device, in the step S3, the injection elements of the first well region, the third well region and the fifth well region are boron, the injection dosage is 2e 12-5 e13 per square centimeter, the injection energy is 60-100 kev, and the injection angle is 7 degrees;
The injection elements of the second well region and the fourth well region are phosphorus, the injection dosage is 1E 14-1E 15 per square centimeter, the injection energy is 80-120 KeV, and the injection angle is 7 degrees;
and then carrying out high-temperature propulsion, wherein the propulsion temperature is 1000-1150 ℃ and the propulsion time is 60-360 minutes.
In the method for manufacturing the electrostatic protection device, in the step S5, the injection elements of the first lightly doped injection region and the second lightly doped injection region are phosphorus, the injection dosage is 1e 13-1 e14 per square centimeter, the injection energy is 60-100 kev, the injection angle is 7 degrees, the advancing temperature is 1000-1100 ℃, and the advancing time is 60-120 minutes, so that the junction depth of the first lightly doped injection region and the second lightly doped injection region is 1.5-3 um, but the first lightly doped injection region and the second lightly doped injection region are not contacted with the buried layer in the longitudinal direction.
In the preparation method of the electrostatic protection device, in the step S6, the injection element of the heavy well region is boron or boron difluoride, the injection dosage is 1E 14-8E 14 per square centimeter, the injection energy is 80-120 KeV, the pushing temperature is 950-1050 ℃, and the pushing time is 30-60 minutes.
In the method for manufacturing the electrostatic protection device, in the step S7, the injection elements of the first to fifth injection regions are phosphorus or arsenic, the injection dose is 2e 15-1 e16 per square centimeter, and the injection energy is 80-120 kev;
the implantation elements of the sixth implantation region and the seventh implantation region are boron or boron difluoride, the implantation dosage is 1E 15-8E 15 cm/square centimeter, and the implantation energy is 40-80 KeV.
In the method for manufacturing the electrostatic protection device of the present invention, in the step S7, an annealing process or a rapid thermal annealing process is used after the first to seventh implantation regions are implanted;
If an annealing process is used, the annealing temperature is 850-950 ℃ and the annealing time is 30-60 minutes;
if a rapid thermal annealing process is used, the rapid thermal annealing temperature is 950-1050 ℃, and the rapid thermal annealing time is 10-30 seconds.
The preparation method of the electrostatic protection device of the present invention, the step S4 includes:
step S41, growing a second thin oxide layer on the surface of the epitaxial layer, and then depositing a silicon nitride layer;
Step S42, sequentially performing photoetching, silicon nitride dry etching and photoresist removal, then forming a first field oxide layer above the first well region and the left side edge of the second well region, sequentially forming a second field oxide layer to a seventh field oxide layer between two adjacent heavily doped injection regions, and forming an eighth field oxide layer above the right side edge of the fourth well region and the fifth well region;
and S43, removing the residual silicon nitride layer by adopting a wet etching process.
The invention relates to a preparation method of an electrostatic protection device, wherein the thickness of the second thin oxide layer is
The invention relates to a preparation method of an electrostatic protection device, wherein the thickness of a silicon nitride layer is as follows
The technical scheme of the invention has the beneficial effects that:
The electrostatic protection device provided by the invention has the advantages of lower trigger voltage and breakdown voltage, stronger through-current capability, higher electrostatic discharge capability, higher stability and reliability, and meanwhile, the area of the electrostatic protection device is not increased.
Drawings
FIGS. 1-9 are schematic views showing steps of a method for fabricating an electrostatic protection device according to a preferred embodiment of the present invention;
FIGS. 10-11 are schematic views showing the structure of an electrostatic protection device according to a preferred embodiment of the present invention;
fig. 12 is an equivalent circuit diagram of an electrostatic protection device in a preferred embodiment of the present invention.
Reference numerals:
1.2, a buried layer, 3, an epitaxial layer, 41, a first well region, 42, a second well region, 43, a third well region, 44, a fourth well region, 45, a fifth well region, 51, a first field oxide layer, 52, a second field oxide layer, 53, a third field oxide layer, 54, a fourth field oxide layer;
55. a fifth field oxide layer, 56, a sixth field oxide layer, 57, a seventh field oxide layer;
58. 61, a first lightly doped injection region;
62. A second lightly doped implant region; a heavy well region 81, a first injection region;
82. the second injection region, 83, the third injection region, 84, the fourth injection region;
85. the semiconductor device comprises a fifth injection region, 86, a sixth injection region, 87, a seventh injection region, 9, a dielectric layer, 101, a first grounding end metal layer, 102 and a second grounding end metal layer;
103. And the IO end metal layer.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
In the embodiment of the invention, the conductive type includes a first conductive type and a second conductive type, and the first conductive type and the second conductive type are opposite, for example:
If the first conductivity type is N type, the second conductivity type is P type;
If the first conductivity type is P-type, the second conductivity type is N-type (this is exemplified in the following embodiment one).
In the following, reference will be made to the case of different average doping concentrations of n+ type, N-type, p+ type, P type and P type, specifically, the doping concentration of N type is smaller than that of N type, the doping concentration of N type is smaller than that of n+ type, the doping concentration of P type is smaller than that of P type, and the doping concentration of P type is smaller than that of p+ type.
Example 1
An embodiment of the present invention provides an electrostatic protection device, referring to fig. 10, providing a substrate 1 of a first conductivity type, and an epitaxial layer 3 on the substrate 1, including:
a buried layer 2 of a second conductivity type formed in a predetermined region of the substrate 1, and the buried layer 2 being diffused upward into the epitaxial layer 3;
At least five well regions formed in the epitaxial layer 3 adjacently in sequence, including a first well region 41, a third well region 43 and a fifth well region 45 of the first conductivity type, the bottoms of the first well region 41 and the fifth well region 45 are simultaneously contacted with the upper surface of the substrate 1 and the buried layer 2 in the epitaxial layer 3;
At least two lightly doped implant regions of the second conductivity type formed in the third well region 43, including a first lightly doped implant region 61 and a second lightly doped implant region 62;
a heavy well region 7 of the first conductivity type formed between the first lightly doped implant region 61 and the second lightly doped implant region 62;
a plurality of heavily doped implant regions including first to fifth implant regions of a second conductivity type, the first implant region 81 being formed in the second well region 42, the second implant region 82 being formed in the first lightly doped implant region 61, the third implant region 83 being formed in the heavy well region 7, the fourth implant region 84 being formed in the second lightly doped implant region 62, the fifth implant region 85 being formed in the fourth well region 44, the sixth implant region 86 and the seventh implant region 87 of the first conductivity type being formed in the third well region 43;
a dielectric layer 9 formed above the epitaxial layer 3, wherein contact holes corresponding to the first to seventh injection regions are formed in the dielectric layer 9;
the metal layer comprises a first grounding end metal layer 101 which is respectively connected with the first injection region 81, the sixth injection region 86 and the second injection region 82, an IO end metal layer 103 which is connected with the third injection region 83, and a second grounding end metal layer 102 which is respectively connected with the fourth injection region 84, the seventh injection region 87 and the fifth injection region 85.
In a preferred embodiment, the first field oxide layer 51 is disposed above the first well region 41 and on the left side edge of the second well region 42, the second to seventh field oxide layers are disposed between two adjacent heavily doped injection regions in sequence, namely, the second field oxide layer 52 is disposed between the first injection region 81 and the sixth injection region 86, the third field oxide layer 53 is disposed between the sixth injection region 86 and the second injection region 82, the fourth field oxide layer 54 is disposed between the second injection region 82 and the third injection region 83, the fifth field oxide layer 55 is disposed between the third injection region 83 and the fourth injection region 84, the sixth field oxide layer 56 is disposed between the fourth injection region 84 and the seventh injection region 87, the seventh field oxide layer 57 is disposed between the seventh injection region 87 and the fifth injection region 85, and the eighth field oxide layer 58 is disposed above the right side edge of the fourth well region 44 and the fifth well region 45.
The method is characterized in that the ion implantation element of the buried layer 2 is antimony or arsenic, the implantation energy is 60-100 KeV, the implantation dosage is 5E 14-8E 15 per square centimeter, the implantation angle is 7 degrees, the furnace tube advancing temperature is 1050-1200 ℃ and the time is 60-120 minutes, so that the junction depth of the buried layer 2 in the substrate 1 is 2-3 mu m.
In a preferred embodiment, the resistivity of the epitaxial layer 3 is greater than 10Ω×cm, and the thickness is 3-10 μm;
The epitaxial layer 3 is of either the first conductivity type or the second conductivity type.
In a preferred embodiment, the implantation elements of the first well region 41, the third well region 43 and the fifth well region 45 are boron, the implantation dose is 2e 12-5 e13 per square centimeter, the implantation energy is 60-100 kev, and the implantation angle is 7 degrees;
the implantation elements of the second well region 42 and the fourth well region 44 are phosphorus, the implantation dosage is 1E 14-1E 15 per square centimeter, the implantation energy is 80-120 KeV, and the implantation angle is 7 degrees;
and then carrying out high-temperature propulsion, wherein the propulsion temperature is 1000-1150 ℃ and the propulsion time is 60-360 minutes.
In a preferred embodiment, the first lightly doped implant region 61 and the second lightly doped implant region 62 are made of phosphorus, the implant dose is 1e 13-1 e14 per square centimeter, the implant energy is 60-100 kev, the implant angle is 7 degrees, the advancing temperature is 1000-1100 ℃ and the advancing time is 60-120 minutes, so that the junction depth of the first lightly doped implant region 61 and the second lightly doped implant region 62 is 1.5-3 um, but the first lightly doped implant region and the second lightly doped implant region are not contacted with the buried layer 2 in the longitudinal direction.
As a preferred embodiment, the distances from the heavy well region 7 to the first and second lightly doped implant regions 61 and 62 are the same.
The preferred implementation mode is that the implantation element of the heavy well region 7 is boron or boron difluoride, the implantation dosage is 1E 14-8E 14 per square centimeter, the implantation energy is 80-120 KeV, the advancing temperature is 950-1050 ℃, and the advancing time is 30-60 minutes.
In a preferred embodiment, the first to fifth implantation regions are formed of phosphorus or arsenic, the implantation dose is 2e15 to 1e16 per square centimeter, and the implantation energy is 80 to 120kev.
In a preferred embodiment, the implantation elements of the sixth implantation region 86 and the seventh implantation region 87 are boron or boron difluoride, the implantation dose is 1e 15-8 e15cm per square centimeter, and the implantation energy is 40-80 kev.
As a preferred embodiment, wherein the plurality of heavily doped implant regions are implanted using an annealing process or a rapid thermal annealing process;
If an annealing process is used, the annealing temperature is 850-950 ℃ and the annealing time is 30-60 minutes;
if a rapid thermal annealing process is used, the rapid thermal annealing temperature is 950-1050 ℃, and the rapid thermal annealing time is 10-30 seconds.
Example two
Referring to fig. 1-10, the present invention further provides a method for preparing an electrostatic protection device, for preparing an electrostatic protection device as described above, including:
Step S1, as shown in FIG. 1, providing a substrate 1 of a first conductivity type, growing a first thin oxide layer on the upper surface of the substrate 1, defining an NBL region by NBL photoetching, performing ion implantation to form a buried layer 2 of a second conductivity type, performing thermal process propulsion by a furnace tube to enable the buried layer 2 to have a certain depth, and removing the first thin oxide layer on the surface by wet etching;
in one embodiment, the substrate 1 is a P-type substrate with a low doping concentration, and the first thin oxide layer has a growth thickness of Further, the buried layer 2 is an N-type buried layer, the ion implantation element of the N-type buried layer is antimony or arsenic, the implantation energy is 60-100 KeV, the implantation dosage is 5E 14-8E 15 per square centimeter, the implantation angle is 7 degrees, the implantation is performed in a furnace tube, the advancing temperature is 1050-1200 ℃ and the time is 60-120 minutes, so that the junction depth of the buried layer 2 in the substrate 1 is 2-3 mu m.
Step S2, as shown in FIG. 2, an epitaxial layer 3 is grown on the surface, and the epitaxial layer 3 is grown at a high temperature so that the buried layer 2 is upwardly diffused into the epitaxial layer 3;
In one embodiment, the epitaxial layer 3 may be N-type, P-type,
And 2, performing epitaxial growth on the upper surface of the silicon wafer.
Preferably, the epitaxial growth may be performed, but the resistivity of the epitaxial layer 3 should be selected to be high, preferably, the resistivity should be greater than 10Ω×cm, and the thickness is 3-10 μm, and more preferably, the thickness of the epitaxial layer 3 is 3-5 μm.
Further, since the epitaxial layer 3 is grown at a high temperature, the buried layer 2 diffuses upward into the epitaxial layer 3.
Step S3, as shown in fig. 3, performing photolithography and ion implantation of the first well region 41, the third well region 43 and the fifth well region 45 of the first conductivity type on the surface of the epitaxial layer 3 in sequence, performing photolithography and ion implantation of the second well region 42 and the fourth well region 44 of the second conductivity type, and performing high-temperature propulsion so that the first well region to the fifth well region are sequentially adjacent, and the bottoms of the first well region 41 and the fifth well region 45 are simultaneously contacted with the substrate 1 and the buried layer 2 in the epitaxial layer 3, and the bottoms of the second well region 42, the third well region 43 and the fourth well region 44 are contacted with the buried layer 2;
preferably, the first well region 41, the third well region 43 and the fifth well region 45 are P-type well regions, the implanted element is boron, the implantation dose is 2E 12-5E 13cm -2, the implantation energy is 60-100 KeV, and the implantation angle is 7 degrees;
the second well region 42 and the fourth well region 44 are both N-type well regions, the implanted element is phosphorus, the implantation dose is 1E 14-1E 15cm -2, the implantation energy is 80-120 KeV, and the implantation angle is 7 degrees.
After the ion implantation, the ion is pushed in a furnace tube, the pushing temperature is 1000-1150 ℃ and the pushing time is 60-360 minutes, so that the first to fifth well regions are sequentially adjacent, the bottoms of the first well region 41 and the fifth well region 45 are in contact with the upper surface of the substrate 1, the right side edge of the first well region 41 and the left side edge of the fifth well region 45 are in contact with the part of the buried layer 2 diffused into the epitaxial layer 3, the bottoms of the second to fourth well regions are in contact with the buried layer 2, and preferably, the second well region 42 and the fourth well region 44 are connected with two ends of the buried layer 2.
Step S4, as shown in FIG. 4, a field oxide layer (FOX) is grown on the surface of the epitaxial layer 3 by a local oxidation process;
in a specific embodiment, step S4 includes:
Step S41, growing a second thin oxide layer on the surface of the epitaxial layer 3, and then depositing a silicon nitride layer;
Step S42, sequentially performing photoetching, silicon nitride dry etching and photoresist removal, then forming a first field oxide layer 51 above the first well region 41 and the left edge of the second well region 42, sequentially forming a second field oxide layer to a seventh field oxide layer between two adjacent heavily doped injection regions, and forming an eighth field oxide layer 58 above the right edge of the fourth well region 44 and the fifth well region 45;
and S43, removing the residual silicon nitride layer by adopting a wet etching process.
Further, the second thin oxide layer has a thickness of
Further, the thickness of the silicon nitride layer is
Step S5, as shown in FIG. 5, a first lightly doped implantation region 61 and a second lightly doped implantation region 62 of a second conductivity type are formed on the surface of the third well region 43 by photolithography and ion implantation, and then high temperature propulsion is performed;
In one embodiment, the first lightly doped implant region 61 and the second lightly doped implant region 62 are both N-type implant regions, the implant element is phosphorus, the implant dose is 1e 13-1 e14cm -2, the implant energy is 60-100 kev, and the implant angle is 7 degrees. The first lightly doped implantation region 61 and the second lightly doped implantation region 62 are both in the third well region 43 and above the buried layer 2, the device is pushed into a high temperature furnace tube for pushing at 1000-1100 ℃ for 60-120 minutes, so that the N-type implantation region has a certain junction depth and lateral diffusion, preferably the junction depth of the N-type implantation region is 1.5-3 um, and a certain distance is reserved between the N-type implantation region and the buried layer 2 in the longitudinal direction, and the N-type implantation region and the buried layer 2 cannot be connected.
Step S6, as shown in FIG. 6, forming a heavy well region 7 on the surface of the third well region 43 by photolithography and ion implantation, wherein the distances from the heavy well region 7 to the first light doped implantation region 61 and the second light doped implantation region 62 are the same, then performing high-temperature propulsion, and laterally diffusing the heavy well region to the lower part of the field oxide layer after the propulsion;
In one embodiment, the heavy well region 7 is between the first lightly doped implantation region 61 and the second lightly doped implantation region 62, and the distance between the heavy well region 7 and the first lightly doped implantation region 61 is the same as the distance between the heavy well region 7 and the second lightly doped implantation region 62, the implantation element is boron or boron difluoride, the implantation dose is 1e 14-8 e14cm -2, and the implantation energy is 80-120 kev. After the high-temperature furnace tube is pushed in, the heavy well region 7 is laterally diffused to the lower parts of the fourth field oxide layer and the fifth field oxide layer.
Step S7, as shown in FIG. 7, forming first to fifth implantation regions of the second conductivity type on the surface by photolithography and ion implantation, forming a first implantation region 81 in the second well region 42, forming a second implantation region 82 in the first lightly doped implantation region 61, forming a third implantation region 83 in the heavy well region 7, forming a fourth implantation region 84 in the second lightly doped implantation region 62, and forming a fifth implantation region 85 in the fourth well region 44;
In one embodiment, the first to fifth implant regions are all n+ implant regions, the implant element is phosphorus or arsenic, the implant dose is 2E15 to 1E16cm -2, and the implant energy is 80 to 120KeV.
Step S8, as shown in fig. 8, forming a sixth implantation region 86 and a seventh implantation region 87 of the first conductivity type in the third well region 43 by photolithography and ion implantation;
In one embodiment, the sixth implantation region 86 and the seventh implantation region 87 are p+ implantation regions, p+ lithography and p+ ion implantation are performed on the surface, the implantation element is boron or boron difluoride, the implantation dose is 1e 15-8 e15cm -2, the implantation energy is 40-80 kev, and then an annealing process is performed to repair the implantation damage.
Further, the annealing process can use a furnace tube for annealing process or rapid thermal annealing process;
If a furnace tube is used for annealing, the annealing temperature is 850-950 ℃ and the annealing time is 30-60 minutes;
if a rapid thermal annealing process is used, the rapid thermal annealing temperature is 950-1050 ℃, and the rapid thermal annealing time is 10-30 seconds.
Step S9, as shown in FIG. 9, a dielectric layer 9 is deposited on the upper surface of the epitaxial layer 3, and then contact holes corresponding to the first to seventh injection regions are formed through photoetching and etching;
in a specific embodiment, the dielectric layer 9 may be an oxide layer, a boron-phosphorus glass layer, or a composite layer formed by multiple insulating films.
In step S10, as shown in fig. 10, a metal layer is deposited on the upper surface of the dielectric layer 9 and in the contact hole, so that the first grounding metal layer 101 is simultaneously connected to the first injection region 81, the sixth injection region 86, the second injection region 82, the io terminal metal layer 103 is connected to the third injection region 83, and the second grounding metal layer 102 is simultaneously connected to the fourth injection region 84, the seventh injection region 87, and the fifth injection region 85.
Preferably, the metal layer is pure aluminum or aluminum silicon compound, more preferably, is of a three-layer composite structure, and is sequentially of a titanium, titanium nitride and aluminum silicon copper three-layer structure from bottom to top, wherein the thickness of the titanium isTitanium nitride has a thickness ofThe thickness of the aluminum-silicon-copper is 2-4 mu m.
In a specific embodiment, as shown in fig. 11, the IO terminal metal layer 103 is connected to the IO terminal, the IO terminal metal layer 103 is connected to only the third injection region 83 contacting the heavy well region 7, and the first ground terminal metal layer 101 and the second ground terminal metal layer 102 are both connected to the Gnd terminal.
As shown in fig. 12, an equivalent circuit diagram of the electrostatic protection device according to the embodiment of the present invention is shown, wherein the first diode D1 is a reverse diode, and is formed by the third injection region 83 and the heavy well region 7, the second diode D2 is a forward diode, and is formed by the third well region 43 and the heavy well region 7, the first transistor T1 is an NPN transistor, and is formed by the first injection region 81, the third well region 43, the first lightly doped injection region 61, and the second injection region 82 on the left side, the second transistor T2 is an NPN transistor, and is formed by the fifth injection region 85, the third well region 43, the second lightly doped injection region 62, and the fourth injection region 84 on the right side, the third well region 43 is a base region of the first transistor T1, the first resistor R1 is a parasitic resistance of the third well region 43, the third well region 43 is a base region of the second transistor T2, and the second resistor R2 is a parasitic resistance of the third well region 43.
The cathode of the first diode D1 is connected with the IO end, the anode of the first diode D1 is connected with the anode of the second diode D2, the cathode of the second diode D2 is connected with the Gnd end, the bases of the first transistor T1 and the second transistor T2 are both connected to the junction between the anode of the first diode D1 and the anode of the second diode D2, the collectors of the first transistor T1 and the second transistor T2 are connected with the IO end, the emitters of the first transistor T1 and the second transistor T2 are connected with the Gnd end, the first resistor R1 is connected between the base and the emitter of the first transistor T1, and the second resistor R2 is connected between the base and the emitter of the second transistor T2.
When an electrostatic discharge (ESD) event occurs in the device, because the heavy well region 7 is heavily doped, the reverse breakdown voltage of the first diode D1 is lower, so that the junction between the second injection region 82 and the third well region 43 of the first transistor T1 and the junction between the fourth injection region 84 and the third well region 43 of the second transistor T2 can be triggered in a faster auxiliary manner, the electrostatic current passes through the third well region 43 and flows out of the first grounding end metal layer 101 from the sixth injection region 86 and flows out of the second grounding end metal layer 102 from the seventh injection region 87 to the Gnd end, and because the third well region 43 is lightly doped, the voltage difference generated from the third well region 43 to the sixth injection region 86 can easily reach 0.7V, so that the third well region 43 and the first lightly doped injection region 61 are forward-turned on, a bipolar transistor effect can be generated at this time, a large amount of electrostatic current enters the first lightly doped injection region 61 and flows out of the second injection region 82, and a large amount of electrostatic current enters the second injection region 86 and flows out of the second grounding end metal layer 102 to the Gnd end, and the voltage difference generated from the third well region 43 to the sixth injection region 86 is easily reaches 0.7V, and the voltage difference generated from the third well region to the sixth injection region 86 is significantly low in voltage, and the voltage difference is significantly lower than the voltage, and the voltage difference can be seen.
In addition, since the first diode D1 and the second diode D2 are connected in series, they are also NPN transistors in nature, and are composed of the third injection region 83, the heavy well region 7, the third well region 43, and the buried layer 2, when the transistor effect is generated, a large amount of electrostatic current enters from the third injection region 83 at the IO end, passes through the heavy well region 7 and the third well region 43, passes through the buried layer 2, the second well region 42 and the fourth well region 44 at both sides, and finally flows out from the first injection region 81 in the second well region 42 and the fifth injection region 85 in the fourth well region 44, so that the discharge of electrostatic current is also realized.
Therefore, the electrostatic current in the embodiment of the invention can be discharged from the IO end to the second injection region 82 and the fourth injection region 84 at two sides in the third well region 43, and also can be discharged from the bottom buried layer 2 to the first injection region 81 and the fifth injection region 85 at two sides of the device, and both utilize the negative snapback characteristics when the transistor effect is generated, so that the breakdown voltage and the trigger voltage are lower, the protection response is faster, and meanwhile, the on-resistance and the clamping voltage are smaller, and the protection capability of the rear-stage integrated circuit is stronger.
Example two
Referring to fig. 11, in the second embodiment of the present invention, the types of the doped regions are changed based on the first embodiment, all N-types are changed to P-types, all P-types are changed to N-types, the steps of the preparation method are the same as those of the first embodiment, the doping element types and the doping process parameters of the doped regions are adaptively adjusted, and the second embodiment has the same characteristics as the first embodiment and is not described herein.
The electrostatic protection device provided by the invention has the advantages of lower trigger voltage and breakdown voltage, stronger through-current capability, higher electrostatic discharge capability, higher stability and reliability, and can not increase the area of the electrostatic protection device.
By way of illustration and the accompanying drawings, there is shown exemplary examples of specific structures of the embodiments and other variations may be made based on the spirit of the invention. While the above invention is directed to the presently preferred embodiments, such disclosure is not intended to be limiting.
Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalents and alternatives falling within the scope of the claims are intended to be embraced therein.

Claims (15)

1.一种静电保护器件，提供一第一导电类型的衬底，以及位于所述衬底上的外延层，其特征在于，包括：1. An electrostatic protection device, comprising: a substrate of a first conductivity type; and an epitaxial layer located on the substrate; 第二导电类型的埋层，形成于所述衬底的预定区域，且所述埋层向上扩散至所述外延层中；A buried layer of a second conductivity type is formed in a predetermined area of the substrate, and the buried layer diffuses upward into the epitaxial layer; 至少五个阱区，依次邻接形成于所述外延层中，包括第一导电类型的第一阱区、第三阱区以及第五阱区，所述第一阱区和所述第五阱区的底部与所述衬底的上表面、所述外延层中的所述埋层同时相接触；第二导电类型的第二阱区和第四阱区，所述第二阱区、所述第三阱区以及所述第四阱区的底部与所述埋层相接触；At least five well regions are sequentially and adjacently formed in the epitaxial layer, including a first well region, a third well region, and a fifth well region of a first conductivity type, wherein the bottoms of the first well region and the fifth well region are in contact with the upper surface of the substrate and the buried layer in the epitaxial layer; and a second well region and a fourth well region of a second conductivity type, wherein the bottoms of the second well region, the third well region, and the fourth well region are in contact with the buried layer. 至少两个第二导电类型的轻掺杂注入区，形成于所述第三阱区内，包括第一轻掺杂注入区和第二轻掺杂注入区；At least two lightly doped implant regions of the second conductivity type are formed in the third well region, including a first lightly doped implant region and a second lightly doped implant region; 第一导电类型的重阱区，形成于所述第一轻掺杂注入区和所述第二轻掺杂注入区之间；A heavy well region of the first conductivity type is formed between the first lightly doped implant region and the second lightly doped implant region; 多个重掺杂注入区，包括第二导电类型的第一至第五注入区，第一注入区形成于所述第二阱区内，第二注入区形成于所述第一轻掺杂注入区内，第三注入区形成于所述重阱区内，第四注入区形成于所述第二轻掺杂注入区内，第五注入区形成于所述第四阱区内；第一导电类型的第六注入区和第七注入区，形成于所述第三阱区内；a plurality of heavily doped implant regions, including first to fifth implant regions of the second conductivity type, wherein the first implant region is formed in the second well region, the second implant region is formed in the first lightly doped implant region, the third implant region is formed in the heavily well region, the fourth implant region is formed in the second lightly doped implant region, and the fifth implant region is formed in the fourth well region; a sixth implant region and a seventh implant region of the first conductivity type are formed in the third well region; 介质层，形成于所述外延层的上方，所述介质层中设有对应第一至第七注入区的接触孔；a dielectric layer formed above the epitaxial layer, wherein the dielectric layer is provided with contact holes corresponding to the first to seventh injection regions; 金属层，包括第一接地端金属层，分别连接所述第一注入区、所述第六注入区、所述第二注入区；IO端金属层，连接所述第三注入区；第二接地端金属层，分别连接所述第四注入区、所述第七注入区、所述第五注入区。The metal layer includes a first grounding metal layer, which is respectively connected to the first injection area, the sixth injection area, and the second injection area; an IO end metal layer, which is connected to the third injection area; and a second grounding metal layer, which is respectively connected to the fourth injection area, the seventh injection area, and the fifth injection area. 2.根据权利要求1所述的静电保护器件，其特征在于，所述第一阱区的上方和所述第二阱区的左侧边缘设有第一场氧化层；第二至第七场氧化层分别依次设置于相邻的两个所述重掺杂注入区之间；所述第四阱区的右侧边缘和所述第五阱区的上方设有第八场氧化层。2. The electrostatic protection device according to claim 1 is characterized in that a first field oxide layer is provided above the first well region and on the left edge of the second well region; the second to seventh field oxide layers are respectively and sequentially arranged between two adjacent heavily doped injection regions; and an eighth field oxide layer is provided on the right edge of the fourth well region and above the fifth well region. 3.根据权利要求1所述的静电保护器件，其特征在于，所述外延层的电阻率大于10Ω*cm，厚度为3～10μm；3. The electrostatic protection device according to claim 1, wherein the resistivity of the epitaxial layer is greater than 10Ω*cm and the thickness is 3 to 10μm; 所述外延层为第一导电类型或第二导电类型；The epitaxial layer is of the first conductivity type or the second conductivity type; 当第一导电类型为N型时，第二导电类型为P型；以及When the first conductivity type is N-type, the second conductivity type is P-type; and 当第一导电类型为P型时，第二导电类型为N型。When the first conductivity type is P type, the second conductivity type is N type. 4.根据权利要求1所述的静电保护器件，其特征在于，所述重阱区至所述第一轻掺杂注入区、所述第二轻掺杂注入区的距离相同。4 . The electrostatic protection device according to claim 1 , wherein the distances from the heavy well region to the first lightly doped injection region and the second lightly doped injection region are the same. 5.一种静电保护器件的制备方法，其特征在于，用于制备如权利要求1-4任意一项所述的静电保护器件，包括：5. A method for preparing an electrostatic protection device, characterized in that it is used to prepare the electrostatic protection device according to any one of claims 1 to 4, comprising: 步骤S1，提供一第一导电类型的衬底，于所述衬底上生长一第一薄氧化层，然后通过光刻、离子注入，再进行热过程推进，形成第二导电类型的埋层，再将表面第一薄氧化层用湿法腐蚀的方式去除；Step S1, providing a substrate of a first conductivity type, growing a first thin oxide layer on the substrate, then forming a buried layer of a second conductivity type by photolithography, ion implantation, and thermal process advancement, and then removing the first thin oxide layer on the surface by wet etching; 步骤S2，于上述表面生长外延层，所述外延层采用高温生长使得所述埋层向上扩散至所述外延层中；Step S2, growing an epitaxial layer on the surface, wherein the epitaxial layer is grown at a high temperature so that the buried layer diffuses upward into the epitaxial layer; 步骤S3，于所述外延层表面依次进行第一导电类型的第一阱区、第三阱区以及第五阱区的光刻、离子注入，第二导电类型的第二阱区和第四阱区的光刻、离子注入，然后进行高温推进，使得第一至第五阱区依次邻接，且所述第一阱区和所述第五阱区的底部与所述衬底、所述外延层中的所述埋层同时相接触，所述第二阱区、所述第三阱区以及所述第四阱区的底部与所述埋层相接触；Step S3, sequentially performing photolithography and ion implantation on the surface of the epitaxial layer to form a first well region, a third well region, and a fifth well region of the first conductivity type, and photolithography and ion implantation on the second well region and the fourth well region of the second conductivity type, and then performing high-temperature advancement, so that the first to fifth well regions are sequentially adjacent, and the bottoms of the first well region and the fifth well region are in contact with the substrate and the buried layer in the epitaxial layer at the same time, and the bottoms of the second well region, the third well region, and the fourth well region are in contact with the buried layer; 步骤S4，于所述外延层表面通过局部氧化工艺，生长场氧化层；Step S4, growing a field oxide layer on the surface of the epitaxial layer through a local oxidation process; 步骤S5，于所述第三阱区表面通过光刻、离子注入形成第二导电类型的第一轻掺杂注入区和第二轻掺杂注入区，然后进行高温推进；Step S5, forming a first lightly doped implantation region and a second lightly doped implantation region of a second conductivity type on the surface of the third well region by photolithography and ion implantation, and then performing high temperature driving; 步骤S6，于所述第三阱区表面通过光刻、离子注入形成重阱区，所述重阱区至所述第一轻掺杂注入区和所述第二轻掺杂注入区的距离相同，然后进行高温推进，推进后所述重阱区横向扩散至所述场氧化层的下方；Step S6, forming a heavy well region on the surface of the third well region by photolithography and ion implantation, wherein the heavy well region is at the same distance from the first lightly doped implant region and the second lightly doped implant region, and then performing high-temperature implantation, so that the heavy well region laterally diffuses to below the field oxide layer after implantation; 步骤S7，在上述表面通过光刻、离子注入形成第二导电类型的第一至第五注入区，于所述第二阱区内形成第一注入区，于所述第一轻掺杂注入区内形成第二注入区，于所述重阱区内形成第三注入区，于所述第二轻掺杂注入区内形成第四注入区，于所述第四阱区内形成第五注入区；Step S7, forming first to fifth implantation regions of the second conductivity type on the surface by photolithography and ion implantation, forming a first implantation region in the second well region, forming a second implantation region in the first lightly doped implantation region, forming a third implantation region in the heavily well region, forming a fourth implantation region in the second lightly doped implantation region, and forming a fifth implantation region in the fourth well region; 步骤S8，于所述第三阱区内通过光刻、离子注入形成第一导电类型的第六注入区和第七注入区；Step S8, forming a sixth implantation region and a seventh implantation region of the first conductivity type in the third well region by photolithography and ion implantation; 步骤S9，于所述外延层的上表面淀积介质层，然后通过光刻、刻蚀形成对应第一至第七注入区的接触孔；Step S9, depositing a dielectric layer on the upper surface of the epitaxial layer, and then forming contact holes corresponding to the first to seventh implantation regions by photolithography and etching; 步骤S10，于所述介质层上表面及所述接触孔中进行金属层的沉积，以使第一接地端金属层连接所述第一注入区、所述第六注入区、所述第二注入区，IO端金属层连接所述第三注入区；第二接地端金属层连接所述第四注入区、所述第七注入区、所述第五注入区。Step S10, depositing a metal layer on the upper surface of the dielectric layer and the contact hole, so that the first grounding metal layer is connected to the first injection area, the sixth injection area, and the second injection area, and the IO end metal layer is connected to the third injection area; the second grounding metal layer is connected to the fourth injection area, the seventh injection area, and the fifth injection area. 6.根据权利要求5所述的静电保护器件的制备方法，其特征在于，所述第一薄氧化层的生长厚度为 6. The method for preparing an electrostatic protection device according to claim 5, wherein the thickness of the first thin oxide layer is 7.根据权利要求5所述的静电保护器件的制备方法，其特征在于，所述步骤S1中，所述埋层的离子注入元素为锑或者砷，注入能量为60～100KeV，注入剂量5E14～8E15每平方厘米，注入角度为7度；炉管推进温度为1050℃～1200℃，时间60～120分钟，以使所述埋层在所述衬底中的结深为2～3μm。7. The method for preparing an electrostatic protection device according to claim 5 is characterized in that in step S1, the ion implantation element of the buried layer is antimony or arsenic, the implantation energy is 60-100 KeV, the implantation dose is 5E14-8E15 per square centimeter, and the implantation angle is 7 degrees; the furnace tube advancement temperature is 1050°C-1200°C, and the time is 60-120 minutes, so that the junction depth of the buried layer in the substrate is 2-3 μm. 8.根据权利要求5所述的静电保护器件的制备方法，其特征在于，所述步骤S3中，所述第一阱区、所述第三阱区以及所述第五阱区的注入元素为硼，注入剂量为2E12～5E13每平方厘米，注入能量为60～100KeV，注入角度为7度；8. The method for preparing an electrostatic protection device according to claim 5, wherein in step S3, the implanted element in the first well region, the third well region, and the fifth well region is boron, the implantation dose is 2E12-5E13 per square centimeter, the implantation energy is 60-100 KeV, and the implantation angle is 7 degrees; 所述第二阱区和所述第四阱区的注入元素为磷，注入剂量为1E14～1E15每平方厘米，注入能量为80～120KeV，注入角度为7度；The implantation element of the second well region and the fourth well region is phosphorus, the implantation dose is 1E14-1E15 per square centimeter, the implantation energy is 80-120 KeV, and the implantation angle is 7 degrees; 然后进行高温推进，推进温度为1000～1150℃，推进时间60～360分钟。Then, high-temperature advancement is carried out, with the advancement temperature being 1000-1150° C. and the advancement time being 60-360 minutes. 9.根据权利要求5所述的静电保护器件的制备方法，其特征在于，所述步骤S5中，所述第一轻掺杂注入区和所述第二轻掺杂注入区的注入元素为磷，注入剂量为1E13～1E14每平方厘米，注入能量为60～100KeV，注入角度为7度；推进温度为1000～1100℃，推进时间60～120分钟，以使所述第一轻掺杂注入区和所述第二轻掺杂注入区的结深为1.5～3um，但在纵向上与所述埋层不接触。9. The method for preparing an electrostatic protection device according to claim 5 is characterized in that in step S5, the injection element of the first lightly doped injection region and the second lightly doped injection region is phosphorus, the injection dose is 1E13~1E14 per square centimeter, the injection energy is 60~100KeV, and the injection angle is 7 degrees; the advancement temperature is 1000~1100℃, and the advancement time is 60~120 minutes, so that the junction depth of the first lightly doped injection region and the second lightly doped injection region is 1.5~3um, but does not contact the buried layer in the vertical direction. 10.根据权利要求5所述的静电保护器件的制备方法，其特征在于，所述步骤S6中，所述重阱区的注入元素为硼或二氟化硼，注入剂量为1E14～8E14每平方厘米，注入能量为80～120KeV；推进温度950～1050℃，推进时间30～60分钟。10. The method for preparing an electrostatic protection device according to claim 5, characterized in that in step S6, the implanted element in the heavy well region is boron or boron difluoride, the implantation dose is 1E14 to 8E14 per square centimeter, the implantation energy is 80 to 120 KeV, the implantation temperature is 950 to 1050° C., and the implantation time is 30 to 60 minutes. 11.根据权利要求5所述的静电保护器件的制备方法，其特征在于，所述步骤S7中，所述第一至第五注入区的注入元素为磷或砷，注入剂量为2E15～1E16每平方厘米，注入能量为80～120KeV；11. The method for preparing an electrostatic protection device according to claim 5, wherein in step S7, the implanted element in the first to fifth implantation regions is phosphorus or arsenic, the implantation dose is 2E15-1E16 per square centimeter, and the implantation energy is 80-120 KeV; 所述第六注入区和所述第七注入区的注入元素为硼或二氟化硼，注入剂量为1E15～8E15cm每平方厘米，注入能量为40～80KeV。The implantation element of the sixth implantation region and the seventh implantation region is boron or boron difluoride, the implantation dosage is 1E15-8E15 cm2, and the implantation energy is 40-80 KeV. 12.根据权利要求5所述的静电保护器件的制备方法，其特征在于，所述步骤S7中，所述第一至第七注入区注入后使用退火工艺或快速热退火工艺；12. The method for preparing an electrostatic protection device according to claim 5, wherein in step S7, an annealing process or a rapid thermal annealing process is used after the first to seventh implantation regions are implanted; 若使用退火工艺，退火温度为850℃～950℃，退火时间为30～60分钟；If the annealing process is used, the annealing temperature is 850℃～950℃ and the annealing time is 30～60 minutes; 若使用快速热退火工艺，快速热退火温度为950～1050℃，快速热退火时间为10～30秒。If a rapid thermal annealing process is used, the rapid thermal annealing temperature is 950-1050° C., and the rapid thermal annealing time is 10-30 seconds. 13.根据权利要求5所述的静电保护器件的制备方法，其特征在于，所述步骤S4包括：13. The method for preparing an electrostatic protection device according to claim 5, wherein step S4 comprises: 步骤S41，于所述外延层表面生长一第二薄氧化层，再淀积氮化硅层；Step S41, growing a second thin oxide layer on the surface of the epitaxial layer, and then depositing a silicon nitride layer; 步骤S42，依次通过光刻、氮化硅干法刻蚀、去除光刻胶，然后于所述第一阱区的上方和所述第二阱区的左侧边缘形成第一场氧化层，于相邻的两个所述重掺杂注入区之间分别依次形成第二至第七场氧化层，于所述第四阱区的右侧边缘和所述第五阱区的上方形成第八场氧化层；Step S42, sequentially performing photolithography and silicon nitride dry etching, removing the photoresist, and then forming a first field oxide layer above the first well region and on the left edge of the second well region, forming second to seventh field oxide layers respectively between two adjacent heavily doped implanted regions, and forming an eighth field oxide layer on the right edge of the fourth well region and above the fifth well region; 步骤S43，采用湿法腐蚀工艺去除残留的所述氮化硅层。Step S43: removing the remaining silicon nitride layer by a wet etching process. 14.根据权利要求13所述的静电保护器件的制备方法，其特征在于，所述第二薄氧化层的厚度为 14. The method for preparing an electrostatic protection device according to claim 13, wherein the thickness of the second thin oxide layer is 15.根据权利要求13所述的静电保护器件的制备方法，其特征在于，所述氮化硅层的厚度为 15. The method for preparing an electrostatic protection device according to claim 13, wherein the thickness of the silicon nitride layer is
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