CN116192355B

CN116192355B - MIPI transmitter and clock calibration method thereof

Info

Publication number: CN116192355B
Application number: CN202211085133.4A
Authority: CN
Inventors: 谢成鑫; 王倩; 徐成阳
Original assignee: Lianyun Technology Hangzhou Co ltd
Current assignee: Lianyun Technology Hangzhou Co ltd
Priority date: 2022-09-06
Filing date: 2022-09-06
Publication date: 2024-02-06
Anticipated expiration: 2042-09-06
Also published as: CN116192355A

Abstract

The application discloses an MIPI transmitter and a clock calibration method thereof. The MIPI transmitter includes a clock channel and a data channel. The clock calibration method comprises the following steps: performing phase comparison on a first sampling clock signal generated by the clock channel and a second sampling clock signal generated by the data channel to obtain an initial phase relationship; and phase shifting the second sampling clock signal according to the initial phase relationship so that the phase difference between the first sampling clock signal and the second sampling clock signal is less than a reference value. The clock calibration method corrects the clock offset of the data channel relative to the clock channel and corrects the clock offset among a plurality of data channels, thereby ensuring the accuracy of data sampling.

Description

MIPI transmitter and clock calibration method thereof

Technical Field

The invention relates to the technical field of data communication, in particular to an MIPI transmitter and a clock calibration method thereof.

Background

A high-speed interface for communication interconnection is required between the different modules of the mobile device. The MIPI (Mobile Industry Processor Interface) alliance is established for standardization of high-speed interfaces. Based on MIPI protocol, interfaces inside the mobile device such as cameras, display screen interfaces, interface circuits of radio frequency/baseband and the like can be standardized, so that the complexity of the design of the mobile device is reduced and the design flexibility is improved. The logic layer of MIPI is a special protocol for different purposes such as camera, display screen, mobile communication, storage, and the physical layer comprises D-PHY, M-PHY, and C-PHY. The D-PHY is part of the MIPI protocol and describes a synchronous, high-speed, low-power physical layer. The D-PHY includes, for example, definitions of DSI (serial display interface) and CSI (serial camera interface) on the physical layer.

According to the MIPI D-PHY protocol, a transmitter in a MIPI circuit comprises a plurality of Data lanes (Data lanes) and one Clock Lane (Clock Lane). The plurality of data channels are independent of each other and share a clock channel. The clock signals received from the clock channels by the plurality of data channels and the clock signals output to the digital section have clock offsets (skew). Clock skew is a different delay caused by different paths of the clock signal, which may lead to sampling errors in the digital part as well as data skew in different data channels, resulting in serious data errors.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide an MIPI transmitter and a clock calibration method thereof, in which a calibration module is used to correct clock offsets of data channels with respect to a clock channel, and to correct clock offsets between a plurality of data channels, thereby ensuring accuracy of data sampling.

According to an embodiment of the present invention, there is provided a clock calibration method of an MIPI transmitter, the MIPI transmitter including a clock channel and a data channel, the clock calibration method including:

performing phase comparison on a first sampling clock signal generated by the clock channel and a second sampling clock signal generated by the data channel to obtain an initial phase relationship; and

and according to the initial phase relation, the second sampling clock signal is phase-shifted so that the phase difference between the first sampling clock signal and the second sampling clock signal is smaller than a reference value.

Preferably, the performing of the phase comparison includes: sampling the first sampling clock signal by adopting the second sampling clock signal; and determining an initial phase relationship of the second sampling clock signal and the second sampling clock signal based on the sampled values.

Preferably, the performing of the phase comparison includes: sampling the second sampling clock signal by adopting the first sampling clock signal; and determining an initial phase relationship of the second sampling clock signal and the second sampling clock signal based on the sampled values.

Preferably, the initial phase relationship comprises the second sampling clock signal leading the first sampling clock signal or the second sampling clock signal lagging the first sampling clock signal.

Preferably, the phase shifting the second sampling clock signal includes: and performing phase shift on the second sampling clock signal at least once according to the initial phase relation.

Preferably, the phase shifting of the second sampling clock signal includes phase shifting the reference value.

Preferably, the number of phase shifts of the second sampling clock signal corresponds to the initial phase relationship.

Preferably, the phase shifting of the second sampling clock signal is triggered by a trigger edge of an enable signal.

Preferably, the phase shifting of the second sampling clock signal includes: extending the high level stage or the low level stage by the reference value in the nearest clock period after the trigger edge, thereby extending the reference value by a single clock period; and recovering the value of the clock cycle in the clock cycle after the nearest neighbor clock cycle.

Preferably, it is determined that the phase difference of the first sampling clock signal and the second sampling clock signal is smaller than a reference value according to the inversion of the phase relationship.

Preferably, in the case where the initial phase relationship is that the second sampling clock signal leads the first sampling clock signal, if the phase relationship is flipped an odd number of times, it is determined that the phase difference of the first sampling clock signal and the second sampling clock signal is smaller than a reference value.

Preferably, in the case where the initial phase relationship is that the second sampling clock signal lags behind the first sampling clock signal, if the phase relationship is inverted even times, it is determined that the phase difference of the first sampling clock signal and the second sampling clock signal is smaller than a reference value.

Preferably, after clock alignment, the start position of the clock period of the second sampling clock signal is aligned with the start position of the clock period of the first sampling clock signal.

Preferably, the clock calibration method further comprises: and carrying out additional phase shifting on the second sampling clock signal, and aligning the middle position of the clock period of the first sampling clock signal at the starting position of the clock period of the second sampling clock signal after clock alignment.

Preferably, the MIPI transmitter further comprises an additional data channel that generates a third sampling clock signal, and the clock calibration method further comprises: and phase shifting the third sampling clock signal so that the phase difference between the first sampling clock signal and the third sampling clock signal is smaller than a reference value.

Preferably, the first sampling clock signal and the second sampling clock signal are clock signals generated based on frequency division of an input clock signal.

Preferably, the reference value is smaller than a clock period of the input clock signal.

According to an embodiment of the present invention, there is provided an MIPI transmitter including:

a digital section for generating a serial data signal based on the first sampling clock signal, and converting an input digital signal into serial data based on the second sampling clock signal; and

an analog portion including a clock path that converts the input serial data signal into a differential output clock signal and a data path that converts serial data into a differential output data signal,

wherein the clock channel and the data channel generate the first sampling clock signal and the second sampling clock signal, respectively,

the digital section includes: a calibration module that generates an enable signal according to a phase relationship of the first sampling clock signal and the second sampling clock signal;

the data channel includes: and the phase shifting module shifts the phase of the second sampling clock signal according to the triggering edge of the enabling signal so that the phase difference between the first sampling clock signal and the second sampling clock signal is smaller than a reference value.

Preferably, the calibration module samples the first sampling clock signal by using the second sampling clock signal; and determining an initial phase relationship of the first sampling clock signal and the second sampling clock signal based on the sampled values.

Preferably, the calibration module samples the first sampling clock signal by using the second sampling clock signal; and determining whether the phase relation of the first sampling clock signal and the second sampling clock signal after phase shifting is inverted according to the sampling value.

Preferably, the phase shift module shifts the second sampling clock signal at least once.

Preferably, the phase shifting of the second sampling clock signal includes:

extending the high level stage or the low level stage by the reference value in the nearest clock period after the trigger edge, thereby extending the reference value by a single clock period; and

and recovering the value of the clock cycle in the clock cycles after the nearest neighbor clock cycle.

Preferably, it is determined that the phase difference between the first sampling clock signal and the second sampling clock signal is smaller than a reference value according to the inversion of the phase relationship after the phase shift.

Preferably, in the case where the initial phase relationship is that the second sampling clock signal leads the first sampling clock signal, if the phase relationship after the phase shift is inverted an odd number of times, it is determined that the phase difference of the first sampling clock signal and the second sampling clock signal is smaller than a reference value.

Preferably, in the case where the initial phase relationship is that the second sampling clock signal lags behind the first sampling clock signal, if the phase relationship after the phase shift is inverted even times, it is determined that the phase difference of the first sampling clock signal and the second sampling clock signal is smaller than a reference value.

According to an embodiment of the present invention, the MIPI transmitter calibrates the clock signal CLKB in the digital portion of the MIPI transmitter. To this end, the digital section also includes a calibration module. The calibration module receives the clock signals CLKa and CLKb, compares phases of the clock signals CLKa and CLKb, and generates an enable signal EN for controlling the operation of the phase shifting module according to the comparison result. If the phase difference of the clock signals CLKa and CLKb does not match the reference value, the enable signal EN provides a trigger edge, and the phase shifting module shifts the phase of the clock signal CLKb to change the phase relationship of the clock signals CLKa and CLKb. In the case where the number of phase shifts of the clock signal CLKb corresponds to the initial phase difference of the clock signal CLKa and the clock signal CLKb, the phase differences of the clock signals CLKa and CLKb may finally conform to the reference value. The MIPI transmitter uses the calibration module to correct the clock offset of the data channel relative to the clock channel, thereby ensuring the accuracy of data sampling.

In a preferred embodiment, the MIPI transmitter may comprise a plurality of data lanes and the plurality of data lanes share a clock lane, wherein the plurality of data lanes each align a respective clock signal CLKb with a clock signal CLKa provided by the shared clock lane. Thus, the MIPI transmitter can correct clock skew between a plurality of data channels, thereby ensuring accuracy of data sampling.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 shows a schematic block diagram of an MIPI transmitter in accordance with an embodiment of the invention.

Fig. 2 shows a flowchart of a clock calibration method of an MIPI transmitter in accordance with an embodiment of the invention.

Fig. 3 shows a timing diagram of a clock calibration method of an MIPI transmitter in accordance with an embodiment of the invention.

Fig. 4 shows a simulated waveform diagram of a one shot of an MIPI transmitter in a clock calibration method.

Fig. 5a and 5b show simulated waveforms of the MIPI transmitter before and after clock calibration, respectively.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown.

The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to". In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

The following describes in further detail the embodiments of the present invention with reference to the drawings and examples.

Fig. 1 shows a schematic block diagram of an MIPI transmitter in accordance with an embodiment of the invention. In the present embodiment, the MIPI transmitter 100 is, for example, a high speed transmitter (high speed transmitter, abbreviated as HSTX) including a digital portion 110 and an analog portion 120.

The digital part 110 of the MIPI transmitter 100 receives the input digital signal Di, and the clock signals CLKa and CLKb, and provides the serial data signal dataack and the serial data DATAs. The analog part 120 of the MIPI transmitter 100 performs serial-to-parallel conversion on the serial data signal DATAck based on the clock signal CLKa to generate differential output clock signals CLKp and CLKm, and performs serial-to-parallel conversion on the serial data DATAs based on the clock signal CLKb to generate differential output data signals DATAp and DATAm.

Further, the analog portion 120 of the MIPI transmitter 100 includes a clock channel 121 and a data channel 122. For clarity, only one clock channel and one data channel are exemplified below.

Clock path 121 includes parallel-to-serial conversion module 1211, serial-to-parallel conversion module 1212, phase shift module 1213, and divider 1214. The clock path 121 receives differential input clock signals CLK1 and CLK2, and sends to the serial-to-parallel conversion module 1212 via the parallel-to-serial conversion module 1211 for generating differential output clock signals CLKp and CLKm. Further, the clock signal CLK1 is phase-shifted by the phase shift module 1213, and is divided by the divider 1214 to obtain the clock signal CLKa. The analog portion 120 of the MIPI transmitter 100 provides the clock signal CLKa to the digital portion 110 of the MIPI transmitter 100.

The data path 122 includes a parallel-to-serial conversion module 1221, a serial-to-parallel conversion module 1222, a phase shift module 1223, and a frequency divider 1224. The data path 122 receives the differential input clock signals CLK3 and CLK4, and sends to the serial-to-parallel conversion module 1222 through the parallel-to-serial conversion module 1221 for generating differential output data signals DATAp and DATAm. Further, the clock signal CLK3 is phase-shifted by the phase shift module 1223 and divided by the frequency divider 1224 to obtain the clock signal CLKb. The analog portion 120 of the MIPI transmitter 100 provides the clock signal CLKb to the digital portion 110 of the MIPI transmitter 100.

The digital portion 110 of the MIPI transmitter 100 includes a controller 111 and a state machine 112, a clock module 113, and a sampling module 114.

The clock signal CLKa received by the digital section 110 is used not only for controlling the controller 111 but also for controlling the state machine 112. The controller 111 receives the input digital signal Di and sends data to the sampling module 114 under the control of the clock signal CLKa. The clock module 113 converts the clock signal CLKa into a serial data signal dataack. The sampling module 114 receives data transmitted from the controller 111 under the control of the clock signal CLKb, thereby sampling the data to generate serial data DATAs.

The clock signals CLK1 and CLK2 received by the analog portion 120 of the MIPI transmitter 100 described above are clock signals that are inverted with respect to each other, the clock signals CLK3 and CLK4 are clock signals that are inverted with respect to each other, and the phase difference between the clock signal CLK1 and the clock signal CLK3 is 90 degrees. The clock signal CLKa generated by the analog portion 120 is a clock signal generated by phase-shifting and frequency-dividing based on the clock signal CLK1, and the clock signal CLKb of the analog portion 120 is a clock signal generated by phase-shifting and frequency-dividing based on the clock signal CLK 3.

The clock signals CLK1 to CLK4 received by the analog part 120 of the MIPI transmitter 100 are clock signals generated by an external phase locked loop circuit, and thus, the clock signals CLK1 to CLK4 have an accurate phase difference from each other. However, after the clock tree synthesis (Clock Tree Synthesis, abbreviated as CTS) of the analog portion 120, the digital portion 110 of the MIPI transmitter 100 has a clock offset (skew) between the clock signals CLKa and CLKb due to the different paths generated by the clock signals CLKa and CLKb and the different delays of the clock signals CLKa and CLKb received from the analog portion 120.

In the prior art MIPI transmitter, the clock offsets of clock signals CLKa and CLKb are not checked. However, clock skew may cause not only sampling errors of the digital section 110, but also data skew of different data channels, thereby generating serious data errors.

The MIPI transmitter 100 in accordance with embodiments of the invention differs from prior art MIPI transmitters in that the phase between the sampling clock CLKb of the digital-to-analog interface of data channel 122 relative to the clock signal CLKa of clock channel 121 is calibrated in the digital portion 110 of MIPI transmitter 100. To this end, the digital section 110 also includes a calibration module 115. The calibration module 115 receives the clock signals CLKa and CLKb, compares phases of the clock signals CLKa and CLKb, and generates an enable signal EN for controlling the operation of the phase shift module 1223 according to the comparison result. If the phase difference of the clock signals CLKa and CLKb does not match the reference value, the enable signal EN provides a trigger edge, and the phase shift module 1223 shifts the phase of the clock signal CLKb to change the phase relationship of the clock signals CLKa and CLKb. In the case where the number of phase shifts of the clock signal CLKb corresponds to the initial phase difference of the clock signal CLKa and the clock signal CLKb, the phase differences of the clock signals CLKa and CLKb may finally conform to the reference value.

According to the MIPI transmitter 100 of an embodiment of the invention, the analog portion 120 is described as including a clock path 121 and a data path 122. In an alternative embodiment, as described above, the MIPI transmitter 100 may include a plurality of data lanes and the plurality of data lanes share a clock lane, wherein the plurality of data lanes correspond to a respective one of the calibration modules, aligning the respective clock signal CLKb to the middle of the clock signal CLKa provided by the shared clock lane. Thus, the MIPI transmitter 100 may correct clock skew between multiple data lanes to ensure that the sampling clock signal CLKb of a data lane is at an optimal sampling window and to compensate for relative skew between different data lane clock signals CLKb.

Fig. 2 shows a flowchart of a clock calibration method of an MIPI transmitter in accordance with an embodiment of the invention. In this embodiment, the phase shift module 1223 in the MIPI transmitter 100 and the calibration module 115 together perform the steps of the clock calibration method. For example, in an initialization phase of the MIPI circuit, the MIPI transmitter 100 performs steps S01 to S07 described in detail below.

In step S02, the clock signals CLKa and CLKb are phase-compared.

In this step, the calibration module 115 samples the clock signal CLKa provided by the clock channel 121 using the clock signal CLKb provided by the data channel 122, and compares the phases of the clock signals CLKa and CLKb according to the sampled values.

In the present embodiment, the clock periods of the clock signals CLKa and CLKb are identical to each other and are in a predetermined proportional relationship with the clock periods of the clock signals CLK1 and CLK 3.

The clock signal CLKa is a signal generated by dividing the input clock signal CLK1, and the clock signal CLKb is a signal generated by dividing the input clock signal CLK 3. The clock signals CLKa and CLKb are used for serial-to-parallel conversion of the serial data signal DATAck and the serial data DATAs, respectively. If the serial data signal DATAck and the serial data DATAs are 8-bit data, the serial-to-parallel conversion module 1212 in the clock path 121 converts the serial data signal of the 8-bit data into a 1-bit differential output clock signal, and the serial-to-parallel conversion module 1222 in the data path 122 converts the serial data of the 8-bit data into a 1-bit differential output data signal. Thus, the frequency division ratio of the frequency divider 1214 in the clock path 121 and the frequency divider 1224 in the data path 122 is 4 to support serial-to-parallel conversion of 8-bit data into a 2-bit differential signal.

Referring to fig. 3, clock signals CLK1 and CLK3 are input clock signals of the clock path 121 and the data path 122, respectively, and clock signals CLKa and CLKb are sampling clock signals generated by the clock path 121 and the data path 122, respectively. The clock periods of the clock signals CLK1 and CLK3 are both T1, and are identical to each other by a phase difference of 90 degrees. The clock periods of the clock signals CLKa and CLKb are both T2, and the clock periods are identical to each other and have a phase shift. Since the frequency division ratio of the clock path 121 and the data path 122 is 4, the clock period T2 of the clock signals CLKa and CLKb is 4 times the clock period T1 of the clock signals CLK1 and CLK3, that is, t2=4×t1.

In the present embodiment, the clock signal CLKa provided by the clock channel 121 is sampled at the edge of the clock signal CLKb by the clock signal CLKb provided by the data channel 122, and the initial phase relationship of the clock signals CLKa and CLKb is obtained from the sampled values. In an alternative embodiment, based on the same principle, the clock signal CLKa provided by the clock channel 121 may be used, the clock signal CLKb provided by the data channel 122 is sampled at the edges of the clock signal CLKa, and the initial phase relationship of the clock signals CLKa and CLKb is obtained from the sampled values.

In this embodiment, the clock signal CLKa is sampled at the rising edge of the clock signal CLKb. If the sampled value of clock signal CLKa is 0, it indicates that clock signal CLKb leads clock signal CLKa. If the sampled value of the clock signal CLKa is 1, it means that the clock signal CLKb lags behind the clock signal CLKa. In an alternative embodiment, the clock signal CLKa is sampled at the falling edge of the clock signal CLKb. If the sample value is 1, it means that the clock signal CLKb leads the clock signal CLKa. If the sample value is 0, this indicates that the clock signal CLKb lags behind the clock signal CLKa.

Since the edges of the clock signal CLKa and CLKb are difficult to align exactly as the edges of one clock signal are sampled at the edges of the other clock signal, it can be determined from the sampling result of this step that the initial phase relationship, i.e., the clock signal CLKb leads or lags the clock signal CLKa without calibration.

In step S03, the clock signal CLKb is phase-shifted to change the phase relationship of the clock signals CLKa and CLKb.

In this step, the clock calibration module 115 generates an enable signal EN. The phase shift module 1223 shifts the phase of the clock signal CLKb in response to the trigger edge of the enable signal EN, for example, by extending the high level phase or the low level phase one clock cycle after the trigger edge to shift the phase of the clock signal CLK3 backward. For each trigger edge, the phase of the clock signal CLK3 is shifted back by T1/2 and, correspondingly, the phase of the clock signal CLKB is shifted back by T1/2.

In step S04, the type of initial phase relationship of the clock signals CLKa and CLKb is determined.

In this embodiment, the amount of phase shift required for the calibration of the clock signal CLKb is different for different initial phase relationships due to the nature of the phase shift module 1223 to shift the phase of the clock signal CLKb back.

If the clock signal CLKb leads the clock signal CLKa, the amount of phase shift required for the calibration of the clock signal CLKb is smaller than the clock period T2 of the clock signal CLKb, and accordingly, the phase relationship is flipped once or other odd number of times (the phase relationship is flipped once later as an example), and thus, step S05 is further performed. If the clock signal CLKb lags behind the clock signal CLKa, the phase shift amount required for the calibration of the clock signal CLKb is greater than T2 and less than 2×t2, and accordingly, the phase relationship is flipped twice or other even number of times (the phase relationship is flipped twice in the following example), and thus, step S06 is further performed.

In step S05, it is determined whether the phase relationship of the clock signals CLKa and CLKb is inverted once.

If the phase relationship of the clock signals CLKa and CLKb is not flipped, it is determined that the phase difference of the clock signals CLKa and CLKb does not conform to the reference value, and steps S03 to S05 are performed back, and the phase shift of the clock signal CLKb is repeated one or more times until the phase relationship of the clock signals CLKa and CLKb is flipped one time.

If the phase relationship of the clock signals CLKa and CLKb is flipped once, it is determined that the phase difference of the clock signals CLKa and CLKb matches the reference value, and the step S07 is continued to be executed, thereby ending the clock calibration method.

Referring to fig. 3, clock signals clkb_10, clkb_11, and clkb_12 represent an initial clock signal, a clock signal after the first phase shift, and a clock signal after the fifth phase shift, respectively.

As an initial clock signal, the clock signal clkb_10 leads the clock signal CLKa by less than T1/2. A sample value of 0 is detected on the rising edge of clock signal clkb_10. The amount of phase shift delta phi=t1/2=t2/8 of the backward shift of the clock signal CLKb due to each pulse of the enable signal EN. Therefore, the phase shift is only required once, and the clock signal clkb_11 after the first phase shift is obtained. A sample value of 1 is detected on the rising edge of clock signal clkb_11. Thus, from the value inversion of the sample values, it is possible to detect that the phase relationship of the clock signals CLKa and CLKb is inverted once. At this time, the phase difference between the clock signal clkb_11 and the clock signal CLKa is smaller than T1/2, and the rising edges of both are substantially aligned.

Preferably, the clock signal clkb_11 is further phase-shifted four times, and the total phase shift ΔΦ=2×t1=t2/2, to obtain the clock signal clkb_12 after the fifth phase shift. At this time, the phase difference between the clock signal clkb_12 and the clock signal CLKa is smaller than T2/2, and the rising edge of the clock signal clkb_12 is substantially aligned with the falling edge of the clock signal CLKa.

In step S06, it is determined whether the phase relationship of the clock signals CLKa and CLKb is inverted twice.

If the phase relationship of the clock signals CLKa and CLKb is not flipped, it is determined that the phase difference of the clock signals CLKa and CLKb does not conform to the reference value, and steps S03 to S05 are performed back, and the phase shift of the clock signal CLKb is repeated one or more times until the phase relationship of the clock signals CLKa and CLKb is flipped twice.

If the phase relationship of the clock signals CLKa and CLKb is flipped twice, it is determined that the phase difference of the clock signals CLKa and CLKb matches the reference value, and the step S07 is continued to be executed, thereby ending the clock calibration method.

Referring to fig. 3, the clock signals clkb_20, clkb_21, clkb_22, and clkb_23 represent an initial clock signal, a clock signal after the third phase shift, a clock signal after the seventh phase shift, and a clock signal after the eleventh phase shift, respectively.

As an initial clock signal, the clock signal clkb_20 lags behind the clock signal CLKa by an amount greater than T1/2 and less than T1. A sample value of 1 is detected on the rising edge of clock signal clkb_20. The amount of phase shift delta phi=t1/2=t2/8 of the backward shift of the clock signal CLKb due to each pulse of the enable signal EN. Thus, after shifting the phase three times, the clock signal clkb_21 after the phase shift for the third time is obtained. A sample value of 0 is detected on the rising edge of clock signal clkb_21. Thus, a first inversion of the phase relationship of the clock signals CLKa and CLKb is detected from the value inversion of the sample values. After shifting the phase seven times, the seventh phase-shifted clock signal clkb_22 is obtained. A sample value of 1 is detected on the rising edge of clock signal clkb_21. Thus, a second inversion of the phase relationship of the clock signals CLKa and CLKb can be detected based on the value inversion of the sample values. At this time, the phase difference between the clock signal clkb_22 and the clock signal CLKa is smaller than T1/2, and the rising edges of both are substantially aligned.

Preferably, the clock signal clkb_22 is further phase-shifted four times, and the total phase shift ΔΦ=2×t1=t2/2, to obtain an eleventh phase-shifted clock signal clkb_23. At this time, the phase difference between the clock signal clkb_23 and the clock signal CLKa is smaller than T2/2, and the rising edge of the clock signal clkb_23 is substantially aligned with the falling edge of the clock signal CLKa.

According to the clock calibration method of the embodiment of the present invention, the analog part 120 is described as including one clock channel 121 and one data channel 122. In an alternative embodiment, as described above, the MIPI transmitter 100 may include a plurality of data channels and the plurality of data channels share a clock channel, wherein the plurality of data channels respectively perform the above-described clock calibration method to align sampling clock signals of the plurality of data channels with sampling clock signals of the shared clock channel respectively. Therefore, the clock calibration method can correct clock offset among a plurality of data channels, thereby ensuring the accuracy of data sampling.

Fig. 4 shows a simulated waveform diagram of a one shot of an MIPI transmitter in a clock calibration method. In the figure, CLKa represents the clock signal provided by the clock channel, CLKb1 and CLKb2 represent the clock signals provided by the two data channels, respectively, and EN1 and EN2 represent the enable signals provided by the clock calibration modules in the two data channels, respectively.

As shown in fig. 4, clock signals CLKb1 and CLKb2 lead clock signal CLKa. The phase shifting blocks in both data channels change the duty cycle of the clock signals CLKb1 and CLKb2 in the nearest neighbor clock period T3 after the trigger edge, for example, extend the high level phase of the nearest neighbor clock period T3 by Δt=t1/2=t2/8. Then, the duty cycle of the clock signals CLKb1 and CLKb2 is recovered at the next neighbor time period T2 after the trigger edge. Thus, each trigger edge of the enable signals EN1 and EN2 may obtain a phase shift amount ΔΦ=t1/2=t2/8 of the backward shift of the clock signals CLKb1 and CLKb 2.

In the above embodiment, it is described that the phase shift module shifts back by an amount equal to T1/2 for each trigger edge. However, the amount of phase shift of the phase shift module depends on the circuit characteristics. By modifying the circuit design of the phase shifting module, the phase shifting quantity with higher precision can be obtained, thereby improving the clock calibration precision. In alternative embodiments, the amount of phase shift that the phase shift module shifts back for each trigger edge may be equal to any of T1, T1/2, T1/4, T1/8, T1/16, etc.

Fig. 5a and 5b show simulated waveforms of the MIPI transmitter before and after clock calibration, respectively. In the figure, CLKa represents the clock signal provided by the clock channel and CLKb1 and CLKb2 represent the clock signals provided by the two data channels, respectively.

As shown in fig. 5a, clock signals CLKb1 and CLKb2 lead clock signal CLKa. Since the clock calibration is not performed, the phase difference Δt between the clock signals CLKb1 and CLKb2 may be greater than T1, resulting in a large clock offset between the differential output signals of the serial data of the two data channels output to the differential line after serial-to-parallel conversion.

As shown in fig. 5b, the clock signals CLKb1 and CLKb2 are clock-calibrated to align the positions of 1/2 clock cycles of the clock signal CLKa, respectively, the phase difference between the clock signals CLKb1 and CLKa is 2×1< Δta < (2+1/2) ×t1, and the phase difference between the clock signals CLKb2 and CLKa is 2×1< Δtb < (2+1/2) ×t1. Between performing clock calibration, the phase difference Δt < T1/2 between the clock signal CLKb1 and the clock signal CLKb2 is equal to each other, and thus clock offset between differential output signals output to the differential lines after serial-to-parallel conversion of serial data of two data channels is substantially eliminated.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A clock calibration method of an MIPI transmitter, the MIPI transmitter comprising a clock channel and a data channel, the clock calibration method comprising:

phase shifting the second sampling clock signal according to the initial phase relationship such that the phase difference between the first sampling clock signal and the second sampling clock signal is less than a reference value,

wherein in the case where the initial phase relationship is that the second sampling clock signal leads the first sampling clock signal, if the phase relationship is flipped an odd number of times, it is determined that the phase difference of the first sampling clock signal and the second sampling clock signal is smaller than a reference value.

2. The clock calibration method of claim 1, wherein the performing a phase comparison comprises:

sampling the first sampling clock signal by adopting the second sampling clock signal; and

and determining the initial phase relation between the first sampling clock signal and the second sampling clock signal according to the sampling value.

3. The clock calibration method of claim 1, wherein the performing a phase comparison comprises:

sampling the second sampling clock signal by adopting the first sampling clock signal; and

4. A clock calibration method according to claim 2 or 3, wherein the initial phase relationship comprises the second sampling clock signal leading the first sampling clock signal or the second sampling clock signal lagging the first sampling clock signal.

5. The clock calibration method of claim 4, wherein the phase shifting the second sampling clock signal comprises: and performing phase shift on the second sampling clock signal at least once according to the initial phase relation.

6. The clock calibration method of claim 5, wherein the phase shifting of the second sampling clock signal comprises phase shifting the reference value.

7. The clock calibration method of claim 5, wherein the number of phase shifts of the second sampling clock signal corresponds to the initial phase relationship.

8. The clock calibration method of claim 5, wherein the phase shifting of the second sampling clock signal is triggered by a trigger edge of an enable signal.

9. The clock calibration method of claim 8, wherein the phase shifting of the second sampling clock signal comprises:

10. The clock calibration method according to claim 4, wherein it is determined that the phase difference of the first sampling clock signal and the second sampling clock signal is smaller than a reference value according to the inversion of the phase relationship.

11. The clock calibration method according to claim 10, wherein in the case where the initial phase relationship is that the second sampling clock signal lags behind the first sampling clock signal, if the phase relationship is inverted even times, it is determined that a phase difference of the first sampling clock signal and the second sampling clock signal is smaller than a reference value.

12. The clock calibration method of claim 1, wherein a start position of a clock cycle of the second sampling clock signal is aligned with a start position of a clock cycle of the first sampling clock signal after clock alignment.

13. The clock calibration method of claim 1, further comprising: and carrying out additional phase shifting on the second sampling clock signal, and aligning the middle position of the clock period of the first sampling clock signal at the starting position of the clock period of the second sampling clock signal after clock alignment.

14. The clock calibration method of claim 1, wherein the MIPI transmitter further comprises an additional data channel that generates a third sampling clock signal, the clock calibration method further comprising: and phase shifting the third sampling clock signal so that the phase difference between the first sampling clock signal and the third sampling clock signal is smaller than a reference value.

15. The clock calibration method of claim 1, wherein the first sampling clock signal and the second sampling clock signal are clock signals generated based on frequency division of an input clock signal.

16. The clock calibration method of claim 15, wherein the reference value is less than a clock period of the input clock signal.

17. A MIPI transmitter comprising:

the data channel includes: a phase shift module for shifting the phase of the second sampling clock signal according to the triggering edge of the enabling signal so that the phase difference between the first sampling clock signal and the second sampling clock signal is smaller than a reference value,

and under the condition that the initial phase relation is that the second sampling clock signal leads the first sampling clock signal, if the phase relation after phase shifting is inverted for odd times, the calibration module determines that the phase difference between the first sampling clock signal and the second sampling clock signal is smaller than a reference value.

18. The MIPI transmitter of claim 17, wherein the calibration module samples the first sampling clock signal with the second sampling clock signal; and determining an initial phase relationship of the first sampling clock signal and the second sampling clock signal based on the sampled values.

19. The MIPI transmitter of claim 18, wherein the calibration module samples the first sampling clock signal with the second sampling clock signal; and determining whether the phase relation of the first sampling clock signal and the second sampling clock signal after phase shifting is inverted according to the sampling value.

20. The MIPI transmitter of claim 17, wherein the phase shifting module phase shifts the second sampling clock signal at least once.

21. The MIPI transmitter of claim 17, wherein the phase shifting of the second sampling clock signal comprises phase shifting back by the reference value.

22. The MIPI transmitter of claim 18, wherein the number of phase shifts of the second sampling clock signal corresponds to the initial phase relationship.

23. The MIPI transmitter of claim 17, wherein the phase shifting of the second sampling clock signal comprises:

24. The MIPI transmitter of claim 19, wherein the phase difference of the first sampling clock signal and the second sampling clock signal is determined to be less than a reference value based on the phase-shifted phase relationship flip.

25. The MIPI transmitter of claim 24, wherein if the phase relationship after phase shifting is inverted even times in the event that the initial phase relationship is that the second sampling clock signal lags the first sampling clock signal, then determining that the phase difference of the first and second sampling clock signals is less than a reference value.