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CN116205178B - FPGA with built-in interconnection module containing heterogeneous selector - Google Patents

FPGA with built-in interconnection module containing heterogeneous selector Download PDF

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Publication number
CN116205178B
CN116205178B CN202211726136.1A CN202211726136A CN116205178B CN 116205178 B CN116205178 B CN 116205178B CN 202211726136 A CN202211726136 A CN 202211726136A CN 116205178 B CN116205178 B CN 116205178B
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interconnection
selection circuit
input
circuit
output
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CN116205178A (en
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单悦尔
徐彦峰
陈波寅
徐玉婷
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Wuxi Zhongwei Yixin Co Ltd
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Wuxi Zhongwei Yixin Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The application discloses an FPGA with built-in interconnection modules comprising heterogeneous selectors, which relates to the FPGA technology, wherein the interconnection modules in the FPGA are not all internally provided with symmetrical selectors, but are provided with at least one built-in heterogeneous selector of the interconnection modules, and the heterogeneous selector comprises a first selection circuit and a second selection circuit, so that when an input signal is connected to interconnection input points of the interconnection modules and is fanned out to a plurality of interconnection output points, part of conduction paths are realized by the first selection circuit, part of conduction paths are realized by the second selection circuit, and the second selection circuit is not connected with a pull-up circuit, so that load requirements are hardly generated, and more fanout quantity can be realized by using a pull-down circuit with smaller driving capability, thereby reducing the occupied area and power consumption of the pull-down circuit and reducing the waste of the area and the power consumption.

Description

FPGA with built-in interconnection module containing heterogeneous selector
Technical Field
The invention relates to the field of FPGA, in particular to an FPGA with built-in interconnection modules comprising heterogeneous selectors.
Background
The FPGA (Field Programmable GATE ARRAY ) internally comprises a large number of resource modules such as CLB, BRAM, DSP, IOB, interconnection modules INT are distributed around the resource modules, and the input and output of each resource module are connected with other resource modules through the corresponding interconnection modules INT, so that a wiring framework of which the plane is unfolded to the whole FPGA is formed.
IN the most commonly used wiring architecture of the FPGA at present, please refer to fig. 1, each interconnection module INT has a rectangular structure and includes interconnection input points e_in, s_in, w_in, n_in IN four directions of southwest and northwest, so that signal input IN each direction can be obtained, and each interconnection module INT further includes interconnection output points e_out, s_out, w_out, n_out IN four directions of southwest and northwest, so that signals can be output IN each direction. Inside the interconnect module INT, the required connections between the different interconnect input points and the interconnect output points are achieved via the switch box.
Each interconnection output point is connected with an interconnection input point IN each direction, signals received by one interconnection input point are fanned OUT to the interconnection output point through code flow control selection, as shown IN fig. 1, which shows a schematic diagram that interconnection input points e_in, s_in, w_in and n_in IN four directions are connected with an interconnection output point e_out through a first selection circuit and a buffer circuit U0, and the first selection circuit can fann OUT signals of one interconnection input point to e_out according to four received control signals C0, C1, C2 and C3, so as to achieve a design goal. In addition, the output end of the first selection circuit connected with each interconnection output point of the interconnection module INT is also connected with the pull-up circuit PU, so that even if any interconnection input point connected with the first selection circuit is not selected, default output is still ensured, and the phenomenon that the circuit floats, namely, the y0 point is not 0 and is not 1, can be avoided.
And when the input signal is about to drive 0, the drive pull-down circuit connected with the input signal pulls down the internal conduction path of the interconnection module INT to 0, so that the signal fan-out is realized. However, as described above, a pull-up circuit is provided at each interconnection output point of the interconnection module INT, and the pull-up circuit is used as a load for driving the pull-down circuit, so that in order to ensure that the signal 0 is transmitted to the interconnection output point in time, the driving capability of the input signal connection for driving the pull-down circuit needs to be large enough to avoid being influenced by the pull-up circuit. In actual operation, the input signal can be fanned out to a plurality of interconnection output points of each interconnection module INT when being input to the interconnection input points of each interconnection module INT, so that the driving capability of the driving pull-down circuit connected with the input signal needs to be ensured to meet the high-load requirement in the multi-fanout process during design. Therefore, in order to ensure normal driving, the driving capability of the driving pull-down circuit often needs to be designed redundantly according to the upper limit value of the fan-out number, which not only results in a larger circuit area, but also results in small area waste and power consumption waste when the fan-out number is not used in practical use.
Disclosure of Invention
The present inventors have proposed an FPGA with built-in interconnect modules including heterogeneous selectors, which is directed against the above-mentioned problems and technical needs, and the technical scheme of the present application is as follows:
An FPGA with built-in interconnection modules comprising heterogeneous selectors, wherein at least one interconnection module internally comprises built-in heterogeneous selectors to realize interconnection between interconnection input points and interconnection output points, the interconnection output points in the interconnection module are connected with a first selection circuit in the heterogeneous selectors, and the at least one interconnection output point is also connected with a second selection circuit in the heterogeneous selectors;
The interconnection input points connected with the input signals form a plurality of conduction paths with a plurality of interconnection output points through the heterogeneous selector, the input signals are grounded through the driving pull-down circuit, at least one conduction path is controlled by the second code stream section through the second selection circuit, and the rest conduction paths are controlled by the first code stream section through the first selection circuit;
the input end of the first selection circuit is connected with an interconnection input point, the output end of the first selection circuit is connected with a pull-up power supply through a pull-up circuit, and the output end of the first selection circuit is also connected with a corresponding interconnection output point through a buffer circuit;
The input end of the second selection circuit is connected with the interconnection input point, and the output end of the second selection circuit is connected with the corresponding interconnection output point through the buffer circuit.
The further technical scheme is that the number of conducting paths which are formed by the interconnection module and used for simultaneously fanning out input signals to a plurality of interconnection output points does not exceed a number threshold N1 through the first selection circuit.
The driving capability of the pull-down circuit connected with the input signal is designed according to the load requirement of the pull-up circuit in N1 conducting paths realized by the first selection circuit.
The further technical scheme is that an input signal is connected to an interconnection input point of an interconnection module, and the number of conducting paths for transmitting the input signal, which are realized by a first selection circuit in the interconnection module, does not exceed a number threshold N1;
or the input signals are simultaneously connected to the interconnection input points of the interconnection modules, and the input signals are simultaneously fanned out to the interconnection output points of the interconnection modules through the plurality of conduction paths formed in the interconnection modules, so that the total number of the conduction paths for transmitting the input signals, which are realized in the interconnection modules connected with the input signals through the first selection circuit, does not exceed a number threshold N1.
The further technical scheme is that the first code stream segment received by the first selection circuit with the number of the included input ends within the range of (2 P-1,2P) comprises P code stream bits, and the second code stream segment received by the second selection circuit with the number of the included input ends comprises Q code stream bits;
Among N2 conductive paths formed through the interconnection module for simultaneously fanning out the input signal to a plurality of interconnection output points, wherein N1 conductive paths are realized via the first selection circuit and the remaining N2-N1 conductive paths are realized via the second selection circuit.
A further technical solution is that the method for forming a plurality of conducting paths for simultaneously fanning out an input signal to a plurality of interconnected output points comprises:
the first selection circuit in the interconnection module is preferably used for realizing a plurality of conducting paths for simultaneously fanning out the input signals, and when the number of the conducting paths realized by the first selection circuit reaches N1, the second selection circuit in the interconnection module is used for realizing the rest conducting paths.
The structure of the interconnection module comprises a first selection circuit, a second selection circuit, a pull-up power supply, a connecting module and a connecting module, wherein the first selection circuit and the second selection circuit are connected at one interconnection output point at the same time, the output end of the first selection circuit and the output end of the second selection circuit are both connected with the input end of the buffer circuit, the output end of the buffer circuit is connected with the interconnection output point, the output end of the first selection circuit is also connected with the pull-up power supply through the pull-up circuit, part of interconnection input points of the interconnection module are connected with all the input ends of the first selection circuit, and the other part of interconnection input points of the interconnection module are connected with all the input ends of the second selection circuit.
The further technical scheme is that a first selection circuit connected with the same interconnection output point is controlled by a first code stream section to conduct one path between one input end and one output end to form a conducting path realized by the first selection circuit, and a second selection circuit is controlled by a second code stream section to control the paths between all the input ends and the output ends to be non-conducting;
or the second selection circuit connected with the same interconnection output point is controlled by the second code stream section to conduct one path between one of the input ends and the output end to form a conducting path realized by the second selection circuit, and the first selection circuit is controlled by the first code stream section to control the paths between all the input ends and the output end to be non-conducting.
The further technical scheme is that all interconnection output points of the interconnection module are respectively and simultaneously connected with a first selection circuit and a second selection circuit;
Or part of interconnection output points of the interconnection module are respectively and simultaneously connected with the first selection circuit and the second selection circuit, and the rest of interconnection output points are respectively and only connected with the first selection circuit.
The second selection circuit is constructed based on one or more tri-state buffers, the input end of each tri-state buffer is connected with one interconnection input point in the interconnection module, the output end of the tri-state buffer is connected with the input end of the buffer circuit, and the second code stream section of the second selection circuit comprises the code stream bits of each tri-state buffer;
the first code stream section and the second code stream section are both contained in the control code stream of the FPGA, and when the conducting paths realized by the first selection circuit and/or the second selection circuit are different, the total number of code stream bits contained in the control code stream of the FPGA is unchanged.
The application has the beneficial technical effects that the FPGA internally provided with the interconnection module comprising the heterogeneous selector is disclosed, the interconnection module in the FPGA is not internally provided with all the symmetrical selectors, but is provided with at least one interconnection module internally provided with the heterogeneous selector, the heterogeneous selector comprises a first selection circuit and a second selection circuit, when one input signal is connected to the interconnection input point of the interconnection module and is fanned out to a plurality of interconnection output points, part of the conduction paths are realized by the first selection circuit, part of the conduction paths are realized by the second selection circuit, and the second selection circuit is not connected with the pull-up circuit, so that the load requirement is hardly generated, more fanout quantity can be realized by using the drive pull-down circuit with smaller driving capability, the area occupied by the drive pull-down circuit and the power consumption are reduced, and the waste of the area and the power consumption can be reduced.
Drawings
Fig. 1 is a schematic diagram of a connection between an interconnection input point and an interconnection output point by a built-in symmetrical selector of a conventional interconnection module INT.
Fig. 2 is a schematic diagram of a prior art interconnect module INT based on the architecture of fig. 1 fanning out an input signal IN to individual interconnect output points.
Fig. 3 is a schematic diagram of fanning out an input signal IN to various interconnect output points using a heterogeneous selector built IN an interconnect module INT IN an FPGA of the present application, IN one embodiment of the present application.
Fig. 4 is a schematic diagram of fanning out an input signal IN to an interconnect output point of a plurality of interconnect modules IN an embodiment of the application.
Detailed Description
The following describes the embodiments of the present application further with reference to the drawings.
The application discloses an FPGA with built-IN interconnection modules comprising heterogeneous selectors, wherein the structure of all interconnection modules INT IN a conventional FPGA is recorded IN the background technology, the interconnection modules INT are internally provided with symmetrical selectors for realizing interconnection between interconnection input points and interconnection output points, the symmetrical selectors comprise a plurality of first selection circuits, the connection schematic diagram of each first selection circuit and the interconnection input points and the interconnection output points of the interconnection modules INT is shown IN figure 1, each input end of each first selection circuit is respectively connected with each interconnection input point of the interconnection module INT, four input ends of each first selection circuit are respectively connected with interconnection input points E_IN, S_IN, W_IN and N_IN IN four directions of the interconnection module INT IN figure 1, the output end of each first selection circuit is connected with the input end of a buffer circuit U0, the output end of the buffer circuit U0 is connected with one interconnection output point of the interconnection module INT, and the output end of the buffer circuit U0 is connected with the interconnection output point E_OUT of the interconnection module INT IN figure 1. The output end of the first selection circuit is also connected with a pull-up power supply through a pull-up circuit PU.
IN order to avoid the difference between the paths connected to different interconnection input points, the first selection circuit IN the conventional universal interconnection module INT generally adopts a symmetrical selection structure, fig. 1 shows a typical structure of the first selection circuit including four input ends, the interconnection input point e_in is connected to one end of the switching tube M3 through the switching tube M1, the interconnection input point s_in is connected to one end of the switching tube M3 through the switching tube M2, and the other end of the switching tube M3 is connected to the output end of the first selection circuit. The interconnection input point W_IN is connected with one end of the switching tube M6 through the switching tube M4, the interconnection input point N_IN is connected with one end of the switching tube M6 through the switching tube M5, and the other end of the switching tube M6 is connected with the output end of the first selection circuit. The switching tube M1 and the switching tube M4 are controlled by a control signal C0, the switching tube M2 and the switching tube M5 are controlled by a control signal C1, the switching tube M3 is controlled by a control signal C2, and the switching tube M6 is controlled by a control signal C3. When the first selection circuit has more input ends, those skilled in the art can expand to obtain the circuit structure in the same way, and the application is not repeated.
Thus, the first selection circuit forms a symmetrical selection structure, so that when the control code generated after layout wiring is used to control four control signals of the first selection circuit, only two code stream bits are actually needed, as shown in fig. 1, the first code stream bit generates the control signal C0 and the inversion generates the control signal C1, and the second code stream bit generates the control signal C2 and the inversion generates the control signal C3.
Therefore, the symmetrical selection structure of the first selection circuit is beneficial, when the number of the input ends of the first selection circuit exceeds 2 P-1 and does not exceed 2 P, the first code stream section received by the first selection circuit only needs to contain P code stream bits, one conduction path can be selected from paths formed by the first selection circuit to serve as a conduction path, and signals of interconnection input points connected with the conduction path are fanned out to interconnection output points connected with the conduction path.
In the application, at least one interconnection module INT in the FPGA does not adopt the general structure, the improved interconnection module INT does not use a symmetrical selector, but uses a heterogeneous selector to realize interconnection between interconnection input points and interconnection output points, and the heterogeneous selector comprises a second selection circuit in addition to a first selection circuit compared with the general symmetrical selector. The interconnection output points in the interconnection module are connected with the first selection circuit in the heterogeneous selector, and at least one interconnection output point is also connected with the second selection circuit in the heterogeneous selector. The first selection circuit in the heterogeneous selector has the same structure as the first selection circuit in the universal INT, the input end of the first selection circuit is connected with an interconnection input point, the output end of the first selection circuit is connected with a pull-up power supply through a pull-up circuit, the output end of the first selection circuit is also connected with a corresponding interconnection output point through a buffer circuit U0, and the first selection circuit is controlled by a code stream bit of a first code stream segment Ctrl1 to control the on-off of each path formed inside. The input end of a second selection circuit in the improved interconnection module INT is connected with the interconnection input point of the interconnection module INT, the output end of the second selection circuit is connected with the corresponding interconnection output point through a buffer circuit, and the second selection circuit is controlled by the code stream bit of the second code stream segment Ctrl2 to control the on-off of each path formed inside.
In one embodiment, the second selection circuit is added to all interconnection modules INT inside the FPGA to build in the heterogeneous selector. Or only part of interconnection modules INT in the FPGA are internally provided with a second selection circuit and built-in heterogeneous selectors, and the rest of interconnection modules INT still adopt a conventional structure to build in symmetrical selectors.
Based on the built-IN symmetrical selector of the conventional interconnect module INT, when one input signal IN is connected to the interconnect input point w_in of the interconnect module INT and needs to be simultaneously fanned OUT to three interconnect output points n_out, e_out, s_out, the circuit configuration is as shown IN fig. 2. The interconnection input point w_in is connected with the input signal IN, the input signal IN is grounded through the driving pull-down circuit PD, the interconnection input point w_in connected with the input signal IN forms a plurality of conducting paths with a plurality of interconnection output points n_out, e_out and s_out through a built-IN symmetrical selector, and the three conducting paths are all realized by a first code stream section through a first selection circuit connected with the three interconnection output points. For example, IN fig. 2, the first selection circuit connected to the interconnection output point n_out is controlled by a conduction path between the interconnection input point w_in and the interconnection output point n_out of the first code stream segment Ctrl (1), the first selection circuit connected to the interconnection output point e_out is controlled by a conduction path between the interconnection input point w_in and the interconnection output point e_out of the first code stream segment Ctrl (2), and the first selection circuit connected to the interconnection output point s_out is controlled by a conduction path between the interconnection input point w_in and the interconnection output point s_out of the first code stream segment Ctrl (3). Based on this structure, when the input signal IN is 0, the driving pull-down circuit PD to which the input signal IN is connected needs to pull down all the conduction paths to 0 IN a set time, and the driving capability of the driving pull-down circuit PD to which the input signal IN is connected needs to at least satisfy the load requirements of the pull-up circuits IN all the conduction paths. IN addition, IN practical application, the number of the conductive paths connected to the actual interconnection input point w_in varies under the influence of the layout and wiring, so the driving capability of the driving pull-down circuit PD is generally designed according to the upper limit of the conductive paths IN design, for example, IN the structure of fig. 2, the interconnection input point w_in can form four conductive paths with the four interconnection output points respectively at most, so IN the design stage, the driving capability of the driving pull-down circuit PD connected to the input signal IN is generally designed according to the load requirement of the pull-up circuit IN all four conductive paths, so as to ensure that the signal can be accurately transmitted. However, IN the use stage, the interconnection input point w_in may form two conducting paths with only two interconnection output points, so that the driving capability of the driving pull-down circuit PD is actually redundant, which occupies too much unnecessary area and causes additional power consumption waste. In addition, the application only takes a single INT module as an example, which comprises four interconnection output points, the number of the interconnection input points and the interconnection output points of the INT structure in the actual FPGA is more, and the number of the INT modules is also more, so that the waste of the area and the power consumption is considerable.
In the application, based on the built-in heterogeneous selector of the improved interconnection module INT, a plurality of conducting paths are formed between the interconnection input points connected with the input signals and a plurality of interconnection output points through the heterogeneous selector, at least one conducting path is controlled by a second code stream section Ctrl2 to be realized through a second selection circuit, and the rest conducting paths are controlled by a first code stream section Ctrl1 to be realized through a first selection circuit. Then in the example of fig. 2, a schematic diagram of the connection of the implementation of the heterogeneous selector built-in based on the modified interconnect module INT in the FPGA of the application is shown in fig. 3. As can be seen from a comparison of fig. 2 and 3, in the same case not all the conduction paths are realized by the first selection circuit, but some of them are realized by the second selection circuit. For example, IN fig. 3, a first selection circuit connected to the interconnection output point n_out is controlled by a conduction path between the interconnection input point w_in and the interconnection output point n_out of the first code stream segment Ctrl (1), a first selection circuit connected to the interconnection output point e_out is controlled by a conduction path between the interconnection input point w_in and the interconnection output point e_out of the first code stream segment Ctrl (2), and a second selection circuit connected to the interconnection output point s_out is controlled by a conduction path between the interconnection input point w_in and the interconnection output point s_out of the second code stream segment Ctrl 2.
In order to avoid the circuit floating phenomenon at the interconnection output point, when the interconnection output point is connected to the second selection circuit in the interconnection module INT, the original first selection circuit is not canceled, but the second selection circuit is added on the basis of the original first selection circuit, and fig. 3 takes the interconnection output point s_out as an example, and the first selection circuit and the second selection circuit are simultaneously connected. The structure of connecting the first selection circuit and the second selection circuit at the interconnection output point simultaneously comprises that the output end of the first selection circuit and the output end of the second selection circuit are both connected with the input end of a buffer circuit U0, the output end of the buffer circuit U0 is connected with the interconnection output point, the output end of the first selection circuit is also connected with a pull-up power supply through a pull-up circuit, part of interconnection input points of the interconnection module INT are connected with all the input ends of the first selection circuit, and the other part of interconnection input points are connected with all the input ends of the second selection circuit. With this structure, the phenomenon of floating of the circuit can be avoided, that is, the situation that the y0 point at the s_out in fig. 3 is not 0 nor 1, and at the same time, there is no pull-up circuit in the conduction path realized by the second selection circuit, and the input ends of the first selection circuit and the second selection circuit are respectively connected to the interconnection input point.
The first selection circuit connected with the same interconnection output point is controlled by the first code stream section to conduct one path between one of the input ends and the output end to form a conducting path realized by the first selection circuit, and the second selection circuit is controlled by the second code stream section to control the paths between all the input ends and the output end to be non-conducting. Or the second selection circuit connected with the same interconnection output point is controlled by the second code stream section to conduct one path between one of the input ends and the output end to form a conducting path realized by the second selection circuit, and the first selection circuit is controlled by the first code stream section to control the paths between all the input ends and the output end to be non-conducting. That is, the first selection circuit and the second selection circuit connected to the same interconnection output point form only one conduction path in total.
Therefore, taking fig. 3 as an example, based on this structure, the conduction path realized by the second selection circuit is not connected to the pull-up circuit, and almost no load demand occurs. Therefore, when the input signal IN is 0, the driving pull-down circuit PD connected to the input signal IN needs to pull down all the conduction paths to 0 within the set time, and the driving capability of the driving pull-down circuit PD connected to the input signal IN does not need to meet the load requirements of the pull-up circuits IN all the conduction paths, but only needs to meet the load requirements of the pull-up circuits IN the conduction paths implemented by the first selection circuit, that is, only needs to meet the load requirements of the pull-up circuits IN part of the conduction paths. For example, in comparison with fig. 2 and fig. 3, the driving capability of the pull-down circuit PD is required to satisfy the load requirements of the pull-up circuits in the three conduction paths in fig. 2, whereas the driving capability of the pull-down circuit PD is required to satisfy the load requirements of the pull-up circuits in the two conduction paths in fig. 3. Thereby reducing the need for driving capability of the driving pull-down circuit PD, so that the waste of area and power consumption due to the necessity of using the driving pull-down circuit PD of large driving capability can be reduced.
In the interconnection module INT of a built-in heterogeneous selector, all interconnection output points may be connected to the first selection circuit and the second selection circuit at the same time, respectively. Or only part of interconnection output points of the interconnection module are respectively and simultaneously connected with the first selection circuit and the second selection circuit, and the rest of interconnection output points are respectively and only connected with the first selection circuit. For example, in fig. 3, the interconnection output point s_out is connected to both the first selection circuit and the second selection circuit, but the interconnection output point n_out is connected to only the first selection circuit, and the interconnection output point e_out is also connected to only the first selection circuit.
In one embodiment, the second selection circuit is built based on one or more tri-state buffers, each tri-state buffer having an input connected to one of the interconnect input points in the interconnect module and an output connected to the input of the buffer circuit U0. As shown in fig. 3, for example, when the second selection circuit has more tri-state buffers, the input terminals of the tri-state buffers are connected to different interconnection input points, and the output terminals of the tri-state buffers are connected to the input terminal of the buffer circuit U0.
The second code stream segment Ctrl2 of the second selection circuit comprises the code stream bits of the respective tri-state buffers, and thus the second code stream segment received by the second selection circuit comprising Q inputs comprises Q code stream bits, for example, IN fig. 3, only one input of the second selection circuit is used for connecting w_in, and the second code stream segment Ctrl2 thereof comprises one code stream bit.
The second selection circuit is based on a tri-state buffer implementation, which occupies a slightly larger area than the first selection circuit, and which requires significantly less code stream bits than the second selection circuit when the same number of inputs are included. Therefore, in practical application, a plurality of second selection circuits are not added in the interconnection module INT of the FPGA, but only a limited number of second selection circuits are added, so that the area and the power consumption caused by driving the pull-down circuit PD are reduced, and at the same time, the additional area and the power consumption caused by the second selection circuits are reduced. In the structural design stage, it is determined which interconnection modules INT need to be internally provided with a second selection circuit and which interconnection output points need to be added, and when the FPGA is manufactured, the structure is fixed and cannot be changed. Once the structure and the number of the second selection circuits are fixed, the number of the code stream bits required by the second code stream sections required by the second selection circuits is determined, and the first code stream sections and the second code stream sections are both contained in the control code stream of the FPGA, so that the length of the control code stream generated after the layout and the wiring of the FPGA is fixed, and when the conducting paths implemented by the first selection circuits and/or the second selection circuits are different, the total number of the code stream bits contained in the control code stream of the FPGA is unchanged, that is, no matter how many second selection circuits are finally required to be implemented, the total length of the control code stream is unchanged, and only the content of each code stream section is affected.
As described above, based on the FPGA of the structure of the present application, the requirement for the driving capability of the driving pull-down circuit PD can be reduced by implementing the partial conduction path with the second selection circuit, but the driving capability of the driving pull-down circuit PD still needs to be predetermined at the structural design stage. The driving capability of the driving pull-down circuit to which the input signal is connected may be designed in advance in accordance with the load requirements of the pull-up circuit in the N1 conductive paths realized via the first selection circuit. Then, in the layout wiring, among the plurality of conductive paths formed via the interconnection module for simultaneously fanning out the input signal to the plurality of interconnection output points, the number of conductive paths realized via the first selection circuit does not exceed the number threshold N1 all the time, so that the driving capability of the driving pull-down circuit PD can always be ensured to satisfy the load demand. But the number of conductive paths actually used to fan out the input signal to multiple interconnected output points at the same time may exceed N1.
Under the limitation that the number of conducting paths implemented via the first selection circuit does not exceed the number threshold N1 all the time, there may be a plurality of combinations of which conducting paths are implemented by the first selection circuit and which are implemented by the second selection circuit. In one embodiment, the first selection circuit should be used as much as possible, considering that the same number of inputs requires fewer code stream bits, while the number of second selection circuits is also relatively limited. Assuming that N2 conductive paths for simultaneously fanning out an input signal to a plurality of interconnection output points need to be formed via the interconnection modules in total, when N2 is N1, all N2 conductive paths are realized via the first selection circuit. When N2> N1, N1 of the conduction paths are implemented via the first selection circuit, and then the remaining N2-N1 conduction paths are implemented via the second selection circuit within the limit of the number of conduction paths implemented via the first selection circuit. Also, the driving capability of the driving pull-down circuit PD is exceeded when all of the N2 conduction paths are implemented via the first selection circuit.
IN order to realize the function, when laying out and wiring, a plurality of conducting paths for simultaneously fanning out an input signal IN are realized by using a first selection circuit IN the interconnection module preferentially, and when the number of conducting paths realized by the first selection circuit reaches N1, the rest conducting paths are realized by using a second selection circuit IN the interconnection module.
In the above embodiments, the input signal may be connected to only the interconnection input point of one interconnection module, such as shown in fig. 3, and then the input signal is fanned out to the interconnection output point of the interconnection module only through the conductive path inside the interconnection module. The number of conductive paths for transmitting the input signal IN implemented via the first selection circuit inside the interconnect module does not exceed the number threshold N1;
Or the input signal can be simultaneously connected to the interconnection input points of the interconnection modules, and the input signal is simultaneously fanned out to the interconnection output points of the interconnection modules through a plurality of conducting paths formed inside the interconnection modules. The total number of conductive paths for transmitting the input signal IN, which are implemented by all interconnect module INT parts connected to the input signal IN via the first selection circuit, does not exceed the number threshold N1.
For example, IN fig. 4, the driving capability of the driving pull-down circuit PD to which the input signal IN is connected is designed IN advance according to the load requirements of the pull-up circuit IN 4 conduction paths realized via the first selection circuit. The input signal IN is simultaneously connected with the interconnection input points IN the three interconnection modules, and comprises an interconnection input point S_IN IN the connection interconnection module 1, an interconnection input point W_IN IN the connection interconnection module 2 and an interconnection input point W_IN IN the connection interconnection module 3. IN this example, 6 conductive paths for simultaneously fanning OUT the input signal IN are implemented IN the place and route stage according to the following procedure, the conductive path between the interconnection input point s_in and the interconnection output point n_out IN the interconnection module 1 is implemented by using the first selection circuit, the conductive path between the interconnection input point s_in and the interconnection output point w_out IN the interconnection module 1 is implemented by using the first selection circuit, the conductive path between the interconnection input point w_in and the interconnection output point n_out IN the interconnection module 2 is implemented by using the first selection circuit, the conductive path between the interconnection input point w_in and the interconnection output point e_out IN the interconnection module 2 is implemented by using the first selection circuit, the conductive path between the interconnection input point w_in and the interconnection output point s_out IN the interconnection module 2 is implemented by using the second selection circuit, and the conductive path between the interconnection input point w_in and the interconnection output point e_out IN the interconnection module 3 is implemented by using the second selection circuit. In fig. 4,4 conduction paths realized via the first selection circuit are indicated by solid lines, and 2 conduction paths realized via the second selection circuit are indicated by dash-dot lines.

Claims (7)

1. The FPGA is internally provided with an interconnection module comprising heterogeneous selectors, and is characterized in that at least one interconnection module internally provided with heterogeneous selectors is arranged in the FPGA to realize interconnection between interconnection input points and interconnection output points, the interconnection output points in the interconnection module are connected with a first selection circuit in the heterogeneous selectors, and the at least one interconnection output point is also connected with a second selection circuit in the heterogeneous selectors;
The interconnection input points connected with the input signals form a plurality of conduction paths with a plurality of interconnection output points through the heterogeneous selector, the input signals are grounded through a driving pull-down circuit, at least one conduction path is controlled by a second code stream section through a second selection circuit, and the rest conduction paths are controlled by a first code stream section through a first selection circuit;
The input end of the first selection circuit is connected with the interconnection input point, the output end of the first selection circuit is connected with a pull-up power supply through a pull-up circuit, and the output end of the first selection circuit is also connected with a corresponding interconnection output point through a buffer circuit;
the input end of the second selection circuit is connected with the interconnection input point, and the output end of the second selection circuit is connected with the corresponding interconnection output point through the buffer circuit;
In the structural design stage, the driving capability of the pull-down driving circuit connected with the input signal is designed according to the load requirement of a pull-up circuit in N1 conducting paths realized by the first selection circuit, and when the input signal is laid out and routed, the quantity of conducting paths realized by the first selection circuit does not exceed a quantity threshold N1 in a plurality of conducting paths formed by an interconnection module and used for simultaneously fanning out the input signal to a plurality of interconnection output points;
when N2 conduction paths for simultaneously fanning out an input signal to a plurality of interconnection output points need to be formed via the interconnection modules in total, all N2 conduction paths are realized via the first selection circuit when N2 is N1, when N2> N1, N1 conduction paths are realized via the first selection circuit within a limit range of the number of conduction paths realized via the first selection circuit, the remaining N2-N1 conduction paths are realized via the second selection circuit, and when all N2 conduction paths are realized via the first selection circuit, the driving capability of the driving pull-down circuit PD is exceeded.
2. The FPGA of claim 1 wherein,
The input signal is connected to an interconnection input point of an interconnection module, and the number of conducting paths for transmitting the input signal, which are realized by the first selection circuit inside the interconnection module, does not exceed a number threshold value N1;
Or the input signal is simultaneously connected to the interconnection input points of the interconnection modules, and the input signal is simultaneously fanned out to the interconnection output points of the interconnection modules through the plurality of conduction paths formed in the interconnection modules, so that the total number of the conduction paths for transmitting the input signal, which are realized in the interconnection modules connected with the input signal through the first selection circuit, does not exceed a number threshold N1.
3. The FPGA of claim 1 wherein the first code stream segment received by the first selection circuit having a number of inputs in the range of (2 P-1,2P) comprises P code stream bits and the second code stream segment received by the second selection circuit having Q inputs comprises Q code stream bits.
4. The FPGA of claim 1, wherein the structure for simultaneously connecting the first selection circuit and the second selection circuit at one interconnection output point comprises that the output end of the first selection circuit and the output end of the second selection circuit are both connected with the input end of a buffer circuit, the output end of the buffer circuit is connected with the interconnection output point, the output end of the first selection circuit is also connected with a pull-up power supply through the pull-up circuit, part of interconnection input points of the interconnection module are connected with each input end of the first selection circuit, and the rest of interconnection input points are connected with each input end of the second selection circuit.
5. The FPGA of claim 4 wherein,
The first selection circuit connected with the same interconnection output point is controlled by the first code stream section to conduct one path between one input end and one output end to form a conducting path realized by the first selection circuit, and the second selection circuit is controlled by the second code stream section to control the paths between all the input ends and the output ends to be non-conducting;
or the second selection circuit connected with the same interconnection output point is controlled by the second code stream section to conduct one path between one of the input ends and the output end to form a conducting path realized by the second selection circuit, and the first selection circuit is controlled by the first code stream section to control the paths between all the input ends and the output end to be non-conducting.
6. The FPGA of claim 4 wherein,
All interconnection output points of the interconnection module are respectively and simultaneously connected with a first selection circuit and a second selection circuit;
or part of interconnection output points of the interconnection module are respectively and simultaneously connected with the first selection circuit and the second selection circuit, and the rest of interconnection output points are respectively and only connected with the first selection circuit.
7. The FPGA of claim 5 wherein said second selection circuit is constructed based on one or more tri-state buffers, each tri-state buffer having an input connected to an interconnect input point in said interconnect module and an output connected to an input of said buffer circuit, said second bit stream segment of said second selection circuit comprising bit stream bits of each tri-state buffer;
The first code stream section and the second code stream section are both contained in a control code stream of the FPGA, and when the conducting paths realized by the first selection circuit and/or the second selection circuit are different, the total number of code stream bits contained in the control code stream of the FPGA is unchanged.
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