CN116206648B

CN116206648B - Dynamic memory, read-write method thereof and memory device

Info

Publication number: CN116206648B
Application number: CN202210102588.6A
Authority: CN
Inventors: 戴瑾
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2022-01-27
Filing date: 2022-01-27
Publication date: 2024-02-20
Anticipated expiration: 2042-01-27
Also published as: CN116206648A

Abstract

The application provides a dynamic memory, a reading and writing method thereof and a storage device, wherein after writing external input data into a storage array, a reading module reads data from the storage array and outputs the read data, but sends a feedback signal or a second electric signal to the writing module according to the read data, and the writing module adjusts a first electric signal according to the feedback signal (or the second electric signal) and the external input data and sends the adjusted current first electric signal to a selected writing bit line. And then, the read-out module is controlled to be electrically connected with the output circuit, and the read-out module outputs the data read from the memory array so as to finish reading out the data from the memory array. Therefore, when writing operation is performed on the dynamic memory, reading calibration is performed at the same time, and the first electric signal sent to the memory array by the writing module is adjusted through a feedback mechanism, so that the difference between the written data and the read data is reduced.

Description

Dynamic memory, read-write method thereof and memory device

Technical Field

The present application relates to the technical field of semiconductor devices, and in particular, to a dynamic memory, a read-write method thereof, and a storage device.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory, and compared with static memory, DRAM memory has the advantages of simpler structure, lower manufacturing cost and higher capacity density, and with the development of technology, DRAM memory is increasingly widely used.

The DRAM memory receives external input data and stores the external input data in a plurality of memory cells of the DRAM memory when performing a write operation, and outputs the data stored in the plurality of memory cells to read out the data when performing a read operation. However, the conventional DRAM memory has a problem in that there is a difference between written data and read data, which affects the performance of the DRAM memory.

Disclosure of Invention

Aiming at the defects of the prior art, the application provides a dynamic memory, a read-write method and a storage device thereof, which are used for solving the problem that the written data and the read data of the DRAM memory in the prior art are different.

In a first aspect, embodiments of the present application provide a dynamic memory, including:

the memory array comprises a plurality of memory cells, a plurality of writing lines, a plurality of writing bit lines, a plurality of reading word lines and a plurality of reading bit lines which are arranged in an array manner;

The writing module is electrically connected with the storage array and is used for receiving external input data when one writing line and a reading line corresponding to the writing line are selected and sending a first electric signal to the selected writing bit line according to the external input data;

the read-out module is electrically connected with the storage array and the write-in module respectively and is used for reading the electric signal of the read bit line corresponding to the selected write bit line when the write word line and the read word line are selected, and sending a feedback signal to the write-in module or sending a second electric signal to the write-in module according to the electric signal of the read bit line;

the writing module is further used for comparing the second electric signal with a reference electric signal after receiving the second electric signal, adjusting the first electric signal according to a comparison result until the comparison result meets a set value, and terminating writing operation and reading calibration operation; or after receiving the feedback signal, the writing module is further configured to adjust the first electrical signal according to the feedback signal until the feedback signal meets a set condition, send the current first electrical signal to the selected write bit line, and terminate the writing operation and the reading calibration operation;

The read module is also used for outputting the data of the read bit line after terminating the write operation and the read calibration operation.

Optionally, the storage unit includes a first MOS transistor and a second MOS transistor, and a gate of the first MOS transistor is electrically connected to a source of the second MOS transistor.

Optionally, after receiving the feedback signal, the writing module adjusts the first electrical signal according to the feedback signal and the external input data until the feedback signal is consistent with the external input data, sends the current first electrical signal to the selected writing bit line, and terminates writing operation and reading calibration operation.

Optionally, the readout module includes a readout circuit, and the readout circuit is electrically connected to the storage array and the write module respectively;

the read circuit is used for reading the electric signal of the read bit line corresponding to the selected write bit line when the write word line and the read word line are selected, converting the electric signal into a digital signal, and sending the converted digital signal to the write module as the feedback signal.

Optionally, the writing module includes an input signal conversion module and a comparator that are electrically connected to each other, the input signal conversion module is electrically connected to the storage array, and the comparator is electrically connected to the reading module and the input signal conversion module respectively;

The input signal conversion module is used for receiving external input data when one writing line and a reading line corresponding to the writing line are selected, converting the external input data into a third electric signal, generating a first electric signal and a reference electric signal according to the third electric signal, outputting the first electric signal to the selected writing bit line, and outputting the reference electric signal to the comparator; the method comprises the steps of,

the comparator is configured to receive the second electrical signal sent by the readout module, compare the second electrical signal with a reference electrical signal, send a first adjustment signal to the input signal conversion module if a difference value between the second electrical signal and the reference electrical signal exceeds a preset range, and send a second adjustment signal to the input signal conversion module if the difference value between the second electrical signal and the reference electrical signal is within the preset range;

the input signal conversion module is further configured to adjust the first electrical signal after receiving the first adjustment signal, and send the adjusted first electrical signal to a selected write bit line; and after receiving the second adjusting signal, sending the first electric signal after current adjustment to the selected write bit line, and terminating the write operation and the read calibration operation.

Optionally, the readout module includes a readout amplifier and an output signal conversion module that are electrically connected to each other, the readout amplifier is electrically connected to the storage array and the comparator, and the output signal conversion module is electrically connected to the readout amplifier;

the sense amplifier is used for reading an electric signal of the read bit line corresponding to the selected write bit line when the write word line and the read word line are selected, amplifying the electric signal into the second electric signal and then sending the second electric signal to the comparator; after terminating the writing operation and the reading calibration operation, reading the current electric signal of the reading bit line corresponding to the selected writing bit line, amplifying the current electric signal, and then sending the amplified current electric signal to the output signal conversion module;

the output signal conversion module is used for receiving the current signal amplified signal and converting the current signal amplified signal into a digital signal to be output.

In a second aspect, embodiments of the present application provide a dynamic memory, including a memory device in embodiments of the present application.

In a third aspect, an embodiment of the present application provides a method for reading and writing a dynamic memory, where the method includes:

Controlling the read-write state of the memory array to be a read-calibration state, so that one writing line and a read word line corresponding to the writing line are selected, and sending external input data to a write-in module;

the writing module sends a first electric signal to the selected writing bit line according to the external input data, the reading module reads the electric signal of the reading bit line corresponding to the selected writing bit line, and sends a feedback signal to the writing module or sends a second electric signal to the writing module according to the electric signal of the reading bit line;

the writing module compares the received second electric signal with a reference electric signal, adjusts the first electric signal according to a comparison result until the comparison result meets a set value, and sends the current first electric signal to the selected writing bit line; or, adjusting the first electric signal according to the received feedback signal until the feedback signal meets a set condition, and sending the current first electric signal to the selected write bit line;

and controlling the read-write state of the memory array to be a read-out state so as to terminate the write operation and the read calibration operation, and outputting the data of the read bit line by the read-out module.

Optionally, controlling the read-write state of the storage array to be a read calibration state includes:

applying a first specific voltage to the write word line of the selected row and a second specific voltage to the read word line of the selected row;

controlling the read-write state of the memory array to be a read-out state comprises:

the first specific voltage applied to the write word line of the selected row is removed, and the second specific voltage applied to the read word line of the selected row is removed.

Optionally, the writing module adjusts the first electrical signal according to the received feedback signal until the feedback signal meets a set condition, and sends the current first electrical signal to the selected write bit line, including:

the writing module compares the feedback signal with the external input data after receiving the feedback signal;

if the feedback signal is smaller than the external input data, the first electric signal is increased until the feedback signal is equal to the external input data, and the current first electric signal is sent to the selected write bit line;

and if the feedback signal is greater than the external input data, reducing the first electric signal until the feedback signal is equal to the external input data, and sending the current first electric signal to the selected write bit line.

Optionally, the writing module includes an input signal conversion module and a comparator electrically connected to each other, the input signal conversion module is electrically connected to the storage array, the comparator is electrically connected to the readout module and the input signal conversion module respectively, and the writing module sends a first electrical signal to the selected writing bit line according to the external input data, including:

the input signal conversion module receives external input data when one writing line and a reading word line corresponding to the writing line are selected, and converts the external input data into a third electric signal;

the input signal conversion module generates a first electrical signal and a reference electrical signal according to the third electrical signal, and transmits the first electrical signal to the selected write bit line.

Optionally, the writing module compares the received second electrical signal with a reference electrical signal, adjusts the first electrical signal according to a comparison result until the comparison result meets a set value, and sends a current first electrical signal to the selected writing bit line, including:

the input signal conversion module generates a first electric signal and a reference electric signal according to the third electric signal, and sends the reference electric signal to the comparator;

The read-out module reads the electric signal of the read bit line corresponding to the selected write bit line and sends a second electric signal to the comparator according to the read signal of the read bit line;

the comparator compares the second electric signal with the reference electric signal, and if the difference value between the second electric signal and the reference electric signal exceeds a preset range, a first adjusting signal is sent to the input signal conversion module;

the input signal conversion module adjusts the first electric signal after receiving the first adjusting signal, and sends the adjusted first electric signal to the selected write bit line.

The beneficial technical effects that technical scheme that this application embodiment provided brought include:

the dynamic memory in the embodiment of the application comprises a memory array, a writing module and a reading module, wherein the writing module is electrically connected with the memory array, after external input data are written into the memory array, the reading module reads the data from the memory array and outputs the read data, but sends a feedback signal or a second electric signal to the writing module according to the read data, and the writing module adjusts the first electric signal according to the feedback signal (or the second electric signal) and the external input data and sends the adjusted current first electric signal to a selected writing bit line. And then, the read-out module is controlled to be electrically connected with the output circuit, and the read-out module outputs the data read from the memory array so as to finish reading out the data from the memory array. Therefore, when writing operation is performed on the dynamic memory, reading calibration is performed at the same time, and the first electric signal sent to the memory array by the writing module is adjusted through a feedback mechanism, so that the difference between the written data and the read data is reduced.

Advantages of embodiments of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a dynamic memory according to an embodiment of the present application;

FIG. 2 is a schematic diagram of another dynamic memory according to an embodiment of the present disclosure;

FIG. 3 is a schematic circuit diagram of a memory cell in a dynamic memory according to an embodiment of the present application;

fig. 4 is a flow chart of a read-write method of a dynamic memory according to an embodiment of the present application.

In the figure:

10-dynamic memory; 11-a storage array; 21-a selection switch; 31-a write module; a 32-readout module; 311-an input signal conversion module; 312-a comparator; 321-a sense amplifier; 322-an output signal conversion module; 323-read circuit;

a 100-memory cell; 12-a first MOS tube; 13-a second MOS tube; 141-read word line; 142-read bit line; 151-write word line; 152-write bit line;

41-a common read word line; 42-a common read bit line; 43-common write line; 44-common write bit line.

Detailed Description

Examples of embodiments of the present application are illustrated in the accompanying drawings, in which like or similar reference numerals refer to like or similar elements or elements having like or similar functionality throughout. Further, if detailed description of the known technology is not necessary for the illustrated features of the present application, it will be omitted. The embodiments described below by referring to the drawings are exemplary only for the purpose of illustrating the present application and are not to be construed as limiting the present application.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.

The DRAM memory generally includes a plurality of memory cells arranged in an array, and the memory cells generally include a MOS (Metal-Oxide-semiconductor field effect transistor, metal-Oxide-Semiconductor Field-Effect Transistor) and a capacitor, and the structure thereof is relatively simple, so that the memory cells can be integrated with a relatively high density, so that the capacity per unit volume of the DRAM memory is relatively high. The main working principle of the DRAM memory is to store charges by using a capacitor, and determine whether a binary bit is 1 or 0 according to the quantity of the charges stored in the capacitor. When the DRAM memory performs a reading operation step, after decoding an externally input address, opening an nth row read word line to be selected, applying a specific voltage to the nth row read word line, connecting other read word lines with a low voltage, connecting read bit lines of columns to be read to a reading circuit, and reading an output result; when the writing operation step is carried out, after the address input from the outside is decoded, the nth writing line to be selected is opened, a high voltage is applied to the nth writing line, the rest writing lines are connected with low voltage, the writing bit lines of the columns to be written are connected to a writing circuit, and the writing circuit applies different voltages to the bit lines according to the data to be written.

The inventors of the present application considered that when a DRAM memory performs a multi-bit operation, i.e., reads and writes data of a plurality of bits in a memory cell, accurate measurement and calibration of an electrical signal applied to a memory cell write bit line and an electrical signal read from a memory cell read bit line are required to ensure accuracy and consistency of the read and write data. However, in the existing DRAM memory, due to the difference in the precision of the processing technology, different MOS transistor devices in the memory array have a difference in performance; because different memory cells are positioned at different positions in the memory array, the lengths of wires connecting the different memory cells to the read-write circuit are different (the resistances between the different memory cells and the read-write circuit are also different), so that the electrical signals received by the different memory cells are different; on the same read-write circuit chip, the read-write circuits connected with different read bit lines and write bit lines are also different in performance. The above reasons all cause a large difference between the data written into the DRAM memory and the data read from the DRAM memory, which affects the performance of the DRAM memory.

The application provides a dynamic memory, a read-write method and a storage device thereof, and aims to solve the technical problems in the prior art.

The following describes in detail the dynamic memory, the read-write method and the storage device provided in the embodiments of the present application with reference to the accompanying drawings.

As shown in fig. 1, fig. 2, and fig. 3, the dynamic memory in the embodiment of the application includes:

a memory array 11 including a plurality of memory cells 100 arranged in an array, a plurality of write word lines 151, a plurality of write bit lines 152, a plurality of read word lines 141, and a plurality of read bit lines 142;

a write module 31 electrically connected to the memory array 11, for receiving external input data when a write word line 151 and a read word line 141 corresponding to the write word line 151 are selected, and transmitting a first electrical signal to the selected write bit line 152 according to the external input data;

the read-out module 32 is electrically connected to the memory array 11 and the write module 31, and is configured to read an electrical signal of the read bit line 142 corresponding to the selected write bit line 152 when the write word line 151 and the read word line 141 are selected, and send a feedback signal to the write module 31 or send a second electrical signal to the write module 31 according to the electrical signal of the read bit line 142;

the writing module 31 is further configured to compare the second electrical signal with a reference electrical signal after receiving the second electrical signal, adjust the first electrical signal according to the comparison result, and terminate the writing operation and the reading calibration operation until the comparison result meets a set value; or, after receiving the feedback signal, the writing module 31 is further configured to adjust the first electrical signal according to the feedback signal until the feedback signal meets a set condition, send the current first electrical signal to the selected write bit line 152, and terminate the write operation and the read calibration operation;

The sense module 32 is also configured to output data from the read bit line 142 after terminating the write operation and the read calibration operation.

Specifically, as shown in fig. 1, 2 and 3, the dynamic memory 10 includes a memory array 11, a selection switch 21 electrically connected to the memory array 11, a write module 31 electrically connected to the selection switch 21, and a read module 32. The memory array 11 includes a plurality of memory cells 100 arranged in an array, wherein the memory cells include a plurality of rows of memory cells 100 distributed along a first direction in fig. 1 and a plurality of columns of memory cells 100 distributed along a second direction in fig. 1. Each memory cell 100 includes a first MOS transistor 12, a second MOS transistor 13, a read word line 141, a write word line 151, a read bit line 142, and a write bit line 152, where the first MOS transistor 12 is a read MOS transistor, and the second MOS transistor 13 is a write MOS transistor. The gate of the first MOS transistor 12 is electrically connected to the source/drain of the second MOS transistor 13, the read bit line 142 and the read word line 141 are electrically connected to the source/drain of the first MOS transistor 12, the write word line 151 is electrically connected to the gate of the second MOS transistor 13, and the write bit line 152 is electrically connected to the source/drain of the second MOS transistor 13.

Referring to fig. 1 and 2, the read word lines 141 of the memory cells 100 of the same row are connected to the common read word line 41, and the write word lines 151 of the memory cells 100 of the same row are connected to the common write word line 43. The read bit lines 142 of the same column of memory cells 100 are connected to a common read bit line 42 and the write bit lines 152 of the same column of memory cells 100 are connected to a common write bit line 44. It should be noted that the number of rows and columns of the memory cells 100 in the memory array 11 may be adjusted according to the actual situation, and accordingly, the numbers of the common read word lines 41, the common read bit lines 42, the common write word lines 43, and the common write bit lines 44 may also be adjusted according to the actual situation, which is not limited herein.

In one embodiment, as shown in fig. 1 and 3, after the row address decoder (not shown in the drawings) decodes the external input data in the writing operation step, one common write word line 43 is selected and a high voltage is applied to the second gate of the memory cell 100 located in the same row as the common write word line 43, so as to turn on the memory cell 100 in the same row (i.e., the second MOS transistor 13 in the memory cell 100 to which the data is to be written). Meanwhile, after the column address decoder (not shown in the figure) decodes the external input data, the selection switch 21 turns on the common write bit line 44 corresponding to the memory cell 100 to be written with data to the write module 31 (the memory cell 100 to be written with data is located in the same column, and the write bit line 152 corresponding to the memory cell 100 to be written with data is connected to the same column write bit line). When a write word line 151 and a read word line 141 corresponding to the write word line 151 are selected (the write word line 151 and the read word line 141 corresponding thereto refer to write word lines and read word lines of memory cells to which data is to be written), the write module 31 receives external input data (the external input data is a digital signal) and generates a first electrical signal according to the external input data, and then sends the first electrical signal to the selected write bit line 152 (i.e., a common write bit line corresponding to the memory cells to which data is to be written) to write data into the memory cells 100 to which data is to be written, so that the data is written into the memory array 11.

The embodiment of the application performs the read calibration step while performing the write operation step. Specifically, as shown in fig. 1 and 3, after decoding the externally input data, the row address decoder selects one common read word line 41 and applies a specific voltage (the specific voltage is applied to the source and drain of the first MOS transistor 12 in the memory cells 100 located in the same row as the common read word line 41, the first MOS transistor 12 is correspondingly connected to the second MOS transistor 13 in the memory cell 100 to be written with the data), and meanwhile, the selection switch 21 switches on the read bit line 142 corresponding to the selected write bit line 152 (i.e., the common read bit line 42 corresponding to the memory cell 100 to which the data is written in the write operation step) to the readout module 32, so that the readout module 32 reads the electrical signal (the signal is the current signal) on the read bit line 142 corresponding to the selected write bit line 152. The readout module 32 converts the electric signal into a feedback signal (the feedback signal is a digital signal), and sends the feedback signal to the write module 31. It should be noted that, the feedback signal is the data signal read from the memory cell 100.

After receiving the feedback signal, the writing module 31 adjusts the first electrical signal according to the feedback signal and the external input data, until the feedback signal meets the set condition, and then sends the current first electrical signal (the adjusted first electrical signal) to the selected write bit line 152, and terminates the selected write word line 151 and the read word line 141 (i.e., terminates the write operation and the read calibration operation). The sense module 32 is then controlled to electrically connect to the output circuit, and the sense module 32 outputs a signal on the read bit line 142 to complete the reading of data from the memory array 11. It should be noted that the setting condition may be determined according to an actual situation, for example, a range is set, and if the difference between the feedback signal and the external input data is within the set range, it is determined that the feedback signal meets the setting condition, and a specific determining relationship between the feedback signal and the setting condition will be described in detail later.

In the dynamic memory 10 provided in this embodiment of the present application, after the writing module 31 writes the external input data into the memory array 11, the reading module 32 reads the data from the memory array 11, and does not output the read data first, but sends a feedback signal to the writing module 31 according to the read data, and the writing module 31 adjusts the first electrical signal according to the feedback signal and the external input data until the feedback signal meets the set condition (the difference between the feedback signal and the external input data is within the preset range), and then sends the current first electrical signal to the selected write bit line 152, and terminates the selected write word line 151 and the read word line 141 (i.e. terminates the write operation and the read calibration operation). After that, the readout module 32 is controlled to be electrically connected to the output circuit, and the readout module 32 outputs the data read from the memory array 11 to complete the readout of the data from the memory array 11. Therefore, when the writing operation is performed on the dynamic memory 10, the reading calibration operation is performed at the same time, and the first electric signal sent to the memory array 11 by the writing module 31 is adjusted through the feedback mechanism, so that the difference between the writing data and the reading data can be reduced, and the performance of the dynamic memory 10 is ensured.

It should be noted that, the generation of the feedback signal and the determination of which setting condition the feedback signal specifically needs to satisfy may all be determined according to the actual situation. Optionally, as shown in fig. 1, in the embodiment of the present application, after receiving the feedback signal, the writing module 31 adjusts the first electrical signal according to the feedback signal and the external input data until the feedback signal is consistent with the external input data, sends the current first electrical signal to the selected write bit line 152, and terminates the writing operation and the reading calibration operation.

With continued reference to FIG. 1, the read-out module 32 in the present embodiment includes a read circuit 323, where the read circuit 323 is electrically connected to the memory array 11 and the write module 31, respectively; the read circuit 323 is configured to read an electrical signal of the read bit line 142 corresponding to the selected write bit line 152 when the write word line 151 and the read word line 141 are selected, convert the electrical signal into a digital signal, and transmit the converted digital signal as a feedback signal to the write module 31.

Specifically, as shown in fig. 1, the writing module 31 adjusts the first electrical signal by comparing the magnitude of the feedback signal (digital signal) and the magnitude of the external input data (digital signal), and if the feedback signal is smaller than the external input data (e.g., the feedback signal is P and the external input data is p+1), the writing module 31 increases the first electrical signal. The write module 31 sends the adjusted first electrical signal (i.e., the current first electrical signal) to the selected write bit line 152, and the read module 32 continues to read the electrical signal (the voltage signal) on the read bit line 142 corresponding to the selected write bit line 152 (i.e., the write bit line 152 that receives the adjusted first electrical signal), converts the electrical signal into a feedback signal (the feedback signal is the digital signal converted by the electrical signal on the read bit line 142), and sends the feedback signal to the write module 31. The above steps are repeated until the feedback signal is identical to the external input data, and the selected write word line 151 and the read word line 141 are terminated (i.e., the write operation and the read calibration operation are terminated). Then, a read operation is performed on the dynamic memory 10, a specific voltage is applied to the read word line 141 corresponding to the memory cell 100 to be read, the read circuit 323 in the read module 32 is controlled to be electrically connected to the read bit line 142 corresponding to the memory cell 100 to be read, an electrical signal (the signal is a current signal) of the read bit line 142 corresponding to the selected write bit line 152 is read, the read circuit 323 converts the electrical signal into a digital signal, and the read circuit 323 in the read module 32 is controlled to be electrically connected to an output circuit (not shown in the figure) to output a signal on the read bit line 142 (the signal on the read bit line 142 at this time is consistent with external input data) so as to complete reading data from the memory array 11. By transmitting the digital signal converted from the electric signal of the read bit line 142 as a feedback signal to the write module 31 and setting whether the judgment feedback signal satisfies the setting condition to judge whether the feedback signal coincides with the externally input data, the externally input data can be made to coincide with the data signal read from the memory array 11 even if the write data coincides with the read data, further improving the accuracy of the multibit operation.

In another embodiment, as shown in connection with fig. 2 and 3, the writing module 31 includes an input signal conversion module 311 and a comparator 312 electrically connected to each other, the input signal conversion module 311 is electrically connected to the memory array 11, and the comparator 312 is electrically connected to the reading module 32 and the input signal conversion module 311, respectively;

the input signal conversion module 311 is configured to receive external input data when a write word line 151 and a read word line 141 corresponding to the write word line 151 are selected, convert the external input data into a third electrical signal (a voltage signal corresponding to the external input data), generate a first electrical signal and a reference electrical signal according to the third electrical signal, output the first electrical signal to the selected write bit line 152, and output the reference electrical signal to the comparator 312; the method comprises the steps of,

the comparator 312 is configured to receive the second electrical signal sent by the readout module 32, compare the second electrical signal with the reference electrical signal, send a first adjustment signal to the input signal conversion module 311 if the difference between the second electrical signal and the reference electrical signal exceeds a preset range, and send a second adjustment signal to the input signal conversion module 311 if the difference between the second electrical signal and the reference electrical signal is within the preset range;

The input signal conversion module 311 is further configured to adjust the first electrical signal after receiving the first adjustment signal, and send the adjusted first electrical signal to the selected write bit line 152; and after receiving the second adjustment signal, sending the current adjusted first electrical signal to the selected write bit line 152 and terminating the write operation and the read calibration operation.

Specifically, as shown in fig. 2 and 3, the input signal conversion module 311 converts external input data (the signal is a digital signal) into a third electrical signal (an analog signal) after receiving the external input data, and generates a first electrical signal (a voltage signal) and a reference electrical signal (a voltage signal) from the third electrical signal. The reference electrical signal and the external input data satisfy a corresponding correspondence relationship, that is, the external input data of a specific value corresponds to the reference electrical signal of a specific value. The selection switch 21 turns on the common write bit line 44 corresponding to the memory cell 100 to be written to the input signal conversion module 311, the input signal conversion module 311 sends the first electrical signal to the selected write bit line 152, i.e. the write bit line 152 corresponding to the memory cell 100 to be written to write data to the memory array 11, and the input signal conversion module 311 also sends the reference electrical signal to the comparator 312.

The read calibration operation is performed while writing data into the memory array 11, specifically, after the row address decoder decodes the external input data, one common read word line 41 is selected and a specific voltage is applied to the common read word line (the specific voltage is applied to the source and the drain of the first MOS transistor 12 in the memory cells 100 located in the same row as the common read word line 41), and at the same time, the selection switch 21 switches on the read bit line 142 corresponding to the selected write bit line 152 (i.e., the common read bit line 42 corresponding to the memory cell 100 in which data is written in the write operation step) to the read module 32, so that the read module 32 reads the electrical signal (the signal is a current signal) on the read bit line 142 corresponding to the selected write bit line 152. The sense module 32 sends a second electrical signal (voltage signal) to the comparator 312 based on the electrical signal on the read bit line 142. The comparator 312 compares the received reference electrical signal with the second electrical signal, if the difference between the second electrical signal and the reference electrical signal exceeds the preset range, the first adjustment signal is sent to the input signal conversion module 311, the input signal conversion module 311 adjusts the first electrical signal according to the first adjustment signal until the difference between the second electrical signal and the reference electrical signal is within the preset range, the comparator 312 sends the second adjustment signal to the input signal conversion module 311, and the input signal conversion module 311 sends the current first electrical signal (the adjusted first electrical signal) to the selected write bit line 152 after receiving the second adjustment signal, so as to write the data into the memory array 11. After that, the read calibration operation is terminated, and the read module 32 reads the electrical signal (the current signal) on the read bit line 142 corresponding to the selected write bit line 152, and converts the electrical signal on the read bit line 142 into a digital signal and outputs the digital signal to read the data from the memory array 11.

In the dynamic memory 10 provided in this embodiment of the present application, after the writing module 31 writes the external input data into the memory array 11, the reading module 32 reads the data from the memory array 11, and does not output the read data first, but sends the second electrical signal to the writing module 31 according to the read data, the writing module 31 adjusts the first electrical signal according to the second electrical signal and the external input data until the second electrical signal meets the set condition, sends the current first electrical signal to the selected write bit line 152, and terminates the selected write word line 151 and the read word line 141 (i.e. terminates the write operation and the read calibration operation). Thereafter, the readout module 32 is controlled to be electrically connected to an output circuit (not shown in the figure), and the readout module 32 outputs the data read from the memory array 11 to complete the readout of the data from the memory array 11. Therefore, when the writing operation is performed on the dynamic memory 10, the reading calibration operation is performed at the same time, and the first electric signal sent to the memory array 11 by the writing module 31 is adjusted through the feedback mechanism, so that the difference between the writing data and the reading data can be reduced, and the performance of the dynamic memory 10 is ensured.

Optionally, in the embodiment of the present application, the readout module 32 includes a readout amplifier 321 and an output signal conversion module 322 that are electrically connected to each other, where the readout amplifier 321 is electrically connected to the memory array 11 and the comparator 312, and the output signal conversion module 322 is electrically connected to the readout amplifier 321;

The sense amplifier 321 is configured to read an electrical signal of the read bit line 142 corresponding to the selected write bit line 152 when the write word line 151 and the read word line 141 are selected, amplify the electrical signal into a second electrical signal, and send the second electrical signal to the comparator 312; and, after terminating the write operation and the read calibration operation, reading the current electrical signal of the read bit line 142 corresponding to the selected write bit line 152, and amplifying the current electrical signal and then transmitting to the output signal conversion module 322; the output signal conversion module 322 is configured to receive the current amplified signal and convert the current amplified signal into a digital signal for output.

Specifically, after entering the read calibration mode, the sense amplifier 321 is controlled to be turned on with the common read bit line 42 corresponding to the memory cell 100 to be read, and the sense amplifier 321 reads an electrical signal (current signal) of the read bit line 142 corresponding to the selected write bit line 152, amplifies the electrical signal into a voltage signal (i.e., a second electrical signal), and sends the voltage signal to the comparator 312. The comparator 312 compares the second electrical signal with the reference electrical signal, if the difference between the second electrical signal and the reference electrical signal exceeds the preset range, the comparator 312 sends a first adjustment signal to the input signal conversion module 311, the input signal conversion module 311 adjusts the first electrical signal according to the first adjustment signal until the difference between the second electrical signal and the reference electrical signal is within the preset range, and the input signal conversion module 311 sends the current first electrical signal (the adjusted first electrical signal) to the selected write bit line 152 to write data into the memory array 11. After that, the read calibration operation is terminated, and the sense amplifier 321 reads the electrical signal (the signal is a current signal) on the read bit line 142 corresponding to the selected write bit line 152, amplifies the electrical signal on the read bit line 142 into a voltage signal, and sends the voltage signal to the output signal conversion module 322, and the output signal conversion module 322 converts the voltage signal into a digital signal and outputs the digital signal to read data from the memory array 11. By providing the sense amplifier 321, the electrical signal of the read bit line 142 can be amplified and then sent to the comparator 312, which facilitates the comparator 312 to compare the electrical signal of the read bit line 142 with the reference electrical signal, and is beneficial to improving the accuracy of the first electrical signal adjustment so as to reduce the difference between the external input data and the data signal read from the memory array 11.

It should be noted that the preset range of the difference between the second electric signal and the reference electric signal can be adjusted according to the actual situation. The reference electric signal and the external input data meet the corresponding relation, namely, the external input data with a specific value corresponds to the reference electric signal with a specific value. After receiving the second electrical signal and the reference electrical signal, the comparator 312 compares the two, if the difference value of the two exceeds the preset range, the comparator sends a first adjusting signal to the input signal conversion module 311, the input signal conversion module 311 adjusts the first electrical signal according to the first adjusting signal until the difference value of the second electrical signal and the reference electrical signal is within the preset range, the comparator 312 sends a second adjusting signal to the input signal conversion module 311, and after receiving the second adjusting signal, the input signal conversion module 311 sends the current first electrical signal (the adjusted first electrical signal) to the selected write bit line 152 so as to write data into the memory array 11. In particular, the first adjustment signal is used to increase the first electrical signal when the second electrical signal is less than the reference electrical signal and to decrease the first electrical signal when the second electrical signal is greater than the reference electrical signal. Accordingly, a difference between the externally input data and the data signal read from the memory array 11 can be reduced, improving the accuracy of the multi-bit operation. Alternatively, the comparator 312 sends the first adjustment signal to the input signal conversion module 311 when the second electrical signal is not equal to the reference electrical signal, and the comparator 312 sends the second adjustment signal to the input signal conversion module 311 when the second electrical signal is equal to the reference signal, whereby the difference between the external input data and the data signal read from the memory array 11 can be further reduced.

Based on the same inventive concept, the embodiments of the present application also provide a storage device, which includes the above-mentioned dynamic memory 10 provided in the embodiments of the present application. Since the memory device includes the dynamic memory 10 provided in the embodiments of the present application, the memory device has the same advantages as the dynamic memory 10, and will not be described herein.

Specifically, the storage device in the embodiment of the present application may be a solid state disk, or a usb disk, and may specifically be determined according to an actual situation.

Based on the same inventive concept, the embodiment of the present application further provides a method for reading and writing a dynamic memory, as shown in fig. 4, including:

s101, controlling the read-write state of a storage array to be a read calibration state so that a write word line and a read word line corresponding to the write word line are selected, and sending external input data to a write-in module;

s102, the writing module sends a first electric signal to a selected writing bit line according to external input data, the reading module reads an electric signal of a reading bit line corresponding to the selected writing bit line, and sends a feedback signal to the writing module or sends a second electric signal to the writing module according to the electric signal of the reading bit line;

s103, the writing module compares the received second electric signal with the reference electric signal, adjusts the first electric signal according to the comparison result until the comparison result meets the set value, and sends the current first electric signal to the selected writing bit line; or, adjusting the first electric signal according to the received feedback signal until the feedback signal meets the set condition, and sending the current first electric signal to the selected write bit line;

S104, controlling the read-write state of the memory array to be a read-out state so as to terminate the write operation and the read calibration operation, and outputting the data of the read bit line by the read-out module.

In the method for reading and writing the dynamic memory 10 provided in the embodiment of the present application, after the writing module 31 writes the external input data into the memory array 11, the reading module 32 reads the data from the memory array 11, and first sends the feedback signal or the second electrical signal to the writing module 31 according to the read data, and the writing module 31 adjusts the first electrical signal according to the feedback signal (or the second electrical signal) and the external input data until the feedback signal or the second electrical signal meets the set condition, and then sends the adjusted current first electrical signal to the selected write bit line 152, and terminates the selected write word line 150 and the read word line 141 (i.e. terminates the writing operation and the reading calibration operation). After that, the readout module 32 is controlled to be electrically connected to the output circuit, and the readout module 32 outputs the data read from the memory array 11 to complete the readout of the data from the memory array 11. Therefore, when the dynamic memory 10 is written, the read calibration is performed at the same time, and the first electric signal sent to the memory array 11 by the writing module 31 is adjusted by the feedback mechanism, so that the difference between the written data and the read data can be reduced, and the performance of the dynamic memory 10 is ensured.

In the embodiment of the present application, controlling the read-write state of the memory array 11 to be the read-calibrate state includes:

Specifically, the read calibration operation is performed simultaneously with the write operation to the memory array 11. After decoding external input data, a row address decoder (not shown in the figure) selects a common write word line 43 and applies a first specific voltage to a second MOS transistor in a memory cell 100 located in the same row as the common write word line 43 to turn on the second MOS transistor 13 in the memory cell 100 in the same row, while a column address decoder (not shown in the figure) decodes external input data, and then the writing module 31 applies a second specific voltage to the second MOS transistor in the memory cell 100 located in the same column as the common write bit line 44 (the second MOS transistor 13 in the memory cell 100 is in an on state) through a common write bit line 44 according to the external input data to complete writing of data. Meanwhile, after the row address decoder decodes the externally input data, a common read word line 41 is selected and applied with a specific voltage (the specific voltage is applied to the source and drain of the first MOS transistor 12 in the memory cell 100 located in the same row as the common read word line 41), and at the same time, the read module 32 turns on the common read bit line 42 (the common read bit line 42 of the column to be read) to read the data on the read bit line (the signal is not output at this time). When the read calibration operation is terminated and data in the memory array 11 needs to be read out and output, the first specific voltage applied by the write word line of the selected row may be removed, the read block 32 turns on the common read bit line 42, and an external output circuit (not shown) is turned on to read out the data in the memory array 11.

In one embodiment, the writing module 31 adjusts the first electrical signal according to the received feedback signal until the feedback signal meets a set condition, and sends the current first electrical signal to the selected write bit line, including:

after receiving the feedback signal, the writing module compares the feedback signal with external input data;

if the feedback signal is greater than the external input data, the first electrical signal is reduced until the feedback signal is equal to the external input data, and the current first electrical signal is sent to the selected write bit line.

Specifically, after the writing module 31 writes the external input data into the memory array 11, the reading module 32 reads the data from the memory array 11, and does not output the read data first, but sends a feedback signal to the writing module according to the read data, the writing module 31 adjusts the first electrical signal according to the feedback signal and the external input data until the feedback signal meets the set condition (the difference between the feedback signal and the external input data is within the preset range), and sends the current first electrical signal to the selected write bit line 152, and terminates the selected write word line 151 and the read word line 141 (i.e. terminates the write operation and the read calibration operation). Thereafter, the read-out module 32 is controlled to be electrically connected to an external output circuit (not shown), and the read-out module 32 outputs the data read from the memory array 11 to complete the reading out of the data from the memory array.

The writing module 31 adjusts the first electrical signal by comparing the magnitude of the feedback signal (digital signal) with the magnitude of the external input data (digital signal), and if the feedback signal is smaller than the external input data (e.g., the feedback signal is P and the external input data is p+1), the writing module 31 increases the first electrical signal. The write module 31 sends the adjusted first electrical signal (i.e., the current first electrical signal) to the selected write bit line, and the read module 32 continues to read the electrical signal (the signal is a voltage signal) on the read bit line 142 corresponding to the selected write bit line 152, and sends the electrical signal to the write module 31 after converting the electrical signal into a feedback signal (the feedback signal is a digital signal converted by the electrical signal on the read bit line). If the feedback signal is greater than the external input data (e.g., the feedback signal is p+1 and the external input data is P), the writing module 31 decreases the first electrical signal. The write module 31 sends the adjusted first electrical signal (i.e., the current first electrical signal) to the selected write bit line 152, and the read module 32 continues to read the electrical signal (the signal is a voltage signal) on the read bit line 142 corresponding to the selected write bit line 152, and sends the electrical signal to the write module 31 after converting the electrical signal into a feedback signal (the feedback signal is a digital signal converted by the electrical signal on the read bit line 142).

Alternatively, when the external input data is P, the input signal conversion module 311 may first adjust the first electrical signal to the feedback signal (the digital signal converted from the signal on the read bit line) to p+1, then reduce the first electrical signal until the feedback signal is P, stop the read calibration, and control the read circuit 323 to communicate with the external output circuit to output the digital signal converted from the signal on the read bit line 142, so as to read the data from the memory array 11. If the external input data P is the maximum value of the data that can be stored in the memory array 11, after the feedback signal is adjusted to P, the first electrical signal can be slightly increased, so that a space is reserved for the leakage of the MOS transistor in the memory unit 100 (the leakage current of the MOS transistor causes the charge loss on the storage capacitor), and the inaccuracy of the written data caused by the leakage of the MOS transistor is avoided.

When the feedback signal coincides with the externally input data, the selected write word line 151 and the read word line 141 are terminated (i.e., the write operation and the read calibration operation are terminated). Then, the dynamic memory 10 is read again, a specific voltage is applied to the read word line 141 corresponding to the memory cell 100 to be read, the read circuit 323 in the read module 32 is controlled to be electrically connected to the read bit line 142 corresponding to the memory cell 100 to be read, the electric signal (the signal is a current signal) of the read bit line 142 corresponding to the selected write bit line 152 is read, the read circuit 323 converts the electric signal into a digital signal, and the read circuit 323 is controlled to be electrically connected to the external output circuit, and then the read circuit 323 electrically connects the electric signal (the feedback signal at this time is consistent with the external input data) on the read bit line 142, so as to complete the data reading from the memory array 11.

In another embodiment, the writing module 31 includes an input signal conversion module 311 and a comparator 312 electrically connected to each other, the input signal conversion module 311 is electrically connected to the memory array 11, the comparator 312 is electrically connected to the sensing module 32 and the input signal conversion module 311, respectively, and the writing module 31 sends a first electrical signal to the selected writing bit line 152 according to external input data, including:

the input signal conversion module receives external input data when a writing line and a reading word line corresponding to the writing line are selected, and converts the external input data into a third electric signal;

the input signal conversion module generates a first electrical signal and a reference electrical signal according to the third electrical signal and transmits the first electrical signal to the selected write bit line.

Optionally, the writing module 31 compares the received second electrical signal with a reference electrical signal, adjusts the first electrical signal according to the comparison result until the comparison result meets a set value, and sends the current first electrical signal to the selected write bit line, including:

the comparator compares the second electric signal with the reference electric signal, and if the difference value between the second electric signal and the reference electric signal exceeds a preset range, the comparator sends a first adjusting signal to the input signal conversion module;

Specifically, as shown in fig. 2 and 3, after receiving the external input data (the signal is a digital signal), the input signal conversion module 311 converts the external input data into a third electrical signal (an analog signal), and generates a first electrical signal (a voltage signal) and a reference electrical signal (a voltage signal) according to the third electrical signal, where the reference electrical signal and the external input data satisfy a corresponding relationship, that is, the external input data with a specific value is converted into the analog signal and then is the first electrical signal with a specific value. The selection switch 21 turns on the common write bit line 44 corresponding to the memory cell 100 to be written to the input signal conversion module (i.e., selects one write bit line), the input signal conversion module 311 sends the first electrical signal to the selected write bit line 152, i.e., the write bit line 152 corresponding to the memory cell 100 to be written to write data to the memory array 11, and the input signal conversion module 311 also sends the reference electrical signal to the comparator 312.

The read calibration operation is performed while writing data into the memory array 11, specifically, after the row address decoder decodes the external input data, one common read word line 41 is selected and a specific voltage is applied to the common read word line (the specific voltage is applied to the source and the drain of the first MOS transistor 12 in the memory cells 100 located in the same row as the common read word line 41), and at the same time, the selection switch 21 switches on the read bit line 142 corresponding to the selected write bit line 152 (i.e., the common read bit line 42 corresponding to the memory cell 100 in which data is written in the write operation step) to the read module 32, so that the read module 32 reads the electrical signal (the signal is a current signal) on the read bit line 142 corresponding to the selected write bit line 152. The sense module 32 sends a second electrical signal (voltage signal) to the comparator 312 based on the electrical signal on the read bit line. The comparator 312 compares the received reference electrical signal with the second electrical signal, if the difference between the second electrical signal and the reference electrical signal exceeds the preset range, the first adjustment signal is sent to the input signal conversion module 311, the input signal conversion module 311 adjusts the first electrical signal according to the first adjustment signal until the difference between the second electrical signal and the reference electrical signal is within the preset range, the comparator 312 sends the second adjustment signal to the input signal conversion module 311, and the input signal conversion module 311 sends the current first electrical signal (the adjusted first electrical signal) to the selected write bit line after receiving the second adjustment signal, so as to write the data into the memory array 11. After that, the read calibration operation is terminated, and the read module 32 reads the electrical signal (the current signal) on the read bit line corresponding to the selected write bit line, and converts the electrical signal on the read bit line into a digital signal and outputs the digital signal to read the data from the memory array 10.

The sense module 32 includes a sense amplifier 321 and an output signal conversion module 322 electrically connected to each other, the sense amplifier 321 being electrically connected to the memory array 11 and the comparator 312, respectively, and the output signal conversion module 322 being electrically connected to the sense amplifier 321. After entering the read calibration mode, the sense amplifier 321 is controlled to be turned on with the common read bit line 42 corresponding to the memory cell 100 to be read, and the sense amplifier 321 reads an electric signal (current signal) of the read bit line corresponding to the selected write bit line, amplifies the electric signal into a voltage signal (i.e., a second electric signal), and then sends the voltage signal to the comparator 312. The comparator 312 compares the second electrical signal with the reference electrical signal, if the difference between the second electrical signal and the reference electrical signal exceeds the preset range, the comparator 312 sends a first adjustment signal to the input signal conversion module 311, the input signal conversion module 311 adjusts the first electrical signal according to the first adjustment signal until the difference between the second electrical signal and the reference electrical signal is within the preset range, and the input signal conversion module 311 sends the current first electrical signal (the adjusted first electrical signal) to the selected write bit line 152 to write data into the memory array 11. After that, the read calibration operation is terminated, and the sense amplifier 321 reads the electrical signal (the signal is a current signal) on the read bit line 142 corresponding to the selected write bit line 152, amplifies the electrical signal on the read bit line 142 into a voltage signal, and sends the voltage signal to the output signal conversion module 322, and the output signal conversion module 322 converts the voltage signal into a digital signal and outputs the digital signal to read data from the memory array 11.

The preset range of the difference value between the second electric signal and the reference electric signal can be adjusted according to actual conditions. Optionally, if the second electric signal is equal to the reference electric signal, determining that the difference between the second electric signal and the reference electric signal is within a preset range, otherwise, determining that the difference between the second electric signal and the reference electric signal exceeds the preset range. That is, after receiving the second electrical signal and the reference electrical signal, the comparator 312 compares the second electrical signal and the reference electrical signal, if the difference between the second electrical signal and the reference electrical signal exceeds the preset range, the comparator sends a first adjustment signal to the input signal conversion module 311, the input signal conversion module 311 adjusts the first electrical signal according to the first adjustment signal until the difference between the second electrical signal and the reference electrical signal is within the preset range, the comparator 312 sends a second adjustment signal to the input signal conversion module 311, and the input signal conversion module sends the current first electrical signal (the adjusted first electrical signal) to the selected write bit line 152 after receiving the second adjustment signal, so as to write data into the memory array 11. Accordingly, the difference between the externally input data and the data signal read from the memory array 11 can be further reduced.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

1. the application provides a dynamic memory, a reading and writing method thereof and a storage device, wherein after writing external input data into a storage array, a reading module reads data from the storage array and outputs the read data, but sends a feedback signal or a second electric signal to the writing module according to the read data, and the writing module adjusts a first electric signal according to the feedback signal (or the second electric signal) and the external input data and sends the adjusted current first electric signal to a selected writing bit line. And then, the read-out module is controlled to be electrically connected with the output circuit, and the read-out module outputs the data read from the memory array so as to finish reading out the data from the memory array. Therefore, when writing operation is performed on the dynamic memory, reading calibration is performed at the same time, and the first electric signal sent to the memory array by the writing module is adjusted through a feedback mechanism, so that the difference between the written data and the read data is reduced.

2. In the embodiment of the present application, by transmitting the digital signal converted from the electrical signal of the read bit line 142 as the feedback signal to the write module 31 and setting the judgment whether the feedback signal satisfies the setting condition to judge whether the feedback signal is identical to the external input data (both the feedback signal and the external input data are digital signals), the external input data can be made identical to the data signal read from the memory array 11 even if the write data is identical to the read data, further improving the accuracy of the multi-bit operation.

3. In the embodiment of the present application, by providing the sense amplifier 321 in the sense module 32, the electrical signal of the read bit line 142 can be amplified and then sent to the comparator 312, which is convenient for the comparator 312 to compare the electrical signal of the read bit line 142 with the reference electrical signal, and is beneficial to improving the accuracy of the first electrical signal adjustment, so as to reduce the difference between the external input data and the data signal read from the memory array 11.

4. In the embodiment of the present application, when the external input data is P, the input signal conversion module 311 may first adjust the first electrical signal to the feedback signal (the digital signal converted from the signal electrical signal on the read bit line) to p+1, then reduce the first electrical signal until the feedback signal is P, stop the read calibration, and control the read circuit 323 to communicate with the external output circuit to output the digital signal converted from the signal electrical signal on the read bit line 142, so as to read the data from the memory array 11. If the external input data P is the maximum value of the data that can be stored in the memory array 11, after the feedback signal is adjusted to P, the first electrical signal can be slightly increased, so that a space is reserved for the leakage of the MOS transistor in the memory unit 100 (the leakage current of the MOS transistor causes the charge loss on the storage capacitor), and the inaccuracy of the written data caused by the leakage of the MOS transistor is avoided.

In the description of the present application, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.

The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for a person skilled in the art, several improvements and modifications can be made without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims

1. A dynamic memory, comprising:

2. The dynamic memory of claim 1, wherein the memory cell comprises a first MOS transistor and a second MOS transistor, a gate of the first MOS transistor being electrically connected to a source of the second MOS transistor.

3. The dynamic memory of claim 2, wherein the write module, upon receiving the feedback signal, adjusts the first electrical signal based on the feedback signal and the external input data until the feedback signal is consistent with the external input data, sends a current first electrical signal to the selected write bit line, and terminates the write operation and the read calibration operation.

4. A dynamic memory as claimed in claim 3, wherein the read-out module comprises a read circuit electrically connected to the memory array and the write-in module, respectively;

5. The dynamic memory of claim 2, wherein the write module comprises an input signal conversion module and a comparator electrically connected to each other, the input signal conversion module being electrically connected to the memory array, the comparator being electrically connected to the read module and the input signal conversion module, respectively;

6. The dynamic memory of claim 5, wherein the sense module comprises a sense amplifier and an output signal conversion module electrically connected to each other, the sense amplifier being electrically connected to the memory array and the comparator, respectively, the output signal conversion module being electrically connected to the sense amplifier;

the sense amplifier is used for reading an electric signal of the read bit line corresponding to the selected write bit line when the write word line and the read word line are selected, amplifying the electric signal into the second electric signal and then sending the second electric signal to the comparator; after terminating the write operation and the read calibration operation, reading the current electric signal of the read bit line corresponding to the selected write bit line, amplifying the current electric signal, and then sending the amplified current electric signal to the output signal conversion module;

7. A memory device comprising the dynamic memory of any one of claims 1 to 6.

8. A method of reading from and writing to a dynamic memory as recited in any of claims 1-6, wherein the method of reading from and writing to comprises:

9. The method of claim 8, wherein controlling the read-write state of the memory array to be a read-calibrate state comprises:

10. The method of claim 8, wherein the writing module adjusts the first electrical signal according to the received feedback signal until the feedback signal meets a set condition, and sending the current first electrical signal to the selected write bit line comprises:

11. The method of claim 8, wherein the write module includes an input signal conversion module and a comparator electrically connected to each other, the input signal conversion module electrically connected to the memory array, the comparator electrically connected to the read module and the input signal conversion module, respectively, the write module transmitting a first electrical signal to the selected write bit line based on the external input data, comprising:

12. The method of claim 11, wherein the writing module compares the received second electrical signal with a reference electrical signal, adjusts the first electrical signal according to the comparison result until the comparison result meets a set value, and sends the current first electrical signal to the selected write bit line, comprising: