CN116209278A - Semiconductor structure - Google Patents

Abstract

The embodiment of the application belongs to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor structure. The semiconductor structure provided by the embodiment of the application comprises a substrate, wherein the substrate comprises a first storage area, a second storage area and a peripheral area; the peripheral area is arranged at the periphery of the first storage area and the second storage area; the first storage area is arranged at the periphery of the second storage area, and at least one side of the second storage area is adjacent to the peripheral area. Compared with the related art, two memory cells in the semiconductor structure are stacked in the direction perpendicular to the substrate, and the first memory area and the second memory area are arranged in the same plane, so that the process flow can be simplified, and the integration of the device is improved.

Description

semiconductor structure

technical field

The embodiments of the present application relate to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure.

Background technique

DRAM (Dynamic Random Access Memory) includes a transistor structure and a capacitor structure. The transistor in the transistor structure is electrically connected to the capacitor in the capacitor structure, so as to read data in the capacitor through the transistor or write data into the capacitor. Magnetic random access memory (MRAM, Magnetic Random AccessMemory) includes a transistor structure and a magnetoresistive tunnel junction (MTJ, Magnetic TunnelJunction) inserted between two metal lines. By controlling the transistor in the transistor structure, the resistance of the magnetoresistive tunnel junction is changed. value, and then read and write data.

In the related art, in order to meet different usage requirements of semiconductor memories, the storage units in the magnetic random access memory and the storage units in the dynamic random access memory are integrated for use. However, in the semiconductor structure, two types of memory cells are usually stacked in a direction perpendicular to the substrate, which makes the process complicated and reduces the production efficiency.

Contents of the invention

According to some embodiments, the present application provides a semiconductor structure, comprising:

a substrate comprising a first storage area, a second storage area and a peripheral area;

The peripheral area is provided on the periphery of the first storage area and the second storage area;

The first storage area is disposed on the periphery of the second storage area, and at least one side of the second storage area is adjacent to the peripheral area.

In some disclosed embodiments, a plurality of discrete active pillars on said first storage area and said second storage area;

a first bit line pattern located under the active pillar in the first storage area, the first bit line pattern extends along the first direction and is arranged at intervals in the second direction;

source line patterns located under the active pillars in the second storage region, the source line patterns extending along the first direction and arranged at intervals in the second direction;

The first direction is perpendicular to the second direction.

In some disclosed embodiments, the line width of the first bit line pattern is equal to the line width of the source line pattern;

The period pitch of the first bit line pattern is equal to the period pitch of the source line pattern.

In some disclosed embodiments, the period pitch of the active pillars in the first storage region in the second direction is equal to the period pitch of the first bit line pattern;

The period interval of the active columns in the second storage area in the second direction is equal to the period interval of the source line pattern.

In some disclosed embodiments, the first word line pattern located in the first storage area, the first word line pattern extends along the second direction and is arranged at intervals in the first direction, the first word line pattern an active pillar intersecting the first bit line pattern in the first storage region;

a second word line pattern located in the second storage area, the second word line pattern extends along the second direction and is arranged at intervals in the first direction, the second word line pattern intersects the source line pattern Active pillars in the second storage area.

In some disclosed embodiments, the line width of the first word line pattern is greater than or equal to the maximum width of the active pillar in the first storage region in the first direction;

The line width of the second word line pattern is greater than or equal to the maximum width of the active pillar in the second storage area in the first direction.

In some disclosed embodiments, the period pitch of the active pillars in the first storage region in the first direction is equal to the period pitch of the first word line pattern;

The period interval of the active pillars in the second storage area in the first direction is equal to the period interval of the second word line pattern.

In some disclosed embodiments, the line width of the first word line pattern is equal to the line width of the second word line pattern;

The period pitch of the first word line pattern is equal to the period pitch of the second word line pattern.

In some disclosed embodiments, a first contact pad pattern located above the active pillar in the first storage region, the first contact pad pattern is arranged corresponding to the active pillar of the first storage region;

A second contact pad pattern located above the active pillars in the second storage area, the second contact pad pattern corresponding to the active pillars in the second storage area.

In some disclosed embodiments, the first contact pad pattern partially overlaps the active pillars of the first storage region; the second contact pad pattern partially overlaps the active pillars of the second storage region.

In some disclosed embodiments, the first contact pad pattern includes a plurality of circular or square patterns arranged at intervals; the second contact pad pattern includes a plurality of circular or square patterns arranged at intervals; the The period pitch of the first contact pad pattern is equal to the period pitch of the second contact pad pattern.

In some disclosed embodiments, the capacitance pattern located above the first contact pad pattern in the first storage area, the capacitance pattern partially overlaps with the first contact pad pattern;

A storage node pattern located above the second contact pad pattern in the second storage area, the storage node pattern partially overlapping the second contact pad pattern.

In some disclosed embodiments, the capacitor pattern includes a plurality of circular or square patterns arranged at intervals; the storage node pattern includes a plurality of circular or square patterns arranged at intervals;

The period interval of the capacitance pattern is equal to the period interval of the storage node pattern.

In some disclosed embodiments, the upper electrode pattern located above the capacitor pattern in the first storage area, the upper electrode pattern overlaps with a plurality of the capacitor patterns; located above the storage node pattern in the second storage area The second bit line pattern extends along the second direction and is arranged at intervals in the first direction, and the second bit line pattern partially overlaps with the storage node pattern.

In some disclosed embodiments, the upper electrode pattern covers all capacitor patterns in the first storage area.

In some disclosed embodiments, the line width of the second bit line pattern is greater than or equal to the width of the storage node pattern in the first direction.

In some disclosed embodiments, the period pitch of the second bit line pattern is equal to the period pitch of the storage node pattern in the first direction.

An embodiment of the present application provides a semiconductor structure, including a substrate, and the substrate includes a first storage area, a second storage area, and a peripheral area; the peripheral area is arranged on the periphery of the first storage area and the second storage area; the first storage area It is arranged on the periphery of the second storage area, and at least one side of the second storage area is adjacent to the peripheral area. Compared with the related art, where two kinds of memory cells in the semiconductor structure are stacked in the direction perpendicular to the substrate, the embodiment of the present application arranges the first memory area and the second memory area in the same plane, which can simplify the process flow , improve the integration of the device.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present application, those of ordinary skill in the art can also obtain other drawings based on these drawings without creative effort.

FIG. 1 is a schematic structural diagram of a substrate in a semiconductor structure provided in an embodiment of the present application;

2 is a schematic structural diagram of a first bit line pattern and a source line pattern in a semiconductor structure provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of an active column in a semiconductor structure provided by an embodiment of the present application;

4 is a schematic structural diagram of a first word line pattern and a second word line pattern in a semiconductor structure provided by an embodiment of the present application;

FIG. 5 is a first structural schematic diagram of the first contact pad pattern and the second contact pad pattern in the semiconductor structure provided by the embodiment of the present application;

FIG. 6 is a second structural schematic diagram of the first contact pad pattern and the second contact pad pattern in the semiconductor structure provided by the embodiment of the present application;

FIG. 7 is a schematic structural diagram of a capacitor pattern and a storage node pattern in a semiconductor structure provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of an upper electrode pattern and a second bit line pattern in a semiconductor structure provided by an embodiment of the present application.

Detailed ways

In order to make the above objects, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

An embodiment of the present application provides a semiconductor structure, as shown in FIG. 1 , including: a substrate 10 , and the substrate 10 includes a first storage area 11 , a second storage area 12 and a peripheral area 13 . In this embodiment, the first storage area 11 is used to form the first storage structure, and the second storage area 12 is used to form the second storage structure. The storage principle of the first storage structure is different from that of the second storage structure. The first The storage structure may have storage units of DRAM, for example, and the second storage structure may have storage units of Magnetic Random Access Memory, for example. By forming the first storage structure and the second storage structure with different storage characteristics on the same substrate 10, it is beneficial to further improve the flexible storage performance and fast access performance of the semiconductor structure.

Exemplarily, the pattern of the first storage area 11 and the pattern of the second storage area 12 can be rectangular, and the second storage area 12 is located in the first storage area 11, that is, the first storage area 11 is set in the second Periphery of storage area 12. The pattern of the peripheral area 13 can also be a rectangle, for example, and the first storage area 11 and the second storage area 12 are all located in the peripheral area 13, that is, the peripheral area 13 is arranged on the periphery of the first storage area 11 and the second storage area 12 .

In this embodiment, at least one side of the second storage area 12 is adjacent to the peripheral area 13, so as to reduce the connection distance between the second storage area 12 and the peripheral area 13, and reduce the distance between the second storage area 12 and the peripheral area 13. resistance between. In this embodiment, one side of the first storage area 11 is in line with one side of the second storage area 12, and in the second storage area 12, the side of the first storage area 11 is in line with the peripheral area 13. adjacent. As shown in the figure, since the first storage area 11 is located in the peripheral area 13 , the pattern of the second storage area 12 is adjacent to the peripheral area 13 . Similarly, the first storage area 11 is adjacent to the peripheral area 13 , which can reduce the wiring distance between the first storage area 11 and the peripheral area 13 and reduce the resistance between the first storage area 11 and the peripheral area 13 .

Of course, in some other embodiments, the relative positions of the first storage area 11 , the second storage area 12 and the peripheral area 13 can also be adjusted according to actual needs, which is not specifically limited in this embodiment.

The embodiment of the present application provides a semiconductor structure, including a substrate 10, and the substrate 10 includes a first storage area 11, a second storage area 12, and a peripheral area 13; the peripheral area 13 is provided in the first storage area 11 and the second storage area 12; the first storage area 11 is located at the periphery of the second storage area 12, and at least one side of the second storage area 12 is adjacent to the peripheral area 13. Compared with the related art, where two types of memory cells in the semiconductor structure are stacked in a direction perpendicular to the substrate 10, the embodiment of the present application arranges the first memory area 11 and the second memory area 12 in the same plane, which can Simplify the process flow and improve the integration of the device.

Further, since the first storage area 11 and the second storage area 12 are arranged in the same plane, in the process of forming the first storage structure and the second storage structure, the first storage area 11 and the second storage area 12 can share the same plane. The photomask is beneficial to reduce the production cost.

Referring to FIG. 2 and FIG. 3 , the semiconductor structure further includes a plurality of discrete active pillars 31 located on the first storage region 11 and the second storage region 12 , and the first bit below the active pillars 31 in the first storage region 11 line pattern 21 , and the source line pattern 22 located under the active pillar 31 in the second storage region 12 .

As shown in FIG. 2 , the first direction is the vertical direction in the illustrated position, the second direction is the horizontal direction in the illustrated position, and the first direction is perpendicular to the second direction.

Exemplarily, the first bit line pattern 21 may include a plurality of strip patterns extending along the first direction, and the intervals between adjacent strip patterns in the second direction are equal. The strip pattern may be, for example, a rectangle, and a plurality of rectangles extend along the first direction and are arranged at equal intervals along the second direction. The line width W1 of the first bit line pattern 21 is the width of the strip pattern in the second direction. In the second direction, the distance between the same side of two adjacent strip patterns is the period interval D1 of the first bit line pattern 21 .

Exemplarily, the source line pattern 22 may include a plurality of strip patterns extending along the first direction, and the intervals between adjacent strip patterns in the second direction are equal. The strip pattern may be, for example, a rectangle, and a plurality of rectangles extend along the first direction and are arranged at intervals along the second direction. The line width W2 of the source line pattern 22 is the width of the strip pattern in the second direction. In the second direction, the distance between the same side of two adjacent strip patterns is the periodic interval D2 of the source line patterns 22 .

In this embodiment, the line width W1 of the first bit line pattern 21 may be equal to the line width W2 of the source line pattern 22, and the period interval D1 of the first bit line pattern 21 may be equal to the period interval D2 of the source line pattern 22, so that Making the mask patterns defined by the first storage area 11 and the second storage area 12 the same is conducive to improving resolution and reducing process errors in the manufacturing process. Furthermore, in the process of forming the first bit line and the source line, the first storage area 11 and the second storage area 12 can share the same mask, which is beneficial to reduce the manufacturing cost.

As shown in FIG. 3 , the active column 31 can be rectangular, and of course, in some other embodiments, the active column 31 can also be in other shapes, such as circular, elliptical and so on. Exemplarily, in this embodiment, in the first storage area 11, the line width W3 of the active pillar 31 in the second direction may be equal to the line width W1 of the first bit line pattern 21, and in the second storage area 12 The line width W4 of the active column 31 in the second direction may also be equal to the line width W2 of the source line pattern 22, so that there is a sufficient overlapping area between the active column 31 and the first bit line pattern 21, and there is There is a sufficient overlapping area between the source pillars 31 and the source line patterns 22 , which is conducive to sufficient contact between the formed active pillars 31 and the source lines formed by the source line patterns 22 , and reduces the contact resistance.

In this embodiment, in the second direction in the first storage area 11, the distance between the same sides of two adjacent rectangles is the distance between the active pillars 31 in the second direction in the first storage area 11. Periodic spacing D3; in the second direction in the second storage area 12, the distance between the same sides of two adjacent rectangles is the period of the active column 31 in the second direction in the second storage area 12 Spacing D4. The periodic spacing D3 of the active columns 31 in the second direction in the first storage area 11 may be equal to the periodic spacing D1 of the first bit line pattern 21; the periodic spacing of the active columns 31 in the second storage area 12 in the second direction D4 can be equal to the period interval D2 of the source line pattern 22, so as to improve the integration degree of the devices formed in the first storage area 11 and the second storage area 12, and further, it can also improve the first storage area 11 and the second storage area. 12 The density of devices formed per unit area.

Continuing to refer to FIG. 3 , in this embodiment, in the first direction in the first storage area 11 , the distance between the same sides of two adjacent rectangles is the active column 31 in the first storage area 11 Periodic spacing D5 in the first direction; in the first direction in the second storage area 12, the distance between the same sides of two adjacent rectangles is the first active column 31 in the second storage area 12 Periodic pitch D6 in one direction. The structure of the active pillars 31 in the first storage area 11 and the second storage area 12 is the same, and the active pillars 31 may include a plurality of squares distributed in an array. That is, in the first storage area 11 and the second storage area 12, the periodic interval D3 of the active pillars 31 in the second direction may also be equal to the periodic interval D4 of the active pillars 31 in the second direction. The periodic spacing D5 of the active columns 31 in one direction can also be equal to the periodic spacing D7 of the active columns 31 in the second direction, so that the mask patterns defined by the first storage area 11 and the second storage area 12 are the same, which is beneficial to Improve resolution and reduce process errors in the process.

Referring to FIG. 4 , the semiconductor structure provided by the embodiment of the present application may further include a first word line pattern 312 located in the first storage area 11 and a second word line pattern 322 located in the second storage area 12 . Wherein, the first word line pattern 312 is located above the first bit line pattern 21 , and the second word line pattern 322 is located above the source line pattern 22 .

Exemplarily, the first word line pattern 312 includes a plurality of strip patterns extending along the second direction, and the intervals between adjacent strip patterns in the first direction are equal. The strip pattern may be, for example, a rectangle, and a plurality of rectangles extend along the second direction and are arranged at intervals along the first direction. As shown in the figure, the first word line pattern 312 intersects with the first bit line pattern 21 on the active column 31 of the first storage area 11, so that the active column 31 of the first storage area 11 can be connected to the first word line respectively. The pattern 312 has an overlapping portion with the first bit line pattern 21 .

Optionally, the line width W5 of the first word line pattern 312 is the width of the first word line pattern 312 in the first direction. The line width W5 of the first word line pattern 312 may be greater than or equal to the maximum width of the active column 31 in the first storage region 11 in the first direction, so that the active column 31 is respectively connected to the first word line pattern 312 and the first The bit line pattern 21 has a sufficient overlapping area, which is conducive to sufficient contact between the first word line formed by the first word line pattern 312 and the first bit line formed by the first bit line pattern 21, and the contact resistance is reduced, thereby ensuring the formation of performance of the device structure.

Exemplarily, the second word line pattern 322 includes a plurality of strip patterns extending along the second direction, and the intervals between adjacent strip patterns in the first direction are equal. The strip pattern may be, for example, a rectangle, and a plurality of rectangles extend along the second direction and are arranged at intervals along the first direction. As shown in the figure, the second word line pattern 322 intersects the source line pattern 22 with the active column 31 of the second storage area 12, so that the active column 31 of the second storage area 12 can be connected with the second word line pattern respectively. 322 has an overlapping portion with the source line pattern 22 .

Optionally, the line width W6 of the second word line pattern 322 is the width of the second word line pattern 322 in the first direction. The line width W6 of the second word line pattern 322 may be greater than or equal to the maximum width of the active column 31 in the second storage area 12 in the first direction, so that the active column 31 is connected to the second word line pattern 322 and the source electrode respectively. The line pattern 22 has a sufficient overlapping area, which is conducive to sufficient contact between the second word line formed by the second word line pattern 322 and the active pillar 31 , and the contact resistance is reduced to ensure the performance of the formed device structure.

In this embodiment, in the first direction, the distance between the same side of the adjacent stripe pattern in the first storage area 11 is the period interval D7 of the first word line pattern 312, and in the first storage area 11 The periodic interval D5 of the active columns 31 in the first direction may be equal to the periodic interval D7 of the first word line pattern 312, so that in the first storage area 11, between adjacent stripe patterns of the first word line pattern 312 No overlap occurs. In the first direction, the distance between the same side of adjacent strip patterns in the second storage area 12 is the period interval D8 of the second word line patterns 322 . The periodic spacing D6 of the active columns 31 in the first direction in the second storage area 12 can be equal to the periodic spacing D8 of the second word line pattern 322, so that in the second storage area 12, the adjacent second word line patterns 322 There is no overlap between the strip patterns.

Further, the line width W5 of the first word line pattern 312 can be equal to the line width W6 of the second word line pattern 322; the period interval D7 of the first word line pattern 312 can be equal to the period interval D8 of the second word line pattern 322, to Making the mask patterns defined by the first storage area 11 and the second storage area 12 the same is conducive to improving resolution and reducing process errors in the manufacturing process.

Referring to FIG. 5 and FIG. 6, the semiconductor structure provided by the embodiment of the present application may further include a first contact pad pattern 41 located above the active pillar 31 in the first storage region 11, and a first contact pad pattern 41 located above the active pillar 31 in the second storage region 12. The upper second contact pad pattern 42 .

In this embodiment, the first contact pad pattern 41 may include a plurality of circular or square patterns arranged at intervals; the second contact pad pattern 42 may include a plurality of circular or square patterns arranged at intervals. 5 and 6, the first contact pad pattern 41 may include a plurality of square patterns, for example, and the plurality of square patterns are arranged in an array, so that the first contact pad pattern 41 and the corresponding active pads in the first storage area 11 The columns 31 overlap; the second contact pad pattern 42 may also include a plurality of square patterns, for example, and the plurality of square patterns are arranged in an array so that the second contact pad pattern 42 overlaps with the corresponding active columns 31 in the second storage area 12 .

In this embodiment, the periodic pitch D9 of the first contact pad is the distance between the center points of two adjacent first contact pads, and the periodic pitch D10 of the second contact pad is the center point of two adjacent second contact pads. the distance between. The period interval D9 of the first contact pad pattern 41 can be equal to the period interval D10 of the second contact pad pattern 42, so that the mask patterns defined by the first storage area 11 and the second storage area 12 are the same, which is beneficial to improve resolution, Reduce the process error in the production process.

In an embodiment of the present application, the first contact pad pattern 41 is disposed corresponding to the active pillar 31 of the first storage region 11 . As shown in FIG. 5 , the first contact pad pattern 41 has the same shape as the active column 31 of the first storage area 11 and can completely overlap so that the first contact pad pattern 41 and the active column of the first storage area 11 31 have the largest overlapping area. Similarly, the second contact pad pattern 42 is disposed corresponding to the active pillar 31 of the second storage region 12 . As shown in FIG. 5 , the second contact pad pattern 42 has the same shape as the active column 31 of the second storage area 12 , and can be completely overlapped so that the second contact pad pattern 42 has the same shape as the active column 31 of the second storage area 12 . 31 have the largest overlapping area.

In another embodiment of the present application, the first contact pad pattern 41 partially overlaps the active pillar 31 of the first storage region 11 . As shown in FIG. 6 , the first contact pad pattern 41 and the active column 31 of the first storage area 11 are arranged in a dislocation, and the overlapping portion of the first contact pad pattern 41 and the active column 31 of the first storage area 11 It is located at the lower right part of the active column 31 . Similarly, the second contact pad pattern 42 partially overlaps the active column 31 of the second storage area 12, and the second contact pad pattern 42 is arranged in a misalignment with the active column 31 of the second storage area 12, and the second The overlapping portion of the contact pad pattern 42 and the active pillar 31 of the second memory region 12 is located at the upper left portion of the active pillar 31 . Through the dislocation arrangement described above, the densest packing of devices can be realized and the density of devices can be increased. Of course, in some other embodiments, the positions of the first contact pad pattern 41 and the second contact pad pattern 42 can also be set according to actual needs.

The semiconductor structure provided by the embodiment of the present application further includes a capacitor structure and a storage node structure, wherein the capacitor structure is located above the first contact pad pattern 41 in the first storage region 11, and the storage node pattern 52 is located on the second contact pad pattern 52 in the second storage region 12. above the contact pad pattern 42 .

The capacitor pattern 51 may include a plurality of circular or square patterns arranged at intervals; the storage node pattern 52 may include a plurality of circular or square patterns arranged at intervals. Referring to FIG. 7, the capacitance pattern 51 may include, for example, a plurality of circular patterns, and the plurality of circular patterns are arranged in an array so that the capacitance pattern 51 overlaps with the first contact pad pattern 41; the storage node pattern 52 may also include, for example, multiple and a plurality of circular patterns are arranged in an array so that the storage node pattern 52 overlaps with the second contact pad pattern 42 .

In this embodiment, the periodic interval D11 of the capacitor pattern 51 is the distance between the center points of two adjacent capacitor patterns 51, and the periodic interval D12 of the storage node pattern 52 is the distance between the center points of two adjacent storage node patterns 52. distance. The period interval D11 of the capacitance pattern 51 can be equal to the period interval D12 of the storage node pattern 52, so that the mask patterns defined by the first storage area 11 and the second storage area 12 are the same, which is beneficial to improve the resolution and reduce the manufacturing process. Process error.

Optionally, the capacitance pattern 51 may partially overlap with the first contact pad pattern 41 ; the storage node pattern 52 may partially overlap with the second contact pad pattern 42 . Continuing to refer to FIG. 7, the capacitive pattern 51 can be located in the first contact pad pattern 41, and the center point of the capacitive pattern 51 coincides with the center point of the first contact pad pattern 41, so that between the capacitive pattern 51 and the first contact pad pattern 41 Having a sufficient overlapping area facilitates sufficient contact between the capacitor formed by the capacitor pattern 51 and the first contact pad formed by the first contact pad pattern 41 . Similarly, the storage node pattern 52 can be located in the second contact pad pattern 42, and the center point of the storage node pattern 52 coincides with the center point of the second contact pad pattern 42, so that the distance between the storage node pattern 52 and the second contact pad pattern 42 There is a sufficient overlapping area between them, which is conducive to sufficient contact between the storage node formed by the storage node pattern 52 and the second contact pad formed by the second contact pad pattern 42 , and the contact resistance is reduced.

It is worth noting that the storage node pattern 52 includes a completely overlapping magnetic storage pattern and a contact pattern, wherein the contact pattern is located above the magnetic storage pattern, and the magnetic storage pattern and the contact pattern have exactly the same shape.

The semiconductor structure provided by the embodiment of the present application further includes an upper electrode pattern 61 and a second bit line pattern 62, wherein the upper electrode pattern 61 may be located above the capacitor pattern 51 in the first storage region 11, and the second bit line pattern 62 may be located Above the node pattern 52 is stored in the second storage region 12 .

Exemplarily, the upper electrode pattern 61 overlaps with a plurality of capacitor patterns 51 . The upper electrode pattern 61 is rectangular, and the width of the upper electrode pattern 61 in the first direction and the width in the second direction are greater than the period interval of the capacitor pattern 51, so that the upper electrode pattern 61 can overlap with a plurality of capacitor patterns 51, Furthermore, multiple capacitors formed by the capacitor pattern 51 can be connected together through the upper electrode formed by the upper electrode pattern 61 .

As shown in Figure 8, the upper electrode pattern 61 can cover all the capacitor patterns 51 in the first storage area 11, which is beneficial to further increase the overlapping area between the capacitor pattern 51 and the upper electrode pattern 61, and further facilitates the formation of the upper electrode pattern 61. There is sufficient contact between the upper electrode and the multiple capacitors formed by the capacitor pattern 51 to prevent the capacitors from collapsing.

Exemplarily, the second bit line pattern 62 includes a plurality of strip patterns extending along the second direction, and the intervals between the plurality of strip patterns are equal in the first direction. The strip pattern may be, for example, a rectangle, and a plurality of rectangles extend along the second direction and are arranged at intervals along the first direction. The second bit line pattern 62 may partially overlap the storage node pattern 52 so that the second bit line formed by the second bit line pattern 62 can contact the storage node formed by the storage node pattern 52 .

Exemplarily, the line width W8 of the second bit line pattern 62 is the width of the second bit line pattern 62 in the first direction, and the line width W8 of the second bit line pattern 62 may be greater than or equal to the width of the storage node pattern 52 in the first direction. The upward width W7 is such that there is a sufficient overlapping area between the storage node pattern 52 and the second bit line pattern 62, thereby facilitating the connection between the storage node formed by the storage node pattern 52 and the second bit line formed by the second bit line pattern 62. Full contact between them, and the contact resistance is reduced.

Exemplarily, the period distance D13 of the second bit line pattern 62 is the distance between the same side of two adjacent second bit line patterns 62, and the period distance D13 of the second bit line pattern 62 may be equal to that of the storage node pattern 52 at The period interval D13 in the first direction is such that in the second storage area 12 , the adjacent stripe patterns of the second bit line pattern 62 do not overlap.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, only the division of the above-mentioned functional modules is used as an example for illustration. The internal structure of the system is divided into different functional modules to complete all or part of the functions described above. For the specific working process of the device described above, reference may be made to the corresponding process in the foregoing method embodiments, and details are not repeated here.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting them; although the application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present application. scope.

Claims (17)

1. A semiconductor structure, characterized in that, comprising: a substrate comprising a first storage area, a second storage area and a peripheral area; The peripheral area is provided on the periphery of the first storage area and the second storage area; The first storage area is disposed on the periphery of the second storage area, and at least one side of the second storage area is adjacent to the peripheral area. 2. The semiconductor structure of claim 1, wherein a plurality of discrete active pillars over said first storage area and said second storage area; a first bit line pattern located under the active pillar in the first storage area, the first bit line pattern extends along the first direction and is arranged at intervals in the second direction; source line patterns located under the active pillars in the second storage region, the source line patterns extending along the first direction and arranged at intervals in the second direction; The first direction is perpendicular to the second direction. 3. The semiconductor structure of claim 2, wherein The line width of the first bit line pattern is equal to the line width of the source line pattern; The period pitch of the first bit line pattern is equal to the period pitch of the source line pattern. 4. The semiconductor structure according to claim 2 or 3, characterized in that, The periodic pitch of the active pillars in the second direction in the first storage area is equal to the periodic pitch of the first bit line pattern; The period interval of the active columns in the second storage area in the second direction is equal to the period interval of the source line pattern. 5. The semiconductor structure according to claim 2, characterized in that, A first word line pattern located in the first storage area, the first word line pattern extending along the second direction and arranged at intervals in the first direction, the first word line pattern and the first bit line pattern active pillars intersecting the first storage region; a second word line pattern located in the second storage area, the second word line pattern extends along the second direction and is arranged at intervals in the first direction, the second word line pattern intersects the source line pattern Active pillars in the second storage area. 6. The semiconductor structure of claim 5, wherein The line width of the first word line pattern is greater than or equal to the maximum width of the active pillar in the first storage region in the first direction; The line width of the second word line pattern is greater than or equal to the maximum width of the active pillar in the second storage area in the first direction. 7. The semiconductor structure according to claim 5 or 6, characterized in that, The periodic pitch of the active pillars in the first storage area in the first direction is equal to the periodic pitch of the first word line pattern; The period interval of the active pillars in the second storage area in the first direction is equal to the period interval of the second word line pattern. 8. The semiconductor structure according to claim 5 or 6, characterized in that, The line width of the first word line pattern is equal to the line width of the second word line pattern; The period pitch of the first word line pattern is equal to the period pitch of the second word line pattern. 9. The semiconductor structure of claim 2, wherein a first contact pad pattern located above the active pillars in the first storage area, the first contact pad pattern corresponding to the active pillars of the first storage area; A second contact pad pattern located above the active pillars in the second storage area, the second contact pad pattern corresponding to the active pillars in the second storage area. 10. The semiconductor structure of claim 9, wherein The first contact pad pattern partially overlaps the active column of the first storage area; the second contact pad pattern partially overlaps the active column of the second storage area. 11. The semiconductor structure according to claim 9 or 10, characterized in that, The first contact pad pattern includes a plurality of circular or square patterns arranged at intervals; the second contact pad pattern includes a plurality of circular or square patterns arranged at intervals; The period pitch of the first contact pad pattern is equal to the period pitch of the second contact pad pattern. 12. The semiconductor structure of claim 9, wherein a capacitance pattern located above a first contact pad pattern in the first storage area, the capacitance pattern partially overlapping the first contact pad pattern; A storage node pattern located above the second contact pad pattern in the second storage area, the storage node pattern partially overlapping the second contact pad pattern. 13. The semiconductor structure according to claim 12, wherein the capacitance pattern comprises a plurality of circular or square patterns arranged at intervals; the storage node pattern comprises a plurality of circular or square patterns arranged at intervals ; The period interval of the capacitance pattern is equal to the period interval of the storage node pattern. 14. The semiconductor structure of claim 12, wherein an upper electrode pattern located above the capacitance pattern in the first storage area, the upper electrode pattern overlapping with a plurality of the capacitance patterns; A second bit line pattern located above the storage node pattern in the second storage area, the second bit line pattern extending along the second direction and arranged at intervals in the first direction, the second bit line pattern and the storage node pattern Node patterns partially overlap. 15. The semiconductor structure of claim 14, wherein The upper electrode pattern covers all capacitor patterns in the first storage area. 16. The semiconductor structure of claim 14, wherein The line width of the second bit line pattern is greater than or equal to the width of the storage node pattern in the first direction. 17. The semiconductor structure of claim 14, wherein The period pitch of the second bit line pattern is equal to the period pitch of the storage node pattern in the first direction.

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