CN116230761B - Two-dimensional reconfigurable transistor, preparation method thereof and regulation and control method - Google Patents

Abstract

The invention provides a two-dimensional reconfigurable transistor and a preparation method and a regulation method thereof, wherein the transistor comprises an insulating substrate, a source electrode, a bottom gate dielectric layer, a two-dimensional semiconductor layer, a top gate dielectric layer, a drain electrode and a top gate electrode; the source electrode and the bottom gate electrode are positioned above the insulating substrate, the bottom gate dielectric layer covers the bottom gate electrode, the two-dimensional semiconductor layer is positioned above the bottom gate dielectric layer and is in contact with the source electrode, the top gate dielectric layer covers the two-dimensional semiconductor layer, the drain electrode is in contact with the two-dimensional semiconductor layer, and the top gate electrode is positioned above the top gate dielectric layer and is not in contact with the drain electrode. When the two-dimensional reconfigurable transistor regulated by the vertical double grid voltage is applied to a future integrated circuit, a large number of transistors can be saved under the same calculation force condition, the occupied area of the integrated circuit is reduced, the cost of the integrated circuit and the whole energy consumption are reduced, and the development requirements of applications such as artificial intelligence, the Internet of things and the like in the future are met.

Description

A two-dimensional reconfigurable transistor and its preparation method and control method

Technical Field

The present invention relates to the technical field of two-dimensional semiconductor materials, and in particular to a two-dimensional reconfigurable transistor and a preparation method and a control method thereof.

Background technique

With the vigorous development of emerging electronic application industries such as artificial intelligence, big data, and edge computing, the demand for efficient information processing has become more urgent. Reconfigurable technology that can significantly improve the utilization rate of electronic components provides a possible solution. However, since traditional silicon-based field-effect transistors can only have a single electrical characteristic (N-type/P-type) once successfully prepared, their field-effect characteristics can no longer be dynamically converted through electrical operations. A large amount of transistor resources are required to build a complex circuit structure in order to obtain reconfigurable and efficient computing capabilities, which increases the overall footprint and power consumption of the circuit. Therefore, it is urgent to develop new reconfigurable technologies to reduce the number of transistors required for functional modules and achieve more efficient computing capabilities.

Two-dimensional semiconductor materials have become one of the most anticipated basic electronic materials in the post-Moore era due to their adjustable band gap, atomic-level thickness and no dangling bonds. Unlike traditional solutions, two-dimensional materials have unique upper and lower dual-surface channel layered transport characteristics, that is, by applying gate control voltage on the upper and lower surfaces of the channel of a single transistor at the same time, "one person does the work of two people", reducing functional circuit redundancy, improving transistor utilization efficiency, and achieving higher integration density. In addition, the unique bipolar field effect characteristics of two-dimensional materials and the controllable polarity change characteristics of gate voltage enable a single two-dimensional transistor to achieve a variety of switching characteristics under voltage operation, demonstrating its application potential in the field of reconfigurable technology. The functional circuit integrated with this reconfigurable transistor can further reduce the number of redundant transistors. However, there is currently no report on obtaining a two-dimensional reconfigurable transistor through vertical dual gate voltage operation.

Summary of the invention

In order to solve the above technical problems, the present invention proposes a two-dimensional reconfigurable transistor and a preparation method and a control method thereof, which independently controls the source contact and drain contact polarity through the upper and lower double gates to obtain a variety of switching characteristics such as P-type field effect transistors, N-type field effect transistors, forward-biased diodes, and reverse-biased diodes. The preparation method provided by the present invention avoids the problem of unstable material polarity caused by chemical doping, physical doping, defect control and other means, and proposes a simple, feasible, lossless and reversible new way to construct a high-area efficiency reconfigurable transistor.

To achieve the above object, the present invention provides a two-dimensional reconfigurable transistor, comprising:

An insulating substrate, a source, a bottom gate electrode, a bottom gate dielectric layer, a two-dimensional semiconductor layer, a top gate dielectric layer, a drain and a top gate electrode; wherein the source and the bottom gate electrode are located above the insulating substrate, the bottom gate dielectric layer covers the bottom gate electrode and is not in contact with the source, the two-dimensional semiconductor layer is located above the bottom gate dielectric layer and is in contact with the source, the top gate dielectric layer covers the two-dimensional semiconductor layer, the drain is in contact with the two-dimensional semiconductor layer, and the top gate electrode is located above the top gate dielectric layer and is not in contact with the drain.

Preferably, the two-dimensional semiconductor layer is made of a two-dimensional layered material having bipolar field effect characteristics, and the thickness of the two-dimensional semiconductor layer is 2-10 nm.

Preferably, the insulating substrate is a silicon wafer with an oxide layer, a flexible insulating PET or a sapphire substrate.

Preferably, the materials of the source, bottom gate electrode, drain and top gate electrode include metal electrode materials, two-dimensional semi-metal materials, with a thickness of 20-50nm, and the materials of the bottom gate dielectric layer and the top gate dielectric layer are two-dimensional layered boron nitride, silicon oxide, aluminum oxide or hafnium oxide, with a thickness of 20-40nm.

In order to achieve the above object, the present invention also provides a method for preparing a two-dimensional reconfigurable transistor, comprising:

Depositing source and bottom gate electrodes based on an insulating substrate;

Depositing a bottom gate dielectric layer on the bottom gate electrode to achieve full coverage;

Placing a two-dimensional semiconductor layer above the bottom gate dielectric layer and in direct contact with the source electrode;

Depositing a top gate dielectric layer on the two-dimensional semiconductor layer for partial coverage;

A top gate electrode is deposited on the top gate dielectric layer, and a drain electrode is deposited on the two-dimensional semiconductor layer not covering the top gate dielectric layer, thereby completing the preparation of a two-dimensional reconfigurable transistor controlled by vertical dual gate electrodes.

Preferably, the process of performing the deposition comprises:

The patterning process is performed using an electron beam exposure process or an ultraviolet exposure process, and then the deposition is completed using a thermal evaporation process.

Preferably, the entire covering or the partial covering of the dielectric layer is performed based on an atomic deposition process.

Preferably, a dry transfer process is used when placing the two-dimensional semiconductor layer above the bottom gate dielectric layer.

In order to achieve the above object, the present invention also provides a control method for a two-dimensional reconfigurable transistor, comprising:

When the two-dimensional reconfigurable transistor is in operation, the drain provides a bias voltage to the voltage application terminal, and the source is grounded, then the combination of gate electrodes includes: applying a positive voltage to both the bottom gate electrode and the top gate electrode, applying a negative voltage to both the bottom gate electrode and the top gate electrode, applying a positive voltage to the bottom gate electrode and a negative voltage to the top gate electrode, and applying a negative voltage to the bottom gate electrode and a positive voltage to the top gate electrode;

When a positive voltage is applied to the drain, electrons flow from the source to the drain and holes flow from the drain to the source; when a negative voltage is applied to the source, electrons flow from the drain to the source and holes flow from the source to the drain;

If a positive voltage is applied to the bottom gate electrode, the drain electrode becomes an N-type contact, which hinders hole transmission; if a negative voltage is applied to the bottom gate electrode, the drain electrode becomes a P-type contact, which hinders electron transmission;

If a positive voltage is applied to the top gate electrode, the source electrode behaves as an N-type contact; if a negative voltage is applied to the top gate electrode, the source electrode behaves as a P-type contact.

Compared with the prior art, the present invention has the following advantages and technical effects:

When the two-dimensional reconfigurable transistor with vertical dual-gate voltage control of the present invention is applied to future integrated circuits, under the same computing power conditions, a large number of transistors can be saved, the area occupied by the integrated circuit can be reduced, the cost of the integrated circuit and the overall energy consumption can be reduced, and the development needs of future artificial intelligence, the Internet of Things and other applications can be met;

The control method of the vertical dual-gate voltage-controlled two-dimensional reconfigurable transistor applied in the present invention provides a new design scheme for digital circuits of a new architecture, realizing "one person doing the work of multiple people", which can greatly reduce the consumption of transistor resources and is conducive to the miniaturization of future electronic products;

The preparation method provided by the present invention is compatible with existing semiconductor technology and has universal applicability.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

FIG1 is a schematic diagram of a two-dimensional reconfigurable transistor structure with vertical dual-gate voltage control according to an embodiment of the present invention;

2 is a schematic diagram of energy bands of source and drain metals in contact with tungsten diselenide channel materials under positive and negative bias conditions when positive voltages are applied to both the bottom gate electrode and the top gate electrode of an embodiment of the present invention;

3 is a schematic diagram of energy bands of source and drain metals in contact with tungsten diselenide channel materials under positive and negative bias conditions when negative voltages are applied to both the bottom gate electrode and the top gate electrode of an embodiment of the present invention;

4 is a schematic diagram of energy bands of source and drain metals in contact with tungsten diselenide channel materials under positive and negative bias conditions when a positive voltage is applied to the bottom gate electrode and a negative voltage is applied to the top gate electrode according to an embodiment of the present invention;

5 is a schematic diagram of energy bands of source and drain metals in contact with tungsten diselenide channel materials under positive and negative bias conditions when a negative voltage is applied to the bottom gate electrode and a positive voltage is applied to the top gate electrode according to an embodiment of the present invention;

6 is a volt-ampere characteristic curve of the embodiment of the present invention under four combinations of voltages applied to the bottom gate electrode and the top gate electrode: both are positive, both are negative, one is positive and the other is negative, and one is negative and the other is positive;

Among them, 1. insulating substrate, 2. source, 3. two-dimensional semiconductor layer, 4. top gate dielectric layer, 5. top gate electrode, 6. drain, 7. bottom gate dielectric layer, 8. bottom gate electrode.

Detailed ways

It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

The structural schematic diagram of the two-dimensional reconfigurable transistor of the present invention is shown in Figure 1, wherein 1 is an insulating substrate, 2 is a source, 3 is a two-dimensional semiconductor layer, 4 is a top gate dielectric layer, 5 is a top gate electrode, 6 is a drain, 7 is a bottom gate dielectric layer, and 8 is a bottom gate electrode.

The source 2 and the bottom gate electrode 8 are located above the insulating substrate 1, the bottom gate dielectric layer 7 only completely covers the bottom gate electrode 8, the bottom gate dielectric layer 7 is an "L"-shaped structure, the long sides of which are in contact with the two-dimensional semiconductor layer 3 and the bottom gate electrode 8 respectively, and the long sides are shorter than the two-dimensional semiconductor layer 3, and the short sides of which are in contact with the source 2 and the bottom gate electrode 8 respectively; the two-dimensional semiconductor layer 3 is located above the bottom gate dielectric layer 7 and is in contact with the source 2, the top gate dielectric layer 4 partially covers the two-dimensional semiconductor layer 3 and leaves a drain contact area, the drain 6 is in contact with the two-dimensional semiconductor layer 3, the top gate electrode 5 is located above the top gate dielectric layer 4 and is not in contact with the drain 6, the top gate dielectric layer 4 is an "L"-shaped structure, the long sides of which are in contact with the top gate electrode 5 and the two-dimensional semiconductor layer 3 respectively, and the short sides are in contact with the top gate electrode 5 and the drain 6 respectively. It is worth noting that the top gate electrode 5 does not participate in regulating the drain contact area, and the bottom gate electrode 8 does not participate in regulating the source contact area.

This embodiment provides a vertical dual-gate voltage-controlled tungsten diselenide reconfigurable transistor, and the specific preparation steps are as follows:

(1) Pre-deposition of source electrode 2 and bottom gate electrode 8: a layer of PMMA colloid is spin-coated on insulating substrate 1 and dried at 180°C for 1 min. Electron beam exposure technology is used for patterning, and metal electrodes are deposited by thermal evaporation process. The electrode material is pure gold. Pre-deposition of source electrode and bottom gate electrode is completed. The thickness is 30 nm.

(2) Deposition of bottom gate dielectric layer 7: spin-coat PMMA colloid on the substrate with source 2 and bottom gate electrode 8 and dry at 180° C. for 1 min, perform patterning using electron beam overlay technology, and grow bottom gate dielectric layer 7 using atomic layer deposition process to achieve full coverage of bottom gate electrode 8 and ensure that source 2 is exposed. The dielectric layer material is hafnium oxide, and the thickness of bottom gate dielectric layer 7 is 25 nm.

(3) Preparing a few-layer tungsten diselenide nanosheet by mechanical stripping: stick 3M blue film tape on the tungsten diselenide crystal and slowly tear it off. At this time, a thick multi-layer tungsten diselenide sample remains on the tape. Then, gently fold it in half 2-3 times to thin the thickness of the tungsten diselenide sample to obtain a molybdenum diselenide sample master tape. Then, gently press the thinned tungsten diselenide master tape on the silicon wafer and slowly peel it off to leave a few-layer tungsten diselenide nanosheet on the silicon wafer. Repeat the previous step many times to obtain boron nitride nanosheets of different thicknesses. The thickness of the tungsten diselenide sample selected in this embodiment is 3nm;

(4) Assembly of the two-dimensional semiconductor layer 3: Spin-coat PPC colloid on a silicon wafer with a few layers of tungsten diselenide sample, dry at 100°C for 1 min to form a PPC film with a thickness of 500 nm, slowly peel off the PPC film with the tungsten diselenide sample from the silicon wafer with the help of 3M tape, and fix it to a customized carrier plate with PDMS. Finally, use a precise transfer platform to accurately stack the tungsten diselenide sample on the PPC film on the upper surface of the bottom gate dielectric layer 7 and form contact with the source electrode 2, completing the assembly of the two-dimensional semiconductor layer 3;

(5) Deposition of the top gate dielectric layer 4: The top gate dielectric layer 4 is grown on the upper surface of the two-dimensional semiconductor layer 3 by the same atomic layer deposition process as in step (2) and a contact area between the drain electrode 6 and the two-dimensional semiconductor layer 3 is reserved to complete partial coverage. The dielectric layer material is hafnium oxide and has a thickness of 25 nm.

(6) Deposition of top gate electrode 5 and drain electrode 6: The bottom gate electrode 5 is deposited on the upper surface of the top gate dielectric layer using the same process as step (1), and the drain electrode 6 is deposited at the reserved drain contact area above the two-dimensional semiconductor layer 3. The electrode materials are all pure gold with a thickness of 30 nm, and finally the preparation of a vertical dual-gate voltage-controlled tungsten diselenide reconfigurable transistor is completed.

When the device provided in this embodiment is in operation, the drain 6 is connected to a voltage source to apply a bias voltage, and the source 2 is always grounded; the bottom gate electrode 8 and the top gate electrode 5 are connected to two independent voltage sources to apply gate voltages to control the contact polarities of the drain and source, respectively, including the following specific control methods:

(1) When a positive bias is applied to the drain, electrons flow from the source to the drain and holes flow from the drain to the source, and the Fermi level of the drain metal moves downward relative to the source metal; when a negative bias is applied to the drain, electrons flow from the drain to the source and holes flow from the source to the drain, and the Fermi level of the drain metal moves upward relative to the source metal;

(2) FIG. 2 is a schematic diagram of the energy bands of the device in contact between the source and drain metals and the tungsten diselenide channel material under positive and negative bias when positive voltages are applied to both the bottom gate electrode and the top gate electrode;

When positive voltage is applied to both the bottom gate electrode and the top gate electrode, the source and drain electrodes both show N-type contact, that is, under the action of the positive electrostatic field, the electron accumulation causes the Fermi level of the tungsten diselenide channel material to approach the conduction band, reducing the electron potential barrier and increasing the hole potential barrier, which is beneficial to the transmission of electrons and hinders the transmission of holes.

(3) FIG. 3 is a schematic diagram of the energy bands of the device in contact between the source and drain metals and the tungsten diselenide channel material under positive and negative bias when negative voltages are applied to both the bottom gate electrode and the top gate electrode;

When negative voltage is applied to both the bottom gate electrode and the top gate electrode, the source and drain electrodes both show P-type contact, that is, under the action of the negative electrostatic field, the accumulation of holes causes the Fermi level of the tungsten diselenide channel material to approach the valence band, reducing the hole barrier and increasing the electron barrier, which is beneficial to the transmission of holes and hinders the transmission of electrons.

(4) FIG. 4 is a schematic diagram of the energy bands of the device in contact with the source and drain metals and the tungsten diselenide channel material under positive and negative bias when a positive voltage is applied to the bottom gate electrode and a negative voltage is applied to the top gate electrode;

When a positive voltage is applied to the bottom gate electrode, the drain electrode exhibits an N-type contact, that is, under the action of a positive electrostatic field, the accumulation of electrons causes the Fermi energy level of the tungsten diselenide channel material to approach the valence band, reducing the electron potential barrier, increasing the hole potential barrier, facilitating the transmission of holes and hindering the transmission of electrons; when a negative voltage is applied to the top gate electrode, the source electrode exhibits a P-type contact, that is, under the action of a negative electrostatic field, the accumulation of holes causes the Fermi energy level of the tungsten diselenide channel material to approach the valence band, reducing the hole potential barrier, increasing the electron potential barrier, facilitating the transmission of holes and hindering the transmission of electrons;

(5) FIG. 5 is a schematic diagram of the energy bands of the device in contact between the source and drain metals and the tungsten diselenide channel material under positive and negative bias when a negative voltage is applied to the bottom gate electrode and a positive voltage is applied to the top gate electrode;

When a negative voltage is applied to the bottom gate electrode, the drain exhibits a P-type contact, that is, under the action of a negative electrostatic field, hole accumulation causes the Fermi level of the tungsten diselenide channel material to approach the valence band, reducing the hole potential barrier, increasing the electron potential barrier, facilitating the transmission of holes and hindering the transmission of electrons; when a positive voltage is applied to the top gate electrode, the source exhibits an N-type contact, that is, under the action of a positive electrostatic field, electron accumulation causes the Fermi level of the tungsten diselenide channel material to approach the valence band, reducing the electron potential barrier, increasing the hole potential barrier, facilitating the transmission of holes and hindering the transmission of electrons.

(6) FIG. 6 shows output characteristic curves of the device under four combinations of voltages applied to the bottom gate electrode and the top gate electrode: both are positive, both are negative, one is positive and the other is negative, and one is negative and the other is positive, showing four different switching characteristics;

According to the analysis of Figures 2 to 5, when positive voltages are applied to both the bottom gate electrode and the top gate electrode, the device conducts with electrons as the majority carriers under both positive and negative biases, exhibiting the switching characteristics of an N-type transistor; when negative voltages are applied to both the bottom gate electrode and the top gate electrode, the device conducts with holes as the majority carriers under both positive and negative biases, exhibiting the switching characteristics of a P-type transistor; when a positive voltage is applied to the bottom gate electrode and a negative voltage is applied to the top gate electrode, the device does not conduct in the forward direction, and conducts in the negative direction with holes as the majority carriers, exhibiting the switching characteristics of a reverse-biased diode; when a negative voltage is applied to the bottom gate electrode and a positive voltage is applied to the top gate electrode, the device conducts in the forward direction with electrons as the majority carriers, and does not conduct in the negative direction, exhibiting the switching characteristics of a forward-biased diode.

The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (9)

1. A two-dimensional reconfigurable transistor, comprising:

An insulating substrate (1), a source electrode (2), a bottom gate electrode (8), a bottom gate dielectric layer (7), a two-dimensional semiconductor layer (3), a top gate dielectric layer (4), a drain electrode (6) and a top gate electrode (5); the source electrode (2) and the bottom gate electrode (8) are located above the insulating substrate (1), the bottom gate dielectric layer (7) only completely covers the bottom gate electrode (8), the bottom gate dielectric layer (7) is of an L-shaped structure, the long sides of the bottom gate dielectric layer (7) are respectively contacted with the two-dimensional semiconductor layer (3) and the bottom gate electrode (8), the long sides of the bottom gate dielectric layer (7) are shorter than the two-dimensional semiconductor layer (3), the short sides of the bottom gate dielectric layer (7) are respectively contacted with the source electrode (2) and the bottom gate electrode (8), the two-dimensional semiconductor layer (3) is located above the bottom gate dielectric layer (7) and is contacted with the source electrode (2), the top gate dielectric layer (4) covers the two-dimensional semiconductor layer (3), the drain electrode (6) is contacted with the two-dimensional semiconductor layer (3), and the top gate electrode (5) is located above the top gate dielectric layer (4) and is not contacted with the drain electrode (6); the top gate dielectric layer (4) is of an L-shaped structure, the long side of the top gate dielectric layer (4) is respectively contacted with the top gate electrode (5) and the two-dimensional semiconductor layer (3), the short side of the top gate dielectric layer (4) is respectively contacted with the top gate electrode (5) and the drain electrode (6), the top gate electrode (5) does not participate in regulating and controlling a drain electrode contact area, and the bottom gate electrode (8) does not participate in regulating and controlling a source electrode contact area.

2. The two-dimensional reconfigurable transistor according to claim 1, characterized in that the two-dimensional semiconductor layer (3) is a two-dimensional layered material having bipolar field effect characteristics, the two-dimensional semiconductor layer (3) having a thickness of 2-10nm.

3. The two-dimensional reconfigurable transistor according to claim 1, characterized in that the insulating substrate (1) is a silicon wafer with an oxide layer, a flexible insulating PET or a sapphire substrate.

4. The two-dimensional reconfigurable transistor according to claim 1, wherein the materials of the source electrode (2), the bottom gate electrode (8), the drain electrode (6) and the top gate electrode (5) comprise a metal electrode material, a two-dimensional semi-metal material, and have a thickness of 20-50nm, and the materials of the bottom gate dielectric layer (7) and the top gate dielectric layer (4) adopt two-dimensional layered boron nitride, silicon oxide, aluminum oxide or hafnium oxide, and have a thickness of 20-40nm.

5. A method of fabricating a two-dimensional reconfigurable transistor, comprising:

Depositing a source electrode (2) and a bottom gate electrode (8) on the basis of an insulating substrate (1);

Depositing a bottom gate dielectric layer (7) on the bottom gate electrode (8) to complete the whole coverage;

-placing a two-dimensional semiconductor layer (3) over the bottom gate dielectric layer (7) and in direct contact with the source electrode (2);

Depositing a top gate dielectric layer (4) over the two-dimensional semiconductor layer (3) for partial coverage;

a top gate electrode (5) is deposited above the top gate dielectric layer (4), and a drain electrode (6) is deposited above the two-dimensional semiconductor layer (3) which is not covered by the top gate dielectric layer (4), so that the preparation of the two-dimensional reconfigurable transistor regulated and controlled by the vertical double gate electrode is completed;

The source electrode (2) and the bottom gate electrode (8) are positioned above the insulating substrate (1), the bottom gate dielectric layer (7) only completely covers the bottom gate electrode (8), the bottom gate dielectric layer (7) is of an L-shaped structure, the long sides of the bottom gate dielectric layer (7) are respectively contacted with the two-dimensional semiconductor layer (3) and the bottom gate electrode (8), the long sides of the bottom gate dielectric layer are shorter than the two-dimensional semiconductor layer (3), and the short sides of the bottom gate dielectric layer (7) are respectively contacted with the source electrode (2) and the bottom gate electrode (8); the two-dimensional semiconductor layer (3) is located above the bottom gate dielectric layer (7) and is in contact with the source electrode (2), the top gate dielectric layer (4) partially covers the two-dimensional semiconductor layer (3) and leaves a drain electrode contact area, the drain electrode (6) is in contact with the two-dimensional semiconductor layer (3), the top gate electrode (5) is located above the top gate dielectric layer (4) and is not in contact with the drain electrode (6), the top gate dielectric layer (4) is of an L-shaped structure, long sides of the top gate dielectric layer (4) are respectively in contact with the top gate electrode (5) and the two-dimensional semiconductor layer (3), short sides of the top gate dielectric layer are respectively in contact with the top gate electrode (5) and the drain electrode (6), the top gate electrode (5) does not participate in regulating the drain electrode contact area, and the bottom gate electrode (8) does not participate in regulating the source electrode contact area.

6. The method of claim 5, wherein performing the deposition comprises:

Patterning treatment is carried out by using an electron beam exposure process or an ultraviolet exposure process, and then deposition is completed by using a thermal evaporation process.

7. The method of manufacturing a two-dimensional reconfigurable transistor according to claim 5, wherein the total or partial coverage of the dielectric layer is performed based on an atomic deposition process.

8. The method of manufacturing a two-dimensional reconfigurable transistor according to claim 5, characterized in that a dry transfer process is used when the two-dimensional semiconductor layer (3) is placed over the bottom gate dielectric layer (7).

9. A method for controlling a two-dimensional reconfigurable transistor, applicable to the two-dimensional reconfigurable transistor according to any one of claims 1 to 4, comprising:

when the two-dimensional reconfigurable transistor operates, the drain electrode (6) provides bias voltage for the voltage application end, the source electrode (2) is grounded, and the combination mode of the gate electrode comprises the following steps: the bottom gate electrode (8) and the top gate electrode (5) apply positive voltages, the bottom gate electrode (8) and the top gate electrode (5) apply negative voltages, the bottom gate electrode (8) applies positive voltages and the top gate electrode (5) applies negative voltages, the bottom gate electrode (8) applies negative voltages and the top gate electrode (5) applies positive voltages;

when a positive voltage is applied to the drain electrode (6), electrons flow from the source electrode (2) to the drain electrode (6), and holes flow from the drain electrode (6) to the source electrode (2); when the drain electrode (6) applies a negative voltage, electrons flow from the drain electrode (6) to the source electrode (2), and holes flow from the source electrode (2) to the drain electrode (6);

if positive voltage is applied to the bottom gate electrode (8), the drain electrode (6) is in N-type contact, so that hole transmission is blocked; if the bottom gate electrode (8) is applied with a negative voltage, the drain electrode (6) is in P-type contact, and electron transmission is blocked;

if the top gate electrode (5) is applied with a positive voltage, the source electrode (2) is in N-type contact; if the top gate electrode (5) applies a negative voltage, the source (2) will appear as a P-type contact;

The source electrode (2) and the bottom gate electrode (8) are positioned above the insulating substrate (1), the bottom gate dielectric layer (7) only completely covers the bottom gate electrode (8), the bottom gate dielectric layer (7) is of an L-shaped structure, the long sides of the bottom gate dielectric layer (7) are respectively contacted with the two-dimensional semiconductor layer (3) and the bottom gate electrode (8), the long sides of the bottom gate dielectric layer are shorter than the two-dimensional semiconductor layer (3), and the short sides of the bottom gate dielectric layer (7) are respectively contacted with the source electrode (2) and the bottom gate electrode (8); the two-dimensional semiconductor layer (3) is located above the bottom gate dielectric layer (7) and is in contact with the source electrode (2), the top gate dielectric layer (4) partially covers the two-dimensional semiconductor layer (3) and leaves a drain electrode contact area, the drain electrode (6) is in contact with the two-dimensional semiconductor layer (3), the top gate electrode (5) is located above the top gate dielectric layer (4) and is not in contact with the drain electrode (6), the top gate dielectric layer (4) is of an L-shaped structure, long sides of the top gate dielectric layer (4) are respectively in contact with the top gate electrode (5) and the two-dimensional semiconductor layer (3), short sides of the top gate dielectric layer are respectively in contact with the top gate electrode (5) and the drain electrode (6), the top gate electrode (5) does not participate in regulating the drain electrode contact area, and the bottom gate electrode (8) does not participate in regulating the source electrode contact area.