CN116248119B - Digital-to-analog conversion circuit, chip and electronic equipment for PWM conversion analog output - Google Patents
Digital-to-analog conversion circuit, chip and electronic equipment for PWM conversion analog outputInfo
- Publication number
- CN116248119B CN116248119B CN202211700884.2A CN202211700884A CN116248119B CN 116248119 B CN116248119 B CN 116248119B CN 202211700884 A CN202211700884 A CN 202211700884A CN 116248119 B CN116248119 B CN 116248119B
- Authority
- CN
- China
- Prior art keywords
- coupled
- circuit
- counter
- output
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/86—Digital/analogue converters with intermediate conversion to frequency of pulses
- H03M1/88—Non-linear conversion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
本公开的实施例提供一种PWM转换模拟输出的数模转换电路、芯片及电子设备，PWM转换模拟输出的数模转换电路包括：PWM波产生电路、滤波电路，其中，PWM波产生电路，被配置为通过第一计数器对时钟信号进行计数，然后根据第一计数器的输出值与输入数字码值的比较结果产生PWM波，第一计数器的位数与输入数字码值的位数相同，时钟信号的频率随数模转换电路的预设转换频率、以及输入数字码值的位数的变化而变化；滤波电路，被配置为对PWM波进行滤波处理，得到模拟输出信号。解决了本类型现有的DAC电路精度低、不便于集成的问题。
Embodiments of the present disclosure provide a digital-to-analog conversion circuit, chip, and electronic device for converting PWM to analog output. The digital-to-analog conversion circuit includes a PWM wave generation circuit and a filtering circuit. The PWM wave generation circuit is configured to count a clock signal using a first counter and then generate a PWM wave based on a comparison result between the output value of the first counter and an input digital code value. The number of bits of the first counter is the same as the number of bits of the input digital code value, and the frequency of the clock signal varies with the preset conversion frequency of the digital-to-analog conversion circuit and the number of bits of the input digital code value. The filtering circuit is configured to filter the PWM wave to obtain an analog output signal. This solves the problem of low precision and inconvenient integration of existing DAC circuits of this type.
Description
Technical Field
Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a digital-to-analog conversion circuit, a chip, and an electronic device for PWM conversion of analog output.
Background
The digital-to-analog converter (Digital to analog converter, DAC) is also called a digital-to-analog converter. Implementations of the DAC include a variety of implementations, with pulse width modulation (Pulse Width Modulation, PWM) DAC being one common implementation. The PWM DAC can realize the output of different analog levels by inputting the duty ratio of the digital code value control clock. The implementation of a PWM DAC typically includes two processes, PWM wave generation and filtering. At present, the generation of PWM waves is mainly divided into two types, namely, the generation of PWM waves is realized by an analog comparator, specifically, a sawtooth wave (such as a constant current is charged by a capacitor or an RC integrator) and a DC controllable level are generated, and the PWM waves with adjustable duty ratio are output by the comparator, so that the magnitude of the DC level can be changed to change the duty ratio. However, the analog modulation scheme has larger area and power consumption, and on the other hand, non-ideal factors such as offset of the comparator can influence the modulation precision. The other is realized by an additional MCU chip, in particular, the corresponding PWM wave is obtained by the control of an external MCU chip, but the scheme is not beneficial to integration.
In summary, how to provide a PWM DAC circuit with high precision and convenient integration is needed to be solved.
Disclosure of Invention
The embodiments described herein provide a digital-to-analog conversion circuit, a chip and an electronic device for PWM conversion of analog output, in order to provide a digital-to-analog conversion circuit for PWM conversion of analog output with high precision and easy integration.
According to a first aspect of the present disclosure, there is provided a digital-to-analog conversion circuit for converting an analog output by PWM, comprising a PWM wave generation circuit configured to count a clock signal by a first counter, and then generate a PWM wave according to a comparison result of an output value of the first counter and an input digital code value, wherein the number of bits of the first counter is the same as that of the input digital code value, the frequency of the clock signal varies with a preset conversion frequency of the digital-to-analog conversion circuit and a variation of the number of bits of the input digital code value, and a filter circuit configured to filter the PWM wave to obtain an analog output signal.
The PWM wave generation circuit comprises a first counter, a plurality of first exclusive-OR gates, first triggers and second triggers, wherein the input end of the first counter is coupled with the clock signal, each output end of the first counter is coupled with one input end of one first exclusive-OR gate, the other input end of each first exclusive-OR gate is coupled with one bit signal of the input digital code value, the output end of each first exclusive-OR gate is coupled with one input end of the OR gate, the number of the first exclusive-OR gates is equal to the number of bits of the first counter, the output end of the OR gate is coupled with the clock end of the first trigger, the input ends of the first triggers are respectively coupled with the second output end of the first trigger and the reset end of the second trigger, the reset end of the first trigger is coupled with the reset end of the first trigger, the input end of the second trigger is coupled with the power supply voltage, and the output end of the second trigger is coupled with the first clock signal.
Optionally, the filtering circuit performs filtering processing on the PWM wave through a combination of an RC low-pass filter and a notch filter, and the filtering circuit comprises the RC low-pass filter and the notch filter, wherein the input end of the RC low-pass filter is coupled with the PWM wave, the output end of the RC low-pass filter is coupled with the input end of the notch filter, and the output end of the notch filter outputs the analog output signal.
Optionally, the notch filter comprises two sample-and-hold circuits in ping-pong mode and a sample clock generation circuit, wherein a first end of the sample-and-hold circuit in the first ping-pong mode and a second end of the sample-and-hold circuit in the second ping-pong mode are coupled together and are both coupled with the output end of the RC low-pass filter, a second end of the sample-and-hold circuit in the first ping-pong mode and a first end of the sample-and-hold circuit in the second ping-pong mode are coupled together and output the analog output signal, and the sample clock generation circuit provides the sample clock signals for the sample-and-hold circuits in the two ping-pong modes.
Optionally, the sample hold circuit in ping-pong mode comprises a first switch, a second switch and a sampling capacitor, wherein one end of the first switch is coupled with one end of the second switch, the other end of the first switch is used as a first end of the sample hold circuit in ping-pong mode, the other end of the second switch is used as a second end of the sample hold circuit in ping-pong mode, one end of the sampling capacitor is respectively coupled with one end of the first switch and one end of the second switch, and the other end of the sampling capacitor is coupled with a grounding end.
The sampling clock generation circuit comprises a delay module, a second counter, a second exclusive-OR gate, a plurality of third exclusive-OR gates, a NOR gate, a third trigger and a non-overlapping clock generation circuit, wherein the input end of the delay module is coupled with the clock signal, the output end of the delay module is coupled with one input end of the second exclusive-OR gate, the other input end of the second exclusive-OR gate is coupled with the clock signal, the output end of the second exclusive-OR gate is coupled with the input end of the second counter, the reset signal is a signal which is delayed by one period of the clock signal after the output signal of the reset end of the first counter, each output end of the second counter is coupled with one input end of one third exclusive-OR gate, the bit number of the second counter is 1 larger than the input digital code value, the other input end of one third exclusive-OR gate is coupled with the clock signal, the reset signal is coupled with the other input end of the second exclusive-OR gate, the reset signal is coupled with the output end of the third exclusive-OR gate, the reset signal is generated by the output end of the third exclusive-OR gate is coupled with the output end of the clock signal after one period of the clock signal, and the output ends of the third exclusive-OR gate are respectively.
Optionally, the sampling clock signal comprises a first sampling clock signal and a second sampling clock signal, wherein the first sampling clock signal controls the first switch, and the second sampling clock signal controls the second switch.
Optionally, the frequency of the clock signal is 2 N times of a preset conversion frequency of the digital-to-analog conversion circuit, where N is a number of bits of the input digital code value.
Optionally, the delay of the delay module is less than half of the period of the clock signal.
According to a second aspect of the present disclosure there is provided a chip comprising a digital to analogue conversion circuit for PWM converting an analogue output according to any one of the first aspects.
According to a third aspect of the present disclosure, there is provided an electronic device comprising the chip of the second aspect.
The digital-to-analog conversion circuit of the PWM conversion analog output, the chip and the digital-to-analog conversion circuit of the PWM conversion analog output in the electronic equipment comprise a PWM wave generation circuit and a filter circuit, wherein the PWM wave generation circuit is configured to count a clock signal through a first counter, then generate a PWM wave according to a comparison result of an output value of the first counter and an input digital code value, the bit number of the first counter is the same as that of the input digital code value, the frequency of a clock signal changes along with the preset conversion frequency of the digital-to-analog conversion circuit and the change of the bit number of the input digital code value, and the filter circuit is configured to filter the PWM wave to obtain an analog output signal. It can be seen that the PWM wave generating circuit in the digital-to-analog conversion circuit of the PWM conversion analog output of the embodiment of the present disclosure is a pure digital circuit, which can improve the accuracy compared to the implementation of the analog comparator, and in addition, does not use an additional chip such as an MCU, thus facilitating integration.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:
FIG. 1 is a schematic block diagram of a digital-to-analog conversion circuit for PWM converting an analog output in accordance with an embodiment of the present disclosure;
fig. 2 is an exemplary circuit diagram of a PWM wave generating circuit of an embodiment of the present disclosure;
FIG. 3 is a graph of output waveforms of respective key signals corresponding to the operation of FIG. 2;
FIG. 4 is a schematic block diagram of a filter circuit of an embodiment of the present disclosure;
FIG. 5 is a schematic block diagram of another filtering circuit of an embodiment of the present disclosure;
FIG. 6 is an exemplary circuit diagram of a sample-and-hold circuit in ping-pong mode according to an embodiment of the present disclosure;
FIG. 7 is an exemplary circuit diagram of a sampling clock generation circuit of an embodiment of the present disclosure;
FIG. 8 is a graph of output waveforms of respective key signals associated with operation of the circuit of FIG. 7;
Elements in the figures are illustrated schematically and not drawn to scale.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).
In order to solve the problems that the existing digital-to-analog conversion circuit for converting the analog output by PWM is low in precision and inconvenient to integrate, a novel digital-to-analog conversion circuit for converting the analog output by PWM is provided. The digital-to-analog conversion circuit of the PWM conversion analog output of the present disclosure is described in detail below.
Fig. 1 shows a schematic block diagram of a digital-to-analog conversion circuit 100 for PWM converting an analog output according to an embodiment of the present disclosure, including a PWM wave generating circuit 110, a filtering circuit 120. The PWM wave generating circuit 110 is configured to count the clock signal CLK1 by the first counter I0, and then generate the PWM wave pwm_out according to the comparison result of the output value of the first counter and the input digital code value DIN < N-1:0>, wherein the number of bits of the first counter is the same as the number of bits of the input digital code value DIN < N-1:0 >. The step of generating the PWM wave PWM_OUT according to the comparison result of the output value of the first counter and the input digital code value DIN < N-1:0> is that the output value of the first counter and the input digital code value DIN < N-1:0> are compared bit by bit, when the output value of the first counter is the same as the input digital code value DIN < N-1:0>, the PWM wave PWM_OUT is high level, and thus the high level of the PWM wave PWM_OUT is transformed along with the transformation of the input digital code value DIN < N-1:0>, and the PWM wave with adjustable duty ratio can be obtained. In addition, in order to meet the requirement, the frequency of the clock signal CLK1 is set according to the preset conversion frequency f out of the digital-to-analog conversion circuit and the number of bits of the input digital code value DIN < N-1:0 >. The frequency of the clock signal CLK1 varies with the preset conversion frequency f out of the digital-to-analog conversion circuit and the number of bits of the input digital code value DIN < N-1:0 >. The frequency of the clock signal CLK1 is 2 N times the predetermined conversion frequency f out of the DAC circuit, where N is the number of bits of the input digital code value DIN < N-1:0 >. The filtering circuit 120 is coupled to the PWM wave generating circuit 110, and the filtering circuit 120 is configured to filter the PWM wave pwm_out to obtain the analog output signal Vout. The specific filter circuit 120 may be a first-order or higher-order RC low-pass filter circuit, and an exemplary diagram of a first-order RC low-pass filter circuit is provided at 121 in fig. 5. Of course, other RC low-pass filter circuits capable of implementing low-pass filtering may be used in practical applications.
Further, as shown in FIG. 2, the PWM wave generation circuit 110 comprises a first Counter (N-bit Counter) I 0, a plurality of first exclusive OR gates 111, OR gates 112, a first flip-flop I 1, and a second flip-flop I 2, wherein the input terminal of the first Counter I 0 is coupled to the clock signal CLK1, each output terminal ZOUT < N-1:0> of the first Counter I 0 is coupled to one input terminal of the first exclusive OR gate 111, the other input terminal of each first exclusive OR gate 111 is coupled to one bit signal of the input digital code value DIN < N-1:0>, the output terminal of each first exclusive OR gate 111 is coupled to one input terminal of the OR gate 112, the number of the first exclusive OR gates 111 is equal to the number of bits of the first Counter I 0, the output terminal (the output terminal of the output terminal is C_OK) of the OR gate 112 is coupled to the clock terminal of the first flip-flop I 1, and the input terminal D of the first flip-flop I 1 is coupled to the second output terminal of the first flip-flop I 1, respectivelyReset terminal of second trigger I 2 Reset terminal of first trigger I 1 The input terminal D of the second flip-flop I 2 is coupled to the power voltage VDD, the clock terminal CLK of the second flip-flop I 2 is coupled to the clock signal CLK1, and the first output terminal Q of the second flip-flop I2 outputs the PWM wave PWM_OUT.
The operation principle of the PWM wave generating circuit 110 will be described with reference to the circuit diagram in fig. 2, assuming that for a 3-bit digital-to-analog conversion circuit, the input digital code value DIN < N-1:0> is DIN <2:0>, the first counter I 0 is a 3-bit counter, the number of the first exclusive-or gates 111 is 3, and the frequency of the clock signal CLK1 is 8*f out. When the input digital code value DIN <2:0> is 3'b001, the first counter I 0 outputs 3' b001 on the 1 st clock rising edge, the output value of the first counter I 0 is compared with the input digital code value DIN <2:0> bit by bit through a plurality of first exclusive OR gates 111, and then added through the OR gates 112 to generate a signal C_OK, wherein the C_OK is kept at 0 in the 1 st clock cycle and is restored to 1 on the 2 nd clock rising edge, at the moment, the first trigger I 1 is activated, so that the T_RESET signal is pulled low, and the value of PWM_OUT is pulled low on the 2 nd clock rising edge. while the first counter I 0 will continue to operate until the count is full of 2 3 =8 clock cycles, and then output a RESET signal a_reset of the overall circuit, RESET I 0 and I 1, and pwm_out will also return to high level at the rising edge of the 9 th clock cycle, thereby cycling the process, fig. 3 shows that the output waveforms of the key signals in 8 clock cycles, in order from top to bottom, CLK1, Waveforms corresponding to C_OK, T_RESET, PWM_OUT and A_RESET. Similarly, when the input code value DIN <2:0> is shifted between 3'b000 and 3' b111, the high level time of the corresponding PWM_OUT is also shifted, resulting in a PWM wave with a duty cycle DIN <2:0>/2 3, thus resulting in an analog output signal Vout with a level DIN <2:0>/2 3. For the digital-to-analog conversion circuit of N-bit, only the bit number of the first counter I 0 and the number of the first exclusive-OR gates 111 need to be modified, and the digital logic is kept consistent. In addition, it should be further noted that, in the embodiment of the present disclosure, the first flip-flop I 1 and the second flip-flop I 2 are flip-flops that have a reset terminal and can be triggered on a clock rising edge, for example, may be a D flip-flop shown in fig. 2, may also be an RS flip-flop, a JK flip-flop, or the like, and may satisfy a flip-flop that has a reset terminal and can be triggered on a clock rising edge.
From the above description, it can be seen that the PWM wave generating circuit in the digital-to-analog conversion circuit of the PWM conversion analog output of the embodiment of the present disclosure is a pure digital circuit, which can improve accuracy compared to the manner in which the analog comparator is implemented, and in addition, does not use an additional chip such as an MCU, thus facilitating integration.
Further, for the filtering circuit 120 in the above embodiment, since the circuit obtains the analog level through the first-order or high-order RC low-pass filtering, this scheme may cause the output analog signal to have a large ripple (for example, in fig. 8, rc_out is a schematic waveform obtained by filtering the PWM wave pwm_out based on the RC low-pass filter 121 in fig. 5, a large ripple may be seen), and the setup time is long when the RC has a large value. The embodiment of the disclosure provides a new implementation manner of the filter circuit 120, specifically, the filter circuit 120 performs filtering processing on the PWM wave pwm_out through a combination of an RC low-pass filter and a notch filter to obtain an analog output signal Vout. The PWM wave pwm_out is initially low-pass filtered by the RC low-pass filter, and generally exhibits a ripple similar to a triangular wave after passing through the RC low-pass filter, and the frequency of the ripple is the preset conversion frequency f out of the digital-to-analog conversion circuit, so that a notch filter is considered to reduce the ripple of the analog output signal Vout. Fig. 4 shows an exemplary block diagram of a filter circuit 120 provided by an embodiment of the disclosure, and as shown in fig. 4, the filter circuit 120 includes an RC low-pass filter 121 and a notch filter 122, wherein an input terminal of the RC low-pass filter 121 is coupled to a PWM wave pwm_out, an output terminal of the RC low-pass filter (an output terminal outputs an rc_out signal) is coupled to an input terminal of the notch filter 122, and an output terminal of the notch filter 122 outputs an analog output signal Vout. Further, as shown in fig. 5, the RC low-pass filter 121 includes a filter resistor R and a filter capacitor C, where the filter resistor R and the filter capacitor C form a first-order RC low-pass filter 121, and perform preliminary filtering processing on the PWM wave pwm_out output from the PWM wave generating circuit 110. It should be noted that the RC low-pass filter 121 in fig. 4 may be another type of RC low-pass filter structure, and fig. 5 is only an example, and may be a higher-order RC low-pass filter structure. As shown in fig. 5, notch filter 122 includes two sample-and-hold circuits 1221 in ping-pong mode, a sample clock generating circuit 1222, wherein a first end of the sample-and-hold circuit 1221 in ping-pong mode and a second end of the sample-and-hold circuit 1221 in ping-pong mode are coupled together and are coupled to an output of RC low pass filter 121, a second end of the sample-and-hold circuit 1221 in ping-pong mode and a first end of the sample-and-hold circuit 1221 in ping-pong mode are coupled together and output analog output signal Vout, and the sample clock generating circuit 1222 provides sample clock signals (f s ). Further, fig. 6 shows an exemplary circuit diagram of two ping-pong mode sample-and-hold circuits 1221. As shown in fig. 6, the sample-and-hold circuit 1221 in ping-pong mode includes a first switch S1, a second switch S2, and a sampling capacitor C0, where one end of the first switch S1 is coupled to one end of the second switch S2, the other end of the first switch S1 is used as a first end of the sample-and-hold circuit 1221 in ping-pong mode, the other end of the second switch S2 is used as a second end of the sample-and-hold circuit 1221 in ping-pong mode, and one end of the sampling capacitor C0 is coupled to one end of the first switch S1 and one end of the second switch S2, respectively, and the other end of the sampling capacitor C0 is coupled to a ground terminal. Specifically, the sampling clock signal includes a first sampling clock signalSecond sampling clock signalFirst and second sampling clock signals f s andAre not overlapped with each other, wherein the first sampling clock signal f s controls the first switch S1, the second sampling clock signalThe second switch S2 is controlled. A sampling clock signal (f s),) The sampling frequency of (a) is half of the preset conversion frequency f out of the digital-to-analog conversion circuit, so that the center frequency of the notch filter 122 is f out, the sampling is always performed on the same side slope of RC_OUT, the DC level offset is reduced, and the ripple is reduced. And through a sampling clock signal (f s,) The generation logic of (a) ensures that the point of each sampling is controlled under different input digital code values DIN < N-1:0> to correspond to the middle point of the high level of PWM_OUT, and finally an analog output signal Vout is obtained, wherein Vout is an analog quantity with the level DIN < N-1:0>/2 N.
Further, FIG. 7 shows a method for generating a sampling clock signal (f s,) An exemplary circuit diagram of the sample clock generation circuit 1222. As shown in fig. 7, the sampling clock generation circuit 1222 includes: delay block I 3, second Counter (N+1) -bit Counter) I 4, second exclusive-OR gate 12221, multiple third exclusive-OR gates 12222, NOR gate 12223, third flip-flop I 5, A Non-overlapping clock generating circuit (Non-overlapping Clock generator) I 6, wherein an input terminal of the delay block I 3 is coupled to the clock signal CLK1, and an output terminal of the delay block I 3 is coupled to one input terminal of the second exclusive-or gate 12221; the other input terminal of the second exclusive-or gate 12221 is coupled to the clock signal CLK1, and the output terminal (output terminal outputting the clk_d signal) of the second exclusive-or gate 12221 is coupled to the input terminal of the second counter I4; the Reset terminal Reset of the second counter I4 is coupled to the Reset signal a_reset_d, the Reset signal a_reset_d is a signal of the Reset terminal Reset of the first counter I0 delayed by one period of the clock signal CLK1, each output terminal ZOUT < N:0> of the second counter I 4 is coupled to one input terminal of one third exclusive or gate 12222, the bit number of the second counter I 4 is 1 larger than the bit number of the input digital code value DIN < N-1:0>, the other input terminal of one third exclusive or gate 12222 of the plurality of third exclusive or gates 12222 is coupled to the ground terminal GND, the other input terminal of each other third exclusive or gate 12222 is coupled to one bit signal of the input digital code value DIN < N-1:0>, the output terminal of each third exclusive or gate 12222 is coupled to one input terminal of the nor gate 12223, the output terminal (output terminal d_ok signal) of the nor gate 12223 is coupled to the input terminal of the third flip-flop I24, the other input terminal of the third exclusive or gate 1224 is coupled to the ground terminal GND, the other input terminal of the third flip-flop I is coupled to the third flip-flop I62 is coupled to the output terminal of the third flip-flop I 5, respectivelyAn input terminal of the non-overlapping clock generating circuit I 6, a reset terminal of the third flip-flop I 5 Coupled to the power supply voltage VDD, the output of the non-overlap clock generation circuit I 6 outputs a sampling clock signal (f s,). In addition, it should be further noted that, in the embodiment of the disclosure, the third flip-flop I 5 is a flip-flop with a reset terminal and capable of being triggered on a clock rising edge, for example, may be a D flip-flop shown in fig. 7, and may also be an RS flip-flop, a JK flip-flop, or the like, which may satisfy the flip-flop with a reset terminal and be capable of being triggered on a clock rising edge.
The working principle of the sampling clock generating circuit 1222 is described with reference to fig. 7, in which the clock signal CLK1 is delayed for a period of time by the delay module I 3, then the output result of the delay module I3 is xored with the clock signal CLK1 to generate a double-frequency clock signal clk_d, and then a second counter I 4 of (n+1) -bit is used to count (where N is the number of bits of the input digital code value DIN < N-1:0>, for example, when n=3, the second counter I 4 is a 4-bit counter). This is done because the middle point of the high level of pwm_out is just at the rising edge of the (DIN < N:0> +1) th clock of the clk_d signal after the frequency multiplication of CLK1, the RESET signal a_reset_d of the second counter I 4 is obtained after 1 CLK1 period from the previous a_reset signal, and the use of the a_reset_d signal as the RESET signal of the second counter I 4 can skip the count of the 1st period of clk_d, thereby avoiding the implementation of +1 circuit (avoiding the circuit design of adding 1 to the original code value because adding 1 would increase the area consumption if adding requires an adder, the present disclosure adds 1 to the clock, and the same effect is achieved by clock delay, which can reduce the area consumption). It should be noted that the delay of the delay module I 3 depends on the clock rate of CLK1, and specifically, the delay time may be any value less than 1/2 times the clock period of the clock signal CLK 1. Taking n=3 as an example, the following circuit principle is described, when the output value ZOUT <3:0> of the second counter I 4 corresponds to the input digital code value DIN <2:0>, d_ok is high, and the second output terminal of I 5 is at the same timeIs turned over, and after waiting for the next reset of I 4, is turned over again after DIN <2:0> CLK_D cycles, so each time CLKOUT is turned over in the middle of the high level of PWM_OUT, a sample-and-hold clock signal can be adaptively generated by a non-overlapping clock generating circuit I 6, i.e. a sampling clock signal (f s,). In addition, it should be noted that, for the digital-to-analog conversion circuit of the N-bit, only the number of bits of the second counter I 4 and the number of the third exclusive-or gates 12222 need to be modified, and the digital logic remains consistent.
Further, fig. 8 shows a sampling clock signal (f s,) Output waveforms of the respective key signals in the process are generated. As shown in FIG. 8, CLK1, CLK_ D, PWM _OUT, A_RESET_ D, D _OK, f s, from top to bottom,The waveform diagrams corresponding to the Vout and the RC_OUT are shown, wherein Sampling is taken as a Sampling point, the Sampling is always performed on the slope of the same side of the RC_OUT, the DC level shift is reduced, and compared with the RC_OUT, the ripple wave of the analog output signal Vout is obviously restrained.
From the above description, it can be seen that the filtering stage in the digital-to-analog conversion circuit of PWM conversion analog output according to the embodiments of the present disclosure adds a notch filter to greatly reduce the ripple of the output analog signal. On the basis of the foregoing embodiments, the digital-to-analog conversion circuit for PWM conversion analog output in the embodiments of the present disclosure is a DAC circuit with high precision, easy integration, and small ripple.
The embodiment of the disclosure also provides a chip. The chip includes digital-to-analog conversion circuitry for PWM converting an analog output according to an embodiment of the present disclosure. The chip is, for example, a chip for performing digital-to-analog signal conversion with high accuracy.
The embodiment of the disclosure also provides electronic equipment. The electronic device includes a chip according to an embodiment of the present disclosure. Such as automatic test equipment, and industrial process control equipment.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the disclosure may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (9)
1. A digital-to-analog conversion circuit for PWM conversion analog output is characterized by comprising a PWM wave generating circuit and a filter circuit,
The PWM wave generation circuit is configured to count a clock signal through a first counter, and then generate PWM waves according to a comparison result of an output value of the first counter and an input digital code value, wherein the bit number of the first counter is the same as that of the input digital code value, and the conversion frequency of the digital-to-analog conversion circuit is changed along with the frequency of the clock signal and the change of the bit number of the input digital code value;
the filter circuit is configured to perform filter processing on the PWM waves to obtain analog output signals;
The PWM wave generation circuit comprises a first counter, a plurality of first exclusive-OR gates, first triggers and second triggers, wherein the input end of the first counter is coupled with the clock signal, each output end of the first counter is coupled with one input end of one first exclusive-OR gate, the other input end of each first exclusive-OR gate is coupled with one bit signal of the input digital code value, the output end of each first exclusive-OR gate is coupled with one input end of the OR gate, the number of the first exclusive-OR gates is equal to the number of bits of the first counter, the output end of the OR gate is coupled with the clock end of the first trigger, the input ends of the first triggers are respectively coupled with the second output end of the first trigger and the reset end of the second trigger, the reset end of the first trigger is coupled with the reset end of the first counter, the input end of the second trigger is coupled with the power supply voltage, and the output end of the second trigger is coupled with the first clock signal.
2. The digital-to-analog conversion circuit of claim 1, wherein said filter circuit filters said PWM wave by a combination of an RC low pass filter and a notch filter, said filter circuit comprising an RC low pass filter, a notch filter,
The input end of the RC low-pass filter is coupled with the PWM wave, the output end of the RC low-pass filter is coupled with the input end of the notch filter, and the output end of the notch filter outputs the analog output signal.
3. The digital-to-analog conversion circuit of claim 2, wherein said notch filter comprises two sample-and-hold circuits in ping-pong mode, a sample clock generation circuit,
The first end of the sample hold circuit in the first ping-pong mode and the second end of the sample hold circuit in the second ping-pong mode are coupled together and are coupled with the output end of the RC low-pass filter; the second end of the sample-and-hold circuit in the first ping-pong mode and the first end of the sample-and-hold circuit in the second ping-pong mode are coupled together to output the analog output signal;
the sampling clock generation circuit provides sampling clock signals for two sample hold circuits in ping-pong mode.
4. The digital to analog conversion circuit of claim 3, wherein said ping-pong mode sample and hold circuit comprises a first switch, a second switch, a sampling capacitor,
One end of the first switch is coupled with one end of the second switch, the other end of the first switch is used as a first end of the sample hold circuit in the ping-pong mode, and the other end of the second switch is used as a second end of the sample hold circuit in the ping-pong mode;
one end of the sampling capacitor is respectively coupled with one end of the first switch and one end of the second switch, and the other end of the sampling capacitor is coupled with the grounding end.
5. The digital to analog conversion circuit of claim 3, wherein said sampling clock generation circuit comprises a delay module, a second counter, a second exclusive-OR gate, a plurality of third exclusive-OR gates, a NOR gate, a third flip-flop, a non-overlapping clock generation circuit,
The input end of the delay module is coupled with the clock signal, and the output end of the delay module is coupled with one input end of the second exclusive-OR gate;
The other input end of the second exclusive-or gate is coupled with the clock signal, and the output end of the second exclusive-or gate is coupled with the input end of the second counter;
The reset end of the second counter is coupled with a reset signal, the reset signal is a signal obtained by delaying an output signal of the reset end of the first counter by one period of the clock signal, each output end of the second counter is coupled with one input end of a third exclusive-OR gate, and the number of bits of the second counter is 1 greater than that of the input digital code value;
the other input end of one of the plurality of third exclusive-OR gates is coupled with the grounding end, and the other input end of each of the other third exclusive-OR gates is coupled with one bit signal of the input digital code value;
The output end of the NOR gate is coupled with the clock end of the third trigger, the input end of the third trigger is respectively coupled with the second output end of the third trigger and the input end of the non-overlapping clock generating circuit, and the reset end of the third trigger is coupled with the power supply voltage;
The output end of the non-overlapping clock generation circuit outputs the sampling clock signal.
6. The digital-to-analog conversion circuit of claim 4, wherein said sampling clock signal comprises a first sampling clock signal, a second sampling clock signal;
Wherein the first sampling clock signal controls the first switch and the second sampling clock signal controls the second switch.
7. The digital-to-analog conversion circuit of any one of claims 1-6, wherein the clock signal has a frequency that is 2 N times the conversion frequency of the digital-to-analog conversion circuit, where N is the number of bits of the input digital code value.
8. A chip comprising a digital-to-analog conversion circuit of a PWM converted analog output according to any one of claims 1-7.
9. An electronic device comprising a chip according to claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211700884.2A CN116248119B (en) | 2022-12-28 | 2022-12-28 | Digital-to-analog conversion circuit, chip and electronic equipment for PWM conversion analog output |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211700884.2A CN116248119B (en) | 2022-12-28 | 2022-12-28 | Digital-to-analog conversion circuit, chip and electronic equipment for PWM conversion analog output |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116248119A CN116248119A (en) | 2023-06-09 |
| CN116248119B true CN116248119B (en) | 2025-09-09 |
Family
ID=86626857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211700884.2A Active CN116248119B (en) | 2022-12-28 | 2022-12-28 | Digital-to-analog conversion circuit, chip and electronic equipment for PWM conversion analog output |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116248119B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118860052A (en) * | 2024-09-29 | 2024-10-29 | 中茵微电子(南京)有限公司 | A balanced control circuit in a multi-input LDO power supply system and an operating method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109547028A (en) * | 2017-09-22 | 2019-03-29 | 卡西欧计算机株式会社 | Digiverter, electronic musical instrument, information processing unit and digital-analog convertion method |
| CN110463043A (en) * | 2017-03-22 | 2019-11-15 | 雷神公司 | Low-power analog-digital converter |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6476747B1 (en) * | 2001-04-10 | 2002-11-05 | Adc Telecommunications Israel Ltd. | Digital to analog converter |
| CN202111690U (en) * | 2011-06-03 | 2012-01-11 | 高博 | Digital analog converter |
| CN110830008B (en) * | 2019-11-11 | 2023-04-25 | 上海必阳科技有限公司 | Voltage waveform generating device |
| CN114698178B (en) * | 2020-12-30 | 2022-11-22 | 华润微集成电路(无锡)有限公司 | LED dimming circuit |
-
2022
- 2022-12-28 CN CN202211700884.2A patent/CN116248119B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110463043A (en) * | 2017-03-22 | 2019-11-15 | 雷神公司 | Low-power analog-digital converter |
| CN109547028A (en) * | 2017-09-22 | 2019-03-29 | 卡西欧计算机株式会社 | Digiverter, electronic musical instrument, information processing unit and digital-analog convertion method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116248119A (en) | 2023-06-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7696910B2 (en) | Dither circuit and analog digital converter having dither circuit | |
| WO2007101014A2 (en) | Self-calibrating digital pulse-width modulator (dpwm) | |
| US6965339B2 (en) | Method and system for analog to digital conversion using digital pulse width modulation (PWM) | |
| US5818377A (en) | Bipolar element averaging, digital-to-analog converter | |
| CN116248119B (en) | Digital-to-analog conversion circuit, chip and electronic equipment for PWM conversion analog output | |
| WO2003096542A1 (en) | Digital-analog converter | |
| JP5303761B2 (en) | Timing generation circuit and phase shift circuit | |
| WO2022159786A1 (en) | A digital filter for a delta-sigma analog-to-digital converter | |
| TWI650955B (en) | Sigma delta modulator and signal conversion method thereof | |
| CN106788439B (en) | System and method for adjusting transfer characteristics of integral analog-to-digital converter | |
| TW201332294A (en) | Counter based digital pulse width modulation device could scalable the resolution | |
| EP2083518A1 (en) | Analog/digital conversion circuit, timing signal generation circuit, and control device | |
| JP3927478B2 (en) | D / A converter | |
| CN216451352U (en) | An analog circuit for realizing clock frequency comparison | |
| US8732511B2 (en) | Resistor ladder based phase interpolation | |
| CN109889200B (en) | Circuit for converting voltage signal into frequency signal based on frequency quantizer | |
| JPH0763125B2 (en) | Frequency synthesizer | |
| RU119960U1 (en) | ANALOG-DIGITAL CONVERTER | |
| TWI635708B (en) | Pulse width modulation converter and converting method thereof | |
| Parekh et al. | Power efficient all-digital delta-sigma TDC with differential gated delay line time integrator | |
| US7619549B2 (en) | Methods and systems for reducing a sign-bit pulse at a voltage output of a sigma-delta digital-to-analog converter | |
| CN108055040B (en) | A kind of ADC structure based on multi-phase clock and its analog-to-digital conversion method | |
| KR102109598B1 (en) | Digital-to-analog converter capable of expanding the number of bits | |
| CN109802677B (en) | Analog-to-digital conversion device | |
| CN108988833B (en) | Pulse width modulation converter and its conversion method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |