CN116248573B - Link splicing method, device and storage medium - Google Patents

Abstract

The application provides a link splicing method, a device and a storage medium, relates to the technical field of communication, and is used for solving the problem that a common technology cannot accurately splice a plurality of sub-links in a transmission link. The method comprises the following steps: acquiring a plurality of link information corresponding to a plurality of sub-links one by one; when the link termination information of the other sub-links does not exist the link termination information which is the same as the link start information of the target sub-link, determining the target sub-link as the first sub-link of the target link; and determining address information of other sub-links according to the first sub-link and the logic topology tree, and splicing the plurality of sub-links based on the address information of the other sub-links and the first sub-link to obtain the target link. The application can improve the accuracy of splicing the plurality of sub-links in the transmission link.

Description

Link splicing method, device and storage medium

Technical Field

The present application relates to the field of communication technology, and in particular to a link splicing method, device and storage medium.

Background technique

With the continuous development of the network, the types and number of network devices in the transmission network are increasing. Correspondingly, the link data between network devices is also increasing. In order to monitor and maintain the link data in a complete transmission link, it is necessary to splice multiple sub-links in this complete transmission link.

Therefore, how to accurately splice multiple sub-links in a transmission link is a problem that needs to be solved urgently.

Summary of the invention

The present application provides a link splicing method, device and storage medium, which are used to solve the problem that multiple sub-links in a transmission link cannot be accurately spliced in the general technology.

In order to achieve the above objectives, this application adopts the following technical solutions:

In a first aspect, a link splicing method is provided, comprising: obtaining a plurality of link information corresponding to a plurality of sub-links one by one; the link information comprising link start information and link termination information; when link termination information of other sub-links does not contain link termination information identical to the link start information of a target sub-link, determining the target sub-link as the first sub-link of the target link; the other sub-links are sub-links other than the target sub-link among the plurality of sub-links; determining address information of the other sub-links according to the first sub-link and a logical topology tree, and splicing the plurality of sub-links based on the address information of the other sub-links and the first sub-link to obtain the target link; the logical topology tree comprising a plurality of logical nodes; the logical node is used to determine the address information of the next sub-link of the sub-link that successfully matches the logical node.

Optionally, the method for determining the address information of other sub-links based on the first sub-link and the logical topology tree specifically includes: inputting the link termination information of the nth sub-link into the logical topology tree; n is a positive integer; when the logical topology tree includes a logical node that successfully matches the nth sub-link, determining whether the target logical node outputs the address information of the n+1th sub-link; the target logical node is a logical node that successfully matches the nth sub-link; when the target logical node outputs the address information of the n+1th sub-link, repeatedly inputting the link termination information of the n+1th sub-link into the logical topology tree until the logical topology tree cannot match the sub-link; when the logical topology tree does not include a logical node that successfully matches the nth sub-link, or the target logical node cannot output the n+1th sub-link, determining the nth sub-link as the last sub-link of the target link; and determining the address information of other sub-links based on the address information of the sub-link output by the logical topology tree.

Optionally, the logical topology tree includes multiple logical layers; each logical node includes a first condition; the first condition includes: the link connection type of the nth sub-link is the same as the link connection type configured for the logical node, and/or, the time slot information of the nth sub-link is the same as the time slot information configured for the logical node; the link splicing method also includes: when the link termination information of the nth sub-link meets the first condition corresponding to the first logical node in the mth logical layer, determining the first logical node as the target logical node; m is a positive integer; when the link termination information of the nth sub-link does not meet the first condition corresponding to the first logical node in the mth logical layer, determining whether the m+1th logical layer includes a logical node that meets the first condition, until each logical layer does not include a logical node that meets the first condition, and determining that the logical topology tree does not include a logical node that successfully matches the nth sub-link; the m+1th logical layer is a sub-logical layer of the first logical node.

Optionally, the first logical node includes: a matching operator, a selection operator and a second condition; the matching operator is used to: determine the sublink corresponding to the link start information that is the same as the link termination information of the nth sublink in the link start information of the remaining sublinks; the remaining sublinks are sublinks other than the nth sublink among multiple sublinks; the selection operator is used to: determine the sublink with the largest sublink port number value; the second condition includes: determining whether the number of spliced target links is greater than a threshold or determining whether the second sublink is a sublink in the spliced target link; the link splicing method also includes: executing the matching operator of the first logical node; when the matching operator matches at least one first sublink, executing the selection operator of the first logical node; when the selection operator selects the second sublink from at least one first sublink, determining whether the second sublink meets the second condition; when the second sublink meets the second condition, obtaining the address information of the second sublink, and determining the address information of the second sublink as the address information of the n+1th sublink.

Optionally, after executing the matching operator of the first logical node, the link splicing method also includes: when the matching operator cannot match the first sub-link, determining whether the target logical node has a sub-logical layer; when the matching operator matches at least one first sub-link, and the selection operator selects a second sub-link from at least one first sub-link, and the second sub-link does not meet the second condition, determining whether the target logical node has a sub-logical layer.

Optionally, the link splicing method further includes: when the target logical node has a sub-logical layer, determining whether the sub-logical layer of the target logical node includes a logical node that meets the first condition; when the target logical node does not have a sub-logical layer, determining that the target logical node cannot output the n+1th sub-link.

In a second aspect, a link splicing device is provided, including: an acquisition unit and a processing unit; the acquisition unit is used to acquire multiple link information corresponding to multiple sub-links one by one; the link information includes link start information and link termination information; the processing unit is used to determine the target sub-link as the first sub-link of the target link when there is no link termination information identical to the link start information of the target sub-link in the link termination information of other sub-links; the other sub-links are sub-links other than the target sub-link among the multiple sub-links; the processing unit is also used to determine the address information of the other sub-links according to the first sub-link and the logical topology tree, and splice the multiple sub-links based on the address information of the other sub-links and the first sub-link to obtain the target link; the logical topology tree includes multiple logical nodes; the logical node is used to determine the address information of the next sub-link of the sub-link that successfully matches the logical node.

Optionally, the processing unit is used to: input the link termination information of the nth sub-link into the logical topology tree; n is a positive integer; when the logical topology tree includes a logical node that successfully matches the nth sub-link, determine whether the target logical node outputs the address information of the n+1th sub-link; the target logical node is the logical node that successfully matches the nth sub-link; when the target logical node outputs the address information of the n+1th sub-link, repeatedly input the link termination information of the n+1th sub-link into the logical topology tree until the logical topology tree cannot match the sub-link; when the logical topology tree does not include a logical node that successfully matches the nth sub-link, or the target logical node cannot output the n+1th sub-link, determine the nth sub-link as the last sub-link of the target link; and determine the address information of other sub-links based on the address information of the sub-links output by the logical topology tree.

Optionally, the logical topology tree includes multiple logical layers; each logical node includes a first condition; the first condition includes: the link connection type of the nth sub-link is the same as the link connection type configured for the logical node, and/or, the time slot information of the nth sub-link is the same as the time slot information configured for the logical node; the processing unit is further used to determine the first logical node as the target logical node when the link termination information of the nth sub-link meets the first condition corresponding to the first logical node in the mth logical layer; m is a positive integer; the processing unit is further used to determine whether the m+1th logical layer includes a logical node that meets the first condition when the link termination information of the nth sub-link does not meet the first condition corresponding to the first logical node in the mth logical layer, until each logical layer does not include a logical node that meets the first condition, and it is determined that the logical topology tree does not include a logical node that successfully matches the nth sub-link; the m+1th logical layer is a sub-logical layer of the first logical node.

Optionally, the first logical node includes: a matching operator, a selection operator and a second condition; the matching operator is used to: determine the sublink corresponding to the link start information that is the same as the link termination information of the nth sublink in the link start information of the remaining sublinks; the remaining sublinks are sublinks other than the nth sublink among multiple sublinks; the selection operator is used to: determine the sublink with the largest sublink port number value; the second condition includes: determining whether the number of spliced target links is greater than a threshold or determining whether the second sublink is a sublink in the spliced target link; the processing unit is also used to execute the matching operator of the first logical node; the processing unit is also used to execute the selection operator of the first logical node when the matching operator matches at least one first sublink; the processing unit is also used to determine whether the second sublink meets the second condition when the selection operator selects the second sublink from at least one first sublink; the processing unit is also used to obtain the address information of the second sublink when the second sublink meets the second condition, and determine the address information of the second sublink as the address information of the n+1th sublink.

Optionally, the processing unit is further used to determine whether the target logical node has a sub-logical layer when the matching operator fails to match the first sub-link; the processing unit is further used to determine whether the target logical node has a sub-logical layer when the matching operator matches at least one first sub-link, and the selection operator selects a second sub-link from at least one first sub-link, and the second sub-link does not meet the second condition.

Optionally, the processing unit is further used to determine whether the sub-logical layer of the target logical node includes a logical node that meets the first condition when the target logical node has a sub-logical layer; the processing unit is further used to determine that the target logical node cannot output the (n+1)th sub-link when the target logical node does not have a sub-logical layer.

In a third aspect, a link splicing device is provided, comprising a memory and a processor; the memory is used to store computer execution instructions, and the processor is connected to the memory through a bus; when the link splicing device is running, the processor executes the computer execution instructions stored in the memory, so that the link splicing device executes the link splicing method described in the first aspect.

The link splicing device may be a network device, or a part of a network device, such as a chip system in the network device. The chip system is used to support the network device to implement the functions involved in the first aspect and any possible implementation thereof, for example, to obtain, determine, and send the data and/or information involved in the above-mentioned link splicing method. The chip system includes a chip, and may also include other discrete devices or circuit structures.

In a fourth aspect, a computer-readable storage medium is provided, the computer-readable storage medium comprising computer execution instructions, and when the computer execution instructions are executed on a computer, the computer executes the link splicing method described in the first aspect.

In a fifth aspect, a computer program product is also provided. The computer program product includes computer instructions. When the computer instructions are executed on a link splicing device, the link splicing device executes the link splicing method as described in the first aspect above.

It should be noted that the above computer instructions may be stored in whole or in part on a first computer-readable storage medium, wherein the first computer-readable storage medium may be packaged together with the processor of the link splicing device, or may be packaged separately from the processor of the link splicing device, which is not limited in the present embodiment.

The description of the second, third, fourth and fifth aspects of the present application can refer to the detailed description of the first aspect; and the beneficial effects of the second, third, fourth and fifth aspects can refer to the beneficial effect analysis of the first aspect, which will not be repeated here.

In the embodiments of the present application, the name of the link splicing device does not limit the device or functional module itself. In actual implementation, these devices or functional modules may appear with other names. As long as the functions of each device or functional module are similar to those of the present application, they fall within the scope of the claims of the present application and their equivalent technologies.

These and other aspects of the present application will become more apparent from the following description.

The technical solution provided by this application brings at least the following beneficial effects:

Based on any of the above aspects, the embodiment of the present application provides a link splicing method, which can obtain multiple link information corresponding to multiple sub-links one by one, and when there is no link termination information identical to the link start information of the target sub-link in the link termination information of other sub-links, the target sub-link is determined as the first sub-link of the target link. Then, according to the first sub-link and the logical topology tree, the address information of the other sub-links is determined, and based on the address information of the other sub-links and the first sub-link, the multiple sub-links are spliced to obtain the target link.

As can be seen from the above, since a complete transmission link is composed of multiple sub-links, it is possible to first obtain multiple link information corresponding to the multiple sub-links one by one, and determine the first sub-link of the target link based on the above link information. Then, based on the first sub-link and the logical topology tree, determine the address information of the other sub-links, and then splice the first sub-link and the other sub-links through the address information to obtain the target link. In this way, the link splicing method provided in the embodiment of the present application can accurately and effectively splice multiple sub-links in the target link.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a structure of a link splicing system provided in an embodiment of the present application;

FIG2 is another structural schematic diagram of a link splicing system provided in an embodiment of the present application;

FIG3 is a schematic diagram of a hardware structure of a link splicing device provided in an embodiment of the present application;

FIG4 is a schematic diagram of another hardware structure of the link splicing device provided in an embodiment of the present application;

FIG5 is a schematic diagram of a flow chart of a link splicing method provided in an embodiment of the present application;

FIG6 is a schematic diagram of a flow chart of another link splicing method provided in an embodiment of the present application;

FIG7 is a schematic diagram of a flow chart of another link splicing method provided in an embodiment of the present application;

FIG8 is a schematic diagram of a flow chart of another link splicing method provided in an embodiment of the present application;

FIG9 is a schematic diagram of a flow chart of another link splicing method provided in an embodiment of the present application;

FIG10 is a schematic diagram of a flow chart of another link splicing method provided in an embodiment of the present application;

FIG. 11 is a schematic diagram of the structure of a link splicing device provided in an embodiment of the present application.

Detailed ways

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

In order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", etc. are used to distinguish between the same items or similar items with basically the same functions and effects. Those skilled in the art can understand that the words "first", "second", etc. are not limiting the quantity and execution order.

Before introducing the link splicing method provided by the present application in detail, a brief introduction is first given to the application scenarios and implementation environment involved in the present application.

As described in the background art, in order to monitor and maintain link data in a complete transmission link, it is necessary to splice multiple sub-links in the complete transmission link.

In view of the above problems, an embodiment of the present application provides a link splicing method, after the first electronic device obtains multiple link information corresponding to multiple sub-links one by one, when there is no link termination information identical to the link start information of the target sub-link in the link termination information of other sub-links, the target sub-link is determined as the first sub-link of the target link. Then, the first electronic device determines the address information of other sub-links based on the first sub-link and the logical topology tree, and splices the multiple sub-links based on the address information of the other sub-links and the first sub-link to obtain the target link.

As can be seen from the above, since a complete transmission link is composed of multiple sub-links, the first electronic device can first obtain multiple link information corresponding to the multiple sub-links one by one, and determine the first sub-link of the target link based on the above link information. Then, the first electronic device determines the address information of other sub-links based on the first sub-link and the logical topology tree, and then splices the first sub-link and the other sub-links through the address information to obtain the target link. In this way, the link splicing method provided in the embodiment of the present application can accurately and effectively splice multiple sub-links in the target link.

The link splicing method is applicable to a link splicing system. FIG1 shows a structure of the link splicing system. As shown in FIG1 , the link splicing system includes: a first electronic device 101 and a second electronic device 102.

The first electronic device 101 and the second electronic device 102 are connected in communication.

In practical applications, the first electronic device 101 may be connected to multiple second electronic devices 102, and the second electronic device 102 may also be connected to multiple first electronic devices 101. For ease of understanding, this application takes one first electronic device 101 connected to one second electronic device 102 as an example for explanation.

In the embodiment of the present application, the second electronic device 102 is used to provide data for link splicing to the first electronic device 101, so that the first electronic device 101 performs link splicing according to the data sent by the second electronic device 102.

Optionally, the data used for link splicing may include: link start information and link termination information of multiple sub-links.

Optionally, the entity devices of the first electronic device 101 and the second electronic device 102 may be servers or terminals, or one may be a server and the other may be a terminal, which is not limited in the embodiment of the present application.

Optionally, the terminal may be a device that provides voice and/or data connectivity to a user, a handheld device with wireless connection function, or other processing device connected to a wireless modem. The wireless terminal may communicate with one or more core networks via a radio access network (RAN). The wireless terminal may be a mobile terminal, such as a mobile phone (or "cellular" phone) and a computer with a mobile terminal, or a portable, pocket-sized, handheld, computer-built-in or vehicle-mounted mobile device that exchanges language and/or data with a radio access network, such as a mobile phone, a tablet computer, a laptop computer, a netbook, a personal digital assistant (PDA).

Optionally, the above-mentioned server can be a server in a server cluster (consisting of multiple servers), or a chip in the server, or a system on a chip in the server, or can be implemented by a virtual machine (VM) deployed on a physical machine, which is not limited in the embodiments of the present application.

Optionally, when the first electronic device 101 and the second electronic device 102 are physical devices of the same type (for example, the first electronic device 101 and the second electronic device 102 are both servers, or both are terminals), the first electronic device 101 and the second electronic device 102 may be two devices independently configured, or may be integrated in the same device.

It is easy to understand that when the first electronic device 101 and the second electronic device 102 are integrated into the same device, the communication mode between the first electronic device 101 and the second electronic device 102 is the communication between the internal modules of the device. In this case, the communication process between the two is the same as "the communication process between the first electronic device 101 and the second electronic device 102 when they are independent of each other".

For ease of understanding, the present application is described by taking the first electronic device 101 and the second electronic device 102 as being independent of each other as an example.

In one possible implementation, in combination with FIG. 1 , as shown in FIG. 2 , the first electronic device 101 may include a starting point scanning module 201 , a serial connection engine module 202 , a logic topology tree 203 and a data support module 204 .

The starting point scanning module 201 may include a starting point scanner and a database. The starting point scanner may access the database through three types of starting point scanners: a cross connection (CC) starting point scanner, a topological connection (TL) starting point scanner, and a CC&TL starting point scanner, so as to scan the starting point from the database.

Among them, the CC starting point scanner can be used to query sub-links with a connection type of cross connection, the TL starting point scanner can be used to query sub-links with a connection type of topology connection, and the CC&TL starting point scanner can be used to query sub-links with a connection type of cross connection and sub-links with a connection type of topology connection.

Optionally, the starting point scanning module 201 can select a starting point scanner of a corresponding type to query the first sub-link of the target link (such as the scanning starting point shown in Figure 2) according to the connection type of the first sub-link in the target link, and send the first sub-link to the serial connection engine module 202.

Optionally, the first sublink of the target link may also be referred to as the path start point. The sublink connection type may be a cross connection or a topological connection. The sublink may also be referred to as a path node. When the sublink connection type is a cross connection, the sublink may also be referred to as a cross connection node. When the sublink connection type is a topological connection, the sublink may also be referred to as a topological connection node.

The concatenation engine module 202 may include starting point data, a concatenation engine, and a complete path after the concatenation is completed.

Specifically, after receiving the first sublink of the target link (e.g., the starting point data shown in FIG. 2 ), the concatenation engine module 202 can batch input the first sublink (e.g., batch mount shown in FIG. 2 ) into the concatenation engine, and then the concatenation engine inputs the first sublink into the logical topology tree 203 (e.g., the last node of a certain path currently concatenated as shown in FIG. 2 ) to query other sublinks of the target link except the first sublink. Then, the concatenation engine concatenates the other sublinks queried from the logical topology tree 203 with the first sublink of the target link to obtain the target link (e.g., the complete path after the concatenation is completed as shown in FIG. 2 ).

Alternatively, concatenation may also be referred to as splicing.

The serial logic topology tree 203 may include multiple serial logic layers, each serial logic layer may include multiple logic nodes, each logic node may include preconditions, matching operators, selection operators, node processing, Context, postconditions, and sub-logic layers.

Optionally, the precondition may also be referred to as the first condition. The postcondition may also be referred to as the second condition. The node processing may also be referred to as the node processor. The context may also be referred to as the context update strategy. The logical topology tree may also be referred to as the serialized logical topology tree.

The logical topology tree 203 may be used to query, according to the input sub-link, in the database of the first electronic device 101 or the first electronic device 102 whether the input sub-link has a next sub-link.

Specifically, the logical topology tree 203 may input the first sub-link into the precondition of each logical node in the first logical layer, and determine in turn whether the first sub-link meets the precondition of the logical node. When the first sub-link first encounters a logical node that meets the precondition, the logical node is determined as the target logical node.

Then, after determining that the first sub-link meets the precondition of the target logical node, the logical topology tree 203 may execute the matching operator of the target logical node to match multiple sub-links in the data environment provided by the data support module 204 .

Next, the logical topology tree 203 may execute a selection operator to select a sub-link from the multiple sub-links and determine it as a target sub-link.

Next, the logical topology tree 203 may perform node processing again to process the unselected sub-links, for example, marking the unselected sub-links as backup links.

Next, the logical topology tree 203 may execute Context again to record the main path, backup path, frequency, channel, and quantity of the spliced sub-links in the target link.

Next, the logical topology tree 203 may execute the post-condition again to determine whether the number of spliced sub-links in the target link is greater than a threshold or whether the target link is a spliced sub-link in the target sub-link according to the content recorded in the Context.

When the number of spliced sub-links in the target link is less than or equal to the threshold and the target sub-link is not a spliced sub-link in the target link, the logical topology tree 203 sends the target sub-link to the concatenation engine module 202 .

When the number of spliced sub-links in the target link is greater than the threshold or the target sub-link is a spliced sub-link in the target link, the logical topology tree 203 executes the sub-logical layer to determine whether the target logical node has a sub-logical layer. If the sub-logical layer exists, the logical topology tree 203 inputs the target sub-link into the sub-logical layer and repeats the above operation until the logical topology tree 203 determines that the target sub-link is not found.

The data support module 204 may include a data environment, a data environment based on Redis cache, and a data environment based on ClickHouse. The data environment based on Redis cache and the data environment based on ClickHouse are two implementation methods of the data environment.

The data support module 204 may be used to determine the manner in which the logical topology tree 203 accesses the database.

Optionally, when the logical topology tree 203 performs batch concatenation in units of element management systems (EMS), a data environment based on Redis cache can be used, and when the logical topology tree 203 performs concatenation on a target link, a data environment based on ClickHouse can be used.

The basic hardware structures of the first electronic device 101 and the second electronic device 102 in the link splicing system are similar, and both include the elements included in the link splicing device shown in Figure 3 or Figure 4. The hardware structures of the first electronic device 101 and the second electronic device 102 are introduced below using the link splicing device shown in Figures 3 and 4 as an example.

As shown in Fig. 3, it is a schematic diagram of a hardware structure of a link splicing device provided in an embodiment of the present application. The link splicing device includes a processor 31, a memory 32, a communication interface 33, and a bus 34. The processor 31, the memory 32, and the communication interface 33 can be connected through a bus 34.

The processor 31 is the control center of the link splicing device, which can be a processor or a general term for multiple processing elements. For example, the processor 31 can be a general-purpose central processing unit (CPU) or other general-purpose processors. Among them, the general-purpose processor can be a microprocessor or any conventional processor.

As an embodiment, the processor 31 may include one or more CPUs, such as CPU 0 and CPU 1 shown in FIG. 3 .

The memory 32 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.

In a possible implementation, the memory 32 may exist independently of the processor 31, and the memory 32 may be connected to the processor 31 via a bus 34 to store instructions or program codes. When the processor 31 calls and executes the instructions or program codes stored in the memory 32, the link splicing method provided in the following embodiments of the present application can be implemented.

In the embodiment of the present application, the first electronic device 101 and the second electronic device 102 have different software programs stored in the memory 32, so the first electronic device 101 and the second electronic device 102 implement different functions. The functions performed by each device will be described in conjunction with the following flowchart.

In another possible implementation, the memory 32 may also be integrated with the processor 31 .

The communication interface 33 is used to connect the link splicing device to other devices through a communication network, and the communication network may be Ethernet, wireless access network, wireless local area network (WLAN), etc. The communication interface 33 may include a receiving unit for receiving data and a sending unit for sending data.

The bus 34 may be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, or an extended industry standard architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, FIG3 only uses one thick line, but does not mean that there is only one bus or one type of bus.

Fig. 4 shows another hardware structure of the link splicing device in the embodiment of the present application. As shown in Fig. 4, the link splicing device may include a processor 41 and a communication interface 42. The processor 41 is coupled to the communication interface 42.

The functions of the processor 41 may refer to the description of the processor 31. In addition, the processor 41 also has a storage function and may function as the memory 32.

The communication interface 42 is used to provide data to the processor 41. The communication interface 42 may be an internal interface of the link splicing device, or an external interface of the link splicing device (equivalent to the communication interface 33).

It should be pointed out that the structure shown in FIG. 3 (or FIG. 4 ) does not constitute a limitation on the link splicing device. In addition to the components shown in FIG. 3 (or FIG. 4 ), the link splicing device may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

The link splicing method provided in the embodiment of the present application is described in detail below with reference to the accompanying drawings.

As shown in FIG. 5 , the link splicing method provided in the embodiment of the present application is applied to the first electronic device 101 in the link splicing system shown in FIG. 1 . The link splicing method includes: S501 - S503 .

S501: A first electronic device obtains a plurality of link information corresponding one-to-one to a plurality of sub-links.

The link information includes link start information and link end information.

In one possible implementation, the first electronic device first obtains original link data from multiple element management systems (EMS), then extracts link information from the original link data to obtain link information corresponding to all sub-links in each EMS, and stores the information in a database of the first electronic device. Then, when performing a splicing task, the first electronic device can directly obtain multiple link information corresponding to multiple sub-links from the database.

In another possible implementation, in conjunction with FIG1 , the second electronic device first obtains original link data from each element management system (EMS), extracts link information from the original link data, obtains link information corresponding to all sub-links in each EMS, and stores the information in a database of the second electronic device. Then, when performing a splicing task, the first electronic device can obtain multiple link information corresponding to multiple sub-links from the database of the second electronic device.

S502: When link termination information of other sub-links does not contain link termination information identical to link start information of the target sub-link, the first electronic device determines the target sub-link as the first sub-link of the target link.

Among them, other sub-links are sub-links other than the target sub-link among the multiple sub-links.

Specifically, after acquiring a plurality of link information corresponding to a plurality of sub-links one by one, the first electronic device needs to first determine the first sub-link of the target link.

The specific method for the first electronic device to determine the first sub-link of the target link is: the first electronic device compares whether the link start information of each sub-link in the multiple sub-links is the same as the link termination information of other sub-links. When the link start information of a sub-link (i.e., the target sub-link in the embodiment of the present application) is different from the link termination information of other sub-links, the first electronic device can determine the sub-link as the first sub-link of the target link.

Exemplarily, in the preset target link, the link start information of sublink 1 is A, and the link termination information is B, the link start information of sublink 2 is B, and the link termination information is C, and the link start information of sublink 3 is C, and the link termination information is D. The first electronic device determines that the link start information of sublink 1 is different from the link termination information of sublink 2 and sublink 3, the link start information of sublink 2 is the same as the link termination information of sublink 1, and the link start information of sublink 3 is the same as the link termination information of sublink 2. Therefore, the first electronic device finds that the target sublink is sublink 1, and determines sublink 1 as the first sublink of target link 1.

S503: The first electronic device determines address information of other sub-links according to the first sub-link and the logical topology tree, and splices multiple sub-links based on the address information of other sub-links and the first sub-link to obtain a target link.

The logical topology tree includes a plurality of logical nodes, and the logical node is used to determine the address information of the next sub-link of the sub-link successfully matched with the logical node.

Specifically, after determining the first sub-link of the target link, the first electronic device needs to determine the address information of other sub-links to obtain the target link.

First, the first electronic device inputs the first sub-link into the logical topology tree, and determines whether the logical topology tree outputs the second sub-link.

When the logical topology tree outputs the second sub-link, the first electronic device first uses the addressing function to obtain the address information of the first sub-link and the second sub-link, then adds the address information of the second sub-link to the link termination information of the first sub-link, and adds the address information of the first sub-link to the link start information of the second sub-link, and then the first electronic device inputs the second sub-link into the logical topology tree, and repeats the above operation until the nth sub-link is input into the logical topology tree, and the logical topology tree cannot output the n+1th sub-link. n is a positive integer.

When the logical topology tree cannot output the n+1th sub-link, the first electronic device determines the nth sub-link as the last sub-link. n is a positive integer.

After the last sub-link is determined according to the above operation, the first electronic device has completed the splicing from the first sub-link to the last sub-link and obtains the target link.

Exemplarily, the first sublink of the preset target link 1 is sublink 1. The first electronic device inputs sublink 1 into the logical topology tree to obtain sublink 2. Next, the first electronic device first uses the addressing function to obtain the address information A of sublink 1 and the address information B of sublink 2, and then adds the address information B of sublink 2 to the link termination information of sublink 1, and adds the address information A of sublink 1 to the link start information of sublink 2. Then the first electronic device inputs sublink 2 into the logical topology tree. When the logical topology tree cannot output the third sublink, the first electronic device obtains the target link, which is the link from sublink 1 to sublink 2.

In one embodiment, in combination with FIG. 5 , as shown in FIG. 6 , in the above S503 , the method in which the first electronic device determines the address information of other sub-links according to the first sub-link and the logical topology tree specifically includes: S601 - S605 .

S601: The first electronic device inputs link termination information of the nth sub-link into a logical topology tree.

Wherein, n is a positive integer.

S602: When the logical topology tree includes a logical node that successfully matches the nth sub-link, the first electronic device determines whether the target logical node outputs address information of the (n+1)th sub-link.

The target logical node is the logical node that successfully matches the nth sub-link.

Specifically, after the first electronic device inputs the link termination information of the nth sub-link into the logical topology tree, the link termination information of the nth sub-link is matched with the logical nodes in the logical topology tree one by one until the first successfully matched logical node appears, the matching is stopped, and the first successfully matched logical node is determined as the target logical node. Then, the first electronic device determines whether the target logical node outputs the address information of the n+1th sub-link.

S603: When the target logical node outputs the address information of the n+1th sub-link, the first electronic device repeatedly inputs the link termination information of the n+1th sub-link into the logical topology tree until the logical topology tree cannot match any sub-link.

Specifically, when the target logical node outputs the address information of the n+1th sublink, the first electronic device obtains the address information of the nth sublink. Then, the first electronic device adds the address information of the n+1th sublink to the link termination information of the nth sublink, and adds the address information of the nth sublink to the link start information of the n+1th sublink.

Then, the first electronic device inputs the link termination information of the (n+1)th sub-link into the logical topology tree, and repeatedly performs the above operation of S602 until the logical topology tree cannot match any sub-link.

S604: When the logical topology tree does not include a logical node that successfully matches the nth sublink, or the target logical node cannot output the (n+1)th sublink, the first electronic device determines the nth sublink as the last sublink of the target link.

Specifically, after the first electronic device inputs the link termination information of the nth sub-link into the logical topology tree, the link termination information of the nth sub-link is matched one by one with the logical nodes in the logical topology tree. If no logical node that successfully matches the link termination information of the nth sub-link is found, the first electronic device determines the nth sub-link as the last sub-link of the target link.

Alternatively, if the first electronic device finds a logical node that successfully matches the link termination information of the nth sub-link but the successfully matched logical node does not output the address information of the (n+1)th sub-link, the first electronic device determines the nth sub-link as the last sub-link of the target link.

S605: The first electronic device determines address information of other sub-links according to the address information of the sub-links output by the logical topology tree.

Specifically, according to the above S603, after the logical topology tree outputs the address information of the last sub-link, the first electronic device has successively obtained the address information of the first sub-link, the address information of the second sub-link..., all the way to the address information of the last sub-link, therefore, the first electronic device can determine the address information of other sub-links.

In one embodiment, the logical topology tree includes multiple logical layers. Each logical node includes a first condition. The first condition includes: the link connection type of the nth sub-link is the same as the link connection type configured for the logical node, and/or, the time slot information of the nth sub-link is the same as the time slot information configured for the logical node. In this case, the electronic device can determine whether each logical node has a sub-logical layer according to the logical topology tree. Therefore, in combination with FIG. 6, as shown in FIG. 7, in the above S601, after the link termination information of the nth sub-link is input into the logical topology tree, the link splicing method also includes: S701-S702.

S701: When the link termination information of the nth sub-link meets the first condition corresponding to the first logical node in the mth logical layer, the first electronic device determines the first logical node as the target logical node.

Wherein, m is a positive integer.

Specifically, after the first electronic device inputs the link termination information of the nth sub-link into the logical topology tree, since the first condition of each logical node is different, the first electronic device first determines whether the link termination information of the nth sub-link satisfies the first condition of each logical node in the mth logical layer in the logical topology tree. When the link termination information of the nth sub-link satisfies the first condition corresponding to the first logical node, the first electronic device determines the first logical node as the target logical node.

Optionally, the link termination information may include time slot information.

Exemplarily, it is preset that the link termination information of the second sub-link is input into the logical topology tree, the logical topology tree has logical layer 1, logical layer 2, and logical layer 3, logical layer 1 has logical node A and logical node B, logical layer 2 has logical node C and logical node D, and logical layer 3 has logical node E and logical node F. The first electronic device first determines whether the link termination information of the second sub-link satisfies the first condition of logical node A and logical node B in logical layer 1. When it is determined that the link termination information of the second sub-link satisfies the first condition of logical node B, the first electronic device determines logical node B in logical layer 1 as the target logical node.

S702. When the link termination information of the nth sub-link does not satisfy the first condition corresponding to the first logical node in the mth logical layer, the first electronic device determines whether the m+1th logical layer includes a logical node that satisfies the first condition, until each logical layer does not include a logical node that satisfies the first condition, and determines that the logical topology tree does not include a logical node that successfully matches the nth sub-link.

The (m+1)th logical layer is a sub-logical layer of the first logical node.

Specifically, when the first electronic device does not find the first logical node whose link termination information of the nth sublink satisfies the first condition in the mth logical layer, the first electronic device continues to search for a first logical node that satisfies the first condition in the m+1th logical layer.

When there is a first logical node satisfying the first condition in the (m+1)th logical layer, the first logical node is determined as the target logical node.

When there is no first logical node satisfying the first condition in the m+1th logical layer, the first electronic device continues to search for whether there is a first logical node satisfying the first condition in the m+2th logical layer, until each logical layer does not include a logical node satisfying the first condition, and the first electronic device determines that the logical topology tree does not include a logical node satisfying the first condition.

Exemplarily, it is preset that the link termination information of the second sub-link is input into the logical topology tree, the logical topology tree has a logical layer 1, a logical layer 2, and a logical layer 3, the logical layer 1 has a logical node A and a logical node B, the logical layer 2 has a logical node C and a logical node D, and the logical layer 3 has a logical node E and a logical node F. The first electronic device first determines whether the link termination information of the second sub-link satisfies the first condition of the logical node A and the logical node B in the logical layer 1. When the link termination information of the second sub-link does not satisfy the first condition of the logical node A and the logical node B, the first electronic device determines whether the link termination information of the second sub-link satisfies the first condition of the logical node C and the logical node D in the logical layer 2. When the link termination information of the second sub-link does not satisfy the first condition of the logical node C and the logical node D, the first electronic device determines whether the link termination information of the second sub-link satisfies the first condition of the logical node E and the logical node F in the logical layer 3. When the link termination information of the second sub-link does not satisfy the first condition of the logical node E and the logical node F, the first electronic device determines that the logical topology tree does not include the logical node that satisfies the first condition.

In one embodiment, the first logical node includes: a matching operator, a selection operator, and a second condition. The matching operator is used to: determine the sublink corresponding to the link start information that is the same as the link termination information of the nth sublink in the link start information of the remaining sublinks. The remaining sublinks are sublinks other than the nth sublink among multiple sublinks. The selection operator is used to: determine the sublink with the largest sublink port number value. In this case, the electronic device can determine the address information of the n+1th sublink based on the logical node. The second condition includes: determining whether the number of spliced target links is greater than a threshold or determining whether the second sublink is a sublink in the spliced target link. Therefore, in combination with Figure 7, as shown in Figure 8, in the above S701, after the first logical node is determined as the target logical node, the link splicing method also includes: S801-S804.

S801: A first electronic device executes a matching operator of a first logical node.

Specifically, the first electronic device compares the link termination information of the nth sub-link with the link start information of the remaining sub-links to see whether they are the same, and finds out the first sub-link having the same link termination information as the nth sub-link.

Exemplarily, the link termination information of the second sub-link is preset to be A, the link start information of sub-link 1 is preset to be B, the link start information of sub-link 2 is preset to be A, the link start information of sub-link 3 is preset to be C, and the link start information of sub-link 4 is preset to be D. The first electronic device compares the link termination information of the second sub-link with the link start information of sub-link 1, the link start information of sub-link 2, the link start information of sub-link 3, and the link start information of sub-link 4, and further determines that the first sub-links having the same link termination information as the second sub-link are sub-link 2 and sub-link 4.

S802: When the matching operator matches at least one first sub-link, the first electronic device executes a selection operator of the first logical node.

Specifically, after the matching operator matches at least one first sub-link, the first electronic device determines the size of the port number of the at least one first sub-link, and determines the sub-link with the largest port number as the second sub-link.

Optionally, the termination information of the link may include a port number.

Optionally, there may be multiple selection operators. Each selection operator may correspond to a precondition. The precondition may determine whether to use the corresponding selection operator according to the number of first sub-links.

Exemplarily, the port number of the first sublink 1 is preset to 3, and the port number of the first sublink 2 is preset to 5. The first electronic device compares the port numbers of the first sublink 1 and the first sublink 2, and determines the first sublink 2 as the second sublink.

S803: When the selection operator selects a second sub-link from at least one first sub-link, the first electronic device determines whether the second sub-link satisfies a second condition.

Specifically, after the selection operator selects the second sublink from at least one first sublink, the first electronic device determines whether the number of spliced target links is greater than a threshold and whether the second sublink is a sublink in the spliced target link. Then the first electronic device determines whether the second sublink satisfies the second condition based on the above determination.

Optionally, the threshold value can be set according to user needs, and the embodiment of the present application does not limit the specific value of the threshold value.

S804: When the second sub-link satisfies the second condition, the first electronic device obtains address information of the second sub-link, and determines the address information of the second sub-link as address information of the (n+1)th sub-link.

Specifically, when the first electronic device determines that the number of spliced target links is less than a threshold and the second sub-link is not a sub-link in the spliced target links, it indicates that the second sub-link is the next sub-link of the nth sub-link. Therefore, the first electronic device obtains the address information of the second sub-link and determines the address information of the second sub-link as the address information of the n+1th sub-link.

Exemplarily, the second sublink is preset as sublink 1, the number of spliced target links is 4, the threshold is 10, and the spliced target links include sublink 2, sublink 3, sublink 4, and sublink 5. The first electronic device determines that the number of spliced target links is less than the threshold and the second sublink is not a sublink in the spliced target link, and determines the address information of the second sublink as the address information of the n+1th sublink.

In one embodiment, in combination with FIG. 8 , as shown in FIG. 9 , in the above S801 , after executing the matching operator of the first logical node, the link splicing method further includes: S901 - S902 .

S901: When the matching operator fails to match the first sub-link, the first electronic device determines whether a target logical node has a sub-logical layer.

Specifically, since the matching operator cannot match the first sub-link, the first electronic device determines that the target logical node has not found the next sub-link of the nth sub-link. Then, the first electronic device determines whether the target logical node has a sub-logical layer.

S902: When the matching operator matches at least one first sub-link, and the selection operator selects a second sub-link from the at least one first sub-link, and the second sub-link does not meet the second condition, the first electronic device determines whether the target logical node has a sub-logical layer.

Specifically, although the matching operator matches at least one first sub-link and the selection operator can select a second sub-link from the at least one first sub-link, since the second sub-link does not satisfy the second condition, the first electronic device determines that the target logical node has not found the next sub-link of the nth sub-link. Then, the first electronic device determines whether the target logical node has a sub-logical layer.

In one embodiment, in combination with FIG. 9 , as shown in FIG. 10 , the link splicing method further includes: S1001 - S1002 .

S1001: When a target logical node has a sub-logical layer, the first electronic device determines whether the sub-logical layer of the target logical node includes a logical node that meets a first condition.

Specifically, when the target logical node has a sub-logical layer, because the first electronic device has not found the next sub-link of the nth sub-link in the target logical node, and in order to find the next sub-link of the nth sub-link according to the sub-logical layer, the first electronic device determines whether the sub-logical layer of the target logical node includes a logical node that satisfies the first condition.

For a detailed description of the first electronic device determining whether the sub-logical layer of the target logical node includes a logical node that meets the first condition, reference may be made to the detailed description of S701-S702, which will not be repeated here.

S1002: When the target logical node does not have a sub-logical layer, the first electronic device determines that the target logical node cannot output the (n+1)th sub-link.

Specifically, when the target logical node does not have a sub-logical layer, because the first electronic device has not found the next sub-link of the nth sub-link in the target logical node, and cannot find the next sub-link of the nth sub-link according to the sub-logical layer, the first electronic device determines that the target logical node cannot output the (n+1)th sub-link.

The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the method. In order to realize the above functions, it includes hardware structures and/or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

The embodiment of the present application can divide the link splicing device into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. Optionally, the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

As shown in Figure 11, it is a schematic diagram of the structure of a link splicing device provided in an embodiment of the present application. The link splicing device can be used to execute the link splicing method shown in Figures 5 to 10. The link splicing device shown in Figure 11 includes: an acquisition unit 1101 and a processing unit 1202.

The acquisition unit 1101 is used to acquire a plurality of link information corresponding to the plurality of sub-links one by one; the link information includes link start information and link end information. For example, in conjunction with FIG5 , the acquisition unit 1101 is used to execute S501.

The processing unit 1102 is configured to determine the target sublink as the first sublink of the target link when there is no link termination information identical to the link start information of the target sublink in the link termination information of the other sublinks; the other sublinks are sublinks other than the target sublink among the multiple sublinks. For example, in conjunction with FIG5 , the processing unit 1102 is configured to execute S502.

The processing unit 1102 is further configured to determine the address information of other sub-links according to the first sub-link and the logical topology tree, and to splice multiple sub-links based on the address information of other sub-links and the first sub-link to obtain a target link; the logical topology tree includes multiple logical nodes; the logical node is used to determine the address information of the next sub-link of the sub-link that successfully matches the logical node. For example, in conjunction with FIG5, the processing unit 1102 is further configured to execute S503.

Optionally, the processing unit 1102 is configured to:

Input the link termination information of the nth sub-link into the logical topology tree; n is a positive integer. For example, in conjunction with FIG6 , the processing unit 1102 is further configured to execute S601.

When the logical topology tree includes a logical node that successfully matches the nth sublink, it is determined whether the target logical node outputs the address information of the n+1th sublink; the target logical node is the logical node that successfully matches the nth sublink. For example, in conjunction with FIG6 , the processing unit 1102 is further configured to execute S602.

When the target logical node outputs the address information of the n+1th sublink, the link termination information of the n+1th sublink is repeatedly input into the logical topology tree until the logical topology tree cannot match the sublink. For example, in conjunction with FIG6 , the processing unit 1102 is further configured to execute S603 .

When the logical topology tree does not include a logical node that successfully matches the nth sublink, or the target logical node cannot output the n+1th sublink, the nth sublink is determined as the last sublink of the target link. For example, in conjunction with FIG6 , the processing unit 1102 is further configured to execute S604.

According to the address information of the sub-link output by the logical topology tree, the address information of other sub-links is determined. For example, in conjunction with FIG6 , the processing unit 1102 is further configured to execute S605 .

Optionally, the logical topology tree includes multiple logical layers; each logical node includes a first condition; the first condition includes: the link connection type of the nth sub-link is the same as the link connection type configured for the logical node, and/or, the time slot information of the nth sub-link is the same as the time slot information configured for the logical node.

The processing unit 1102 is further configured to determine the first logical node as the target logical node when the link termination information of the nth sub-link meets the first condition corresponding to the first logical node in the mth logical layer; m is a positive integer. For example, in conjunction with FIG7 , the processing unit 1102 is further configured to execute S701.

The processing unit 1102 is further configured to determine whether the m+1th logical layer includes a logical node that meets the first condition when the link termination information of the nth sub-link does not meet the first condition corresponding to the first logical node in the mth logical layer, until each logical layer does not include a logical node that meets the first condition, and determine that the logical topology tree does not include a logical node that successfully matches the nth sub-link; the m+1th logical layer is a sub-logical layer of the first logical node. For example, in conjunction with FIG7, the processing unit 1102 is further configured to execute S702.

Optionally, the first logical node includes: a matching operator, a selection operator, and a second condition; the matching operator is used to: determine the sublink corresponding to the link start information of the remaining sublinks that is the same as the link termination information of the nth sublink; the remaining sublinks are sublinks other than the nth sublink among multiple sublinks; the selection operator is used to: determine the sublink with the largest sublink port number value; the second condition includes: determining whether the number of spliced target links is greater than a threshold or determining whether the second sublink is a sublink in the spliced target links.

The processing unit 1102 is further configured to execute a matching operator of the first logical node. For example, in conjunction with FIG8 , the processing unit 1102 is further configured to execute S801.

The processing unit 1102 is further configured to execute the selection operator of the first logical node when the matching operator matches at least one first sub-link. For example, in conjunction with FIG8 , the processing unit 1102 is further configured to execute S802.

The processing unit 1102 is further configured to determine whether the second sub-link satisfies the second condition when the selection operator selects the second sub-link from the at least one first sub-link. For example, in conjunction with FIG8 , the processing unit 1102 is further configured to execute S803 .

The processing unit 1102 is further configured to obtain the address information of the second sub-link when the second sub-link satisfies the second condition, and determine the address information of the second sub-link as the address information of the (n+1)th sub-link. For example, in conjunction with FIG8 , the processing unit 1102 is further configured to execute S804.

Optionally, the processing unit 1102 is further configured to determine whether the target logical node has a sub-logical layer when the matching operator fails to match the first sub-link. For example, in conjunction with FIG9 , the processing unit 1102 is further configured to execute S901.

The processing unit 1102 is further configured to determine whether the target logical node has a sub-logical layer when the matching operator matches at least one first sub-link, and the selection operator selects a second sub-link from the at least one first sub-link, and the second sub-link does not meet the second condition. For example, in conjunction with FIG9 , the processing unit 1102 is further configured to execute S902.

Optionally, the processing unit 1102 is further configured to determine whether the sub-logical layer of the target logical node includes a logical node that meets the first condition when the target logical node has a sub-logical layer. For example, in conjunction with FIG10 , the processing unit 1102 is further configured to execute S1001.

The processing unit 1102 is further configured to determine that the target logical node cannot output the n+1th sub-link when the target logical node does not have a sub-logical layer. For example, in conjunction with FIG10 , the processing unit 1102 is further configured to execute S1002 .

An embodiment of the present application further provides a computer-readable storage medium, which includes computer-executable instructions. When the computer-executable instructions are executed on a computer, the computer executes the link splicing method provided in the above embodiment.

The embodiment of the present application also provides a computer program, which can be directly loaded into a memory and contains software code. After being loaded and executed by a computer, the computer program can implement the link splicing method provided in the above embodiment.

Those skilled in the art should be aware that in one or more of the above examples, the functions described in this application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer-readable storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The unit described as a separate component may or may not be physically separated, and the component displayed as a unit may be a physical unit or multiple physical units, that is, it may be located in one place, or it may be distributed in multiple different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the general technology or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a disk, or an optical disk.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims (12)

1. A link splicing method, characterized by comprising: Acquire a plurality of link information corresponding to the plurality of sub-links one by one; the link information includes link start information and link end information; When link termination information of other sub-links does not contain link termination information identical to link start information of the target sub-link, determining the target sub-link as the first sub-link of the target link; the other sub-links are sub-links other than the target sub-link among the multiple sub-links; According to the first sub-link and the logical topology tree, address information of the other sub-links is determined, and the multiple sub-links are spliced based on the address information of the other sub-links and the first sub-link to obtain the target link; the logical topology tree includes multiple logical nodes; the logical nodes are used to determine the address information of the next sub-link of the sub-link that successfully matches the logical node; Wherein, determining the address information of the other sub-links according to the first sub-link and the logical topology tree includes: Inputting the link termination information of the nth sub-link into the logical topology tree; n is a positive integer; When the logical topology tree includes a logical node that successfully matches the nth sublink, determining whether the target logical node outputs address information of the n+1th sublink; the target logical node is the logical node that successfully matches the nth sublink; When the target logical node outputs the address information of the n+1th sub-link, repeatedly inputting the link termination information of the n+1th sub-link into the logical topology tree until the logical topology tree cannot match any sub-link; When the logical topology tree does not include a logical node that successfully matches the nth sublink, or the target logical node cannot output the n+1th sublink, determining the nth sublink as the last sublink of the target link; The address information of the other sub-links is determined according to the address information of the sub-links output by the logical topology tree. 2. The link splicing method according to claim 1, characterized in that the logical topology tree includes multiple logical layers; each logical node includes a first condition; the first condition includes: the link connection type of the nth sub-link is the same as the link connection type configured for the logical node, and/or, the time slot information of the nth sub-link is the same as the time slot information configured for the logical node; After inputting the link termination information of the nth sub-link into the logical topology tree, the method further includes: When the link termination information of the nth sub-link meets the first condition corresponding to the first logical node in the mth logical layer, the first logical node is determined as the target logical node; m is a positive integer; When the link termination information of the nth sub-link does not meet the first condition corresponding to the first logical node in the mth logical layer, determine whether the m+1th logical layer includes a logical node that meets the first condition, until each logical layer does not include a logical node that meets the first condition, and determine that the logical topology tree does not include a logical node that successfully matches the nth sub-link; the m+1th logical layer is a sub-logical layer of the first logical node. 3. The link splicing method according to claim 2, characterized in that the first logical node comprises: a matching operator, a selection operator and a second condition; The matching operator is used to: determine the sublinks corresponding to the link start information that is the same as the link termination information of the n-th sublink among the link start information of the remaining sublinks; the remaining sublinks are the sublinks among the multiple sublinks except the n-th sublink; The selection operator is used to: determine the sublink with the largest sublink port number value; The second condition includes: determining whether the number of spliced target links is greater than a threshold or determining whether the second sub-link is a sub-link in the spliced target link; After determining the first logical node as the target logical node, the method further includes: executing the matching operator of the first logical node; When the matching operator matches at least one first sub-link, executing the selection operator of the first logical node; When the selection operator selects a second sub-link from the at least one first sub-link, determining whether the second sub-link satisfies the second condition; When the second sub-link satisfies the second condition, the address information of the second sub-link is acquired, and the address information of the second sub-link is determined as the address information of the (n+1)th sub-link. 4. The link splicing method according to claim 3, characterized in that after executing the matching operator of the first logical node, it also includes: When the matching operator fails to match the first sub-link, determining whether the target logical node has a sub-logical layer; When the matching operator matches the at least one first sub-link, and the selecting operator selects the second sub-link from the at least one first sub-link, and the second sub-link does not satisfy the second condition, it is determined whether the target logical node has a sub-logical layer. 5. The link splicing method according to claim 4, further comprising: When the target logical node has a sub-logical layer, determining whether the sub-logical layer of the target logical node includes a logical node that meets the first condition; When the target logical node does not have a sub-logical layer, it is determined that the target logical node cannot output the (n+1)th sub-link. 6. A link splicing device, characterized by comprising: an acquisition unit and a processing unit; The acquisition unit is used to acquire a plurality of link information corresponding to the plurality of sub-links one by one; the link information includes link start information and link termination information; The processing unit is configured to determine the target sublink as the first sublink of the target link when link termination information of other sublinks does not contain link termination information identical to link start information of the target sublink; the other sublinks are sublinks other than the target sublink among the multiple sublinks; The processing unit is further used to determine the address information of the other sub-links according to the first sub-link and the logical topology tree, and splice the multiple sub-links based on the address information of the other sub-links and the first sub-link to obtain the target link; the logical topology tree includes multiple logical nodes; the logical node is used to determine the address information of the next sub-link of the sub-link that successfully matches the logical node; Wherein, the processing unit is used to: Inputting the link termination information of the nth sub-link into the logical topology tree; n is a positive integer; When the logical topology tree includes a logical node that successfully matches the nth sublink, determining whether the target logical node outputs address information of the n+1th sublink; the target logical node is the logical node that successfully matches the nth sublink; When the target logical node outputs the address information of the n+1th sub-link, repeatedly inputting the link termination information of the n+1th sub-link into the logical topology tree until the logical topology tree cannot match any sub-link; When the logical topology tree does not include a logical node that successfully matches the nth sublink, or the target logical node cannot output the n+1th sublink, determining the nth sublink as the last sublink of the target link; The address information of the other sub-links is determined according to the address information of the sub-links output by the logical topology tree. 7. The link splicing device according to claim 6, characterized in that the logical topology tree includes multiple logical layers; each logical node includes a first condition; the first condition includes: the link connection type of the nth sub-link is the same as the link connection type configured for the logical node, and/or, the time slot information of the nth sub-link is the same as the time slot information configured for the logical node; The processing unit is further configured to determine the first logical node as the target logical node when the link termination information of the nth sub-link meets the first condition corresponding to the first logical node in the mth logical layer; m is a positive integer; The processing unit is further configured to determine whether the m+1th logical layer includes a logical node that satisfies the first condition when the link termination information of the nth sub-link does not meet the first condition corresponding to the first logical node in the mth logical layer, until each logical layer does not include a logical node that satisfies the first condition, and determine that the logical topology tree does not include a logical node that successfully matches the nth sub-link; the m+1th logical layer is a sub-logical layer of the first logical node. 8. The link splicing device according to claim 7, characterized in that the first logical node comprises: a matching operator, a selection operator and a second condition; The matching operator is used to: determine the sublinks corresponding to the link start information that is the same as the link termination information of the n-th sublink among the link start information of the remaining sublinks; the remaining sublinks are the sublinks among the multiple sublinks except the n-th sublink; The selection operator is used to: determine the sublink with the largest sublink port number value; The second condition includes: determining whether the number of spliced target links is greater than a threshold or determining whether the second sub-link is a sub-link in the spliced target link; The processing unit is further configured to execute the matching operator of the first logical node; The processing unit is further configured to execute the selection operator of the first logical node when the matching operator matches at least one first sub-link; The processing unit is further configured to determine whether the second sub-link satisfies the second condition when the selection operator selects the second sub-link from the at least one first sub-link; The processing unit is further configured to, when the second sub-link satisfies the second condition, obtain the address information of the second sub-link, and determine the address information of the second sub-link as the address information of the (n+1)th sub-link. 9. The link splicing device according to claim 8, characterized in that: The processing unit is further configured to determine whether the target logical node has a sub-logical layer when the matching operator fails to match the first sub-link; The processing unit is further configured to determine whether the target logical node has a sub-logical layer when the matching operator matches the at least one first sub-link, the selection operator selects the second sub-link from the at least one first sub-link, and the second sub-link does not satisfy the second condition. 10. The link splicing device according to claim 9, characterized in that: The processing unit is further configured to, when the target logical node has a sub-logical layer, determine whether the sub-logical layer of the target logical node includes a logical node that meets the first condition; The processing unit is further configured to, when the target logical node does not have a sub-logical layer, determine that the target logical node cannot output the (n+1)th sub-link. 11. A link splicing device, characterized in that it includes a memory and a processor; the memory is used to store computer execution instructions, and the processor is connected to the memory through a bus; when the link splicing device is running, the processor executes the computer execution instructions stored in the memory, so that the link splicing device performs the link splicing method according to any one of claims 1 to 5. 12. A computer-readable storage medium, characterized in that the computer-readable storage medium comprises computer-executable instructions, and when the computer-executable instructions are executed on a computer, the computer executes the link splicing method according to any one of claims 1 to 5.