CN116389809A - Television chip and television - Google Patents

Abstract

The application relates to a television chip and a television, wherein the television chip comprises a Central Processing Unit (CPU), wherein the CPU comprises a four-core 64-bit RISC-V instruction set architecture core, a secondary buffer, an inter-core local interrupt CLINT and a platform-level interrupt control PLIC; the second-level cache is shared by 4 cores of the CPU, and each core comprises a memory management unit MMU, an instruction cache, a data cache and a physical memory protection PMP module; the MMU is used for virtual-real physical address translation; the instruction cache is used for caching instructions; the data cache is used for caching data; the PMP module is used for protecting access of the CPU to the memory and IO under different modes. Therefore, the television chip in the application comprises a four-core 64-bit RISC-V instruction set architecture core, does not depend on the ARM architecture to be matched with the television chip of the Android operating system any more, and improves the safety of televisions.

Description

Television chip and television

Technical Field

The present disclosure relates to the field of television chips, and in particular, to a television chip and a television.

Background

With the development of smart televisions, the security of smart televisions is increasingly important as windows of mass propaganda media. At present, the domestic intelligent television is an ARM architecture matched with an Android operating system, so that risks of being sealed and killed at any time and potential safety hazards exist, and the domestic intelligent television based on a domestic self-chip matched with a domestic operating system is a problem to be solved urgently for a broadcast television system.

Disclosure of Invention

The application provides a television chip and a television, which are used for solving the problem that the intelligent television in the prior art depends on an ARM architecture to be matched with an Android operating system, so that the safety is lower.

In a first aspect, the present application provides a television chip, where the television chip includes a central processing unit CPU, where the CPU includes a four-core 64-bit RISC-V instruction set architecture core, a second-level Cache L2Cache, an inter-core local interrupt CLINT, and a platform-level interrupt control PLIC; the L2Cache is shared by 4 cores of the CPU, and each core comprises a memory management unit MMU, an instruction Cache ICache, a data Cache DCache and a physical memory protection PMP module; the MMU is used for virtual-real physical address translation; the ICache is used for caching instructions; the DCache is used for caching data; the PMP module is used for protecting access of the CPU to the memory and IO under different modes.

Optionally, the television chip further comprises a graphics accelerator GPU; the GPU is used for displaying rendering acceleration pictures.

Optionally, the television chip further includes: the system comprises a phase-locked loop (PLL) unit, a Timer, a real-time clock (RTC), a Direct Memory Access (DMA) and a power management module; the PLL unit is used for controlling and scheduling the television chip; the Timer is used for timing based on the RTC; the DMA is used for storing and transmitting data; the power management module is used for controlling the power supply.

Optionally, the television chip further includes a system bus including an AXI4 bus for mounting a CPU, GPU, and Memory128 bits, a 32-bit AHB bus for mounting a high-speed external device, and a 32-bit APB bus for mounting a low-speed external device.

Optionally, the television chip further comprises a double rate controller DDRC; the DDRC is used for storing and transmitting data.

Optionally, the television chip further comprises a codec; the coder-decoder is used for coding and decoding the audio and video.

Optionally, the television chip further comprises an analog television demodulator and a digital television demodulator.

Optionally, the television chip further comprises an artificial intelligence engine unit for performing at least one of the following operations: display image superdivision, display mode detection, image detection, face detection skin color correction.

Optionally, the television chip further comprises a security module; the security module is used for executing at least one of the following operations: physical isolation, trusted boot, firmware encryption, memory scrambling.

In a second aspect, the present application provides a television comprising the television chip of the first aspect.

Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:

the television chip in the embodiment of the application integrates the four-core 64-bit RISC-V instruction set architecture core, does not depend on the ARM architecture to cooperate with the television chip of the Android operating system any more, and improves the safety of televisions.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic structural diagram of a television chip according to an embodiment of the present application;

fig. 2 is a second schematic structural diagram of a television chip according to an embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.

The embodiment of the application provides a television chip, as shown in fig. 1, the television chip comprises a central processing unit (Central Processing Unit, CPU), wherein the CPU comprises a four-Core 64-bit RISC-V instruction set architecture Core, a secondary Cache L2Cache, inter-Core local interrupt (Core-Local Interruptor, CLINT) and platform-level interrupt control (Platform Level Interrupt Controller, PLIC); the L2Cache is shared by 4 cores of the CPU, and each core comprises a memory management unit (Memory Management Unit, MMU), an instruction Cache ICache, a data Cache DCache and a physical memory protection PMP module;

note that RV64IMAFDC in the embodiments of the present application is a 64bit risc-V core, supporting integer, integer multiply and divide, atomic, single precision floating point, double precision floating point, and 16 bit packed instructions.

MMU, is used for virtual and real physical address translation;

ICache, which is used to cache instruction; and DCache, which is used for caching data; 32KB-256KB may be selected for ICache and DCache in a specific example.

And the PMP module is used for protecting access of the CPU to the memory and IO under different modes. It should be noted that the PMP module is a physical memory protection mechanism specific to the RISC-V architecture.

Therefore, in the application, the television chip integrates the four-core 64-bit RISC-V instruction set architecture core, does not depend on the ARM architecture to cooperate with the television chip of the Android operating system any more, and improves the safety of the television.

In an alternative implementation of the embodiments of the present application, the television chip in the present application further includes a graphics accelerator (Graphics Processing Unit, GPU); and the GPU is used for displaying the rendering acceleration picture. The resolution, fluency and scene details of the product interface display can be greatly improved through the GPU.

In an optional implementation manner of the embodiment of the present application, the television chip in the present application may further include: a phase locked loop (Phase Locked Loop, PLL) unit, timer, real Time Clock (RTC), direct memory access (Direct Memory Access, DMA), and power management module;

the PLL unit is used for controlling and scheduling the television chip; timer, which is used for timing based on RTC; DMA, is used for storage and transmission of the data; and the power management module is used for controlling the power supply.

In the embodiment of the application, JTEG can be built in the television chip for debugging, tracking and using of a developer.

In an alternative implementation in the embodiment of the present application, the tv chip in the present application may further include a system bus, where the system bus includes an AXI4 bus for mounting a CPU, a GPU, and a Memory128 bits, a 32-bit advanced performance bus (Advanced High performance Bus, AHB) bus for mounting a high-speed external device, and a 32-bit peripheral bus (Advanced Peripheral Bus, APB) for mounting a low-speed external device. That is, the television chip adopts a three-level bus architecture in the present application.

In an alternative implementation of the embodiments of the present application, the television chip in the present application further includes a double rate controller (Double Data Rate Controller, DDRC); DDRC for storage and transmission of data. In a specific example, the DDRC in the embodiments of the present application may support 32-bit DDR3/DDR4, with a maximum rate of up to 2800Mbps. In addition, the television chip in the embodiment of the application can also support an external memory such as norflash, nandflash, EMMC.

In addition, in the embodiment of the application, a boot ROM can be supported in the television chip to support the electronic device from the eMMC/SD card

And starting an external memory such as a norflash/nandflash and the like, and supporting a USB/UART starting mode at the same time, wherein the starting mode is used for burning the image file into the memory.

In an optional implementation manner of the embodiment of the present application, the television chip in the embodiment of the present application may further include a codec; and the coder-decoder is used for coding and decoding the audio and video. In a specific example, the codec supports decoding of video formats such as H.264/H.265/Mpeg1/2/4/AVS/VP9, etc., with a maximum resolution of 4K and a maximum frame rate of 60 frames, supports JPEG decoding, and supports JPEG and H.264 encoding.

In addition, the television chip in the embodiment of the application is also internally provided with a digital signal processor (Digital Signal Processor, DSP) for audio, supports TDM/PCM/I2S input, supports PDM to communicate with an external DMIC, supports VAD, supports TDM/PCM/I2S output and supports full duplex SPDIF.

In an alternative implementation of the embodiment of the present application, the television chip of the embodiment of the present application further includes an analog television demodulator and a digital television demodulator. In a specific example, the analog television demodulator may be an analog television demodulator such as NTSC/PAL/SECAM, and the digital television demodulator may be a digital television demodulator supporting DVB-T2/DVB-T/DVB-S2X/DVB-S/DVB-C/ATSC/ISDB-T, etc., which may be used in the global television and set-top box markets.

In an optional implementation manner of the embodiment of the present application, the tv chip in the embodiment of the present application may further be embedded with high-end post-processing units such as HDR, MEMC, and the like, and also support multiple display post-processing such as interlace-to-progressive, film mode detection, image scaling/rotation, noise reduction, antialiasing, sharpening, brightness enhancement, color enhancement, black/white/blue level expansion, dynamic contrast enhancement, backlight adjustment, and the like.

In an alternative implementation manner of the embodiment of the present application, the television chip in the embodiment of the present application further includes an artificial intelligence engine unit, and the artificial intelligence engine unit is configured to perform at least one of the following operations: display image superdivision, display mode detection, image detection, face detection skin color correction.

In an optional implementation manner of the embodiment of the present application, the television chip in the embodiment of the present application further includes a security module; a security module for performing at least one of the following operations: physical isolation, trusted boot, firmware encryption, memory scrambling. In addition, in other examples, the security module also supports encryption algorithms such as AES, DES/3DES, SHA-1/SHA-2, and supports TEE and DRM, chinaDRM.

It should be noted that, the television chip in the embodiment of the present application supports multiple peripheral interfaces, including the following parts:

storage interface: DDR, EMMC, norflash, nandflash, etc.;

video input interface: HDMI, MIPI-CSI, tuner, TS, CVBS, component, etc.;

video output interface: HDMI, MIPI-DSI, V-by-One, TCON, CVBS, LVDS;

audio interface: SPDIF, PDM, TDM, analog L/R,

Universal interface: UART, USB, GPIO, I2C, SPI, ethernet, PWM, IR, etc.

In summary, in the embodiment of the present application, the structure of the tv chip is shown in fig. 2, and includes: CPU, GPU, system bus, central control unit, storage, audio/video coding/decoding, ATV/DTV, image and video post-processing, AI engine, peripheral I/O and security modules.

The television chip in the application is a television product main control chip architecture based on a RISC-V instruction set kernel, and the core CPU processor is a RISC-V architecture, can be matched with different IP according to the periphery, and can be further derived to be used for main control chips of various screen display products such as intelligent televisions, intelligent screens, set TOP boxes, TOPs, outdoor display large screens, advertising machines, projectors and the like. Therefore, the television chip in the embodiment of the application is a television chip based on RISC-V instruction set kernel architecture, and fills the current industry blank; in addition, a television chip based on RISC-V instruction set kernel architecture supports ATV/DTV and other modules, and can be used for the set top box market; in addition, the television chip based on RISC-V instruction set kernel architecture is provided with various video output modules, and can be used in markets such as OTT, advertising machines, large display screens and the like.

It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. The television chip is characterized by comprising a Central Processing Unit (CPU), wherein the CPU comprises a four-core 64-bit RISC-V instruction set architecture core, a secondary Cache L2Cache, an inter-core local interrupt CLINT and a platform-level interrupt control PLIC; the L2Cache is shared by 4 cores of the CPU, and each core comprises a memory management unit MMU, an instruction Cache ICache, a data Cache DCache and a physical memory protection PMP module;

the MMU is used for virtual-real physical address translation;

the ICache is used for caching instructions;

the DCache is used for caching data;

the PMP module is used for protecting access of the CPU to the memory and IO under different modes.

2. The television chip of claim 1, wherein the television chip further comprises a graphics accelerator GPU; the GPU is used for displaying rendering acceleration pictures.

3. The television chip of claim 1, wherein the television chip further comprises: the system comprises a phase-locked loop (PLL) unit, a Timer, a real-time clock (RTC), a Direct Memory Access (DMA) and a power management module;

the PLL unit is used for controlling and scheduling the television chip;

the Timer is used for timing based on the RTC;

the DMA is used for storing and transmitting data;

the power management module is used for controlling the power supply.

4. The television chip of claim 1, further comprising a system bus comprising an AXI4 bus for mounting a CPU, GPU, and Memory128 bits, a 32 bit AHB bus for mounting high speed external devices, and a 32 bit APB bus for mounting low speed external devices.

5. The television chip of claim 1, wherein the television chip further comprises a double rate controller DDRC; the DDRC is used for storing and transmitting data.

6. The television chip of claim 1, wherein the television chip further comprises a codec; the coder-decoder is used for coding and decoding the audio and video.

7. The television chip of claim 1, wherein the television chip further comprises an analog television demodulator and a digital television demodulator.

8. The television chip of claim 1, wherein the television chip further comprises an artificial intelligence engine unit to perform at least one of the following operations: display image superdivision, display mode detection, image detection, face detection skin color correction.

9. The television chip of claim 1, wherein the television chip further comprises a security module; the security module is used for executing at least one of the following operations: physical isolation, trusted boot, firmware encryption, memory scrambling.

10. A television comprising the television chip of any one of claims 1 to 9.

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