CN116383102B

CN116383102B - Translation look-aside buffer access method, device, equipment and storage medium

Info

Publication number: CN116383102B
Application number: CN202310619338.4A
Authority: CN
Inventors: 郇丹丹; 李祖松
Original assignee: Beijing Micro Core Technology Co ltd
Current assignee: Beijing Micro Core Technology Co ltd
Priority date: 2023-05-30
Filing date: 2023-05-30
Publication date: 2023-08-29
Anticipated expiration: 2043-05-30
Also published as: CN116383102A

Abstract

The application discloses a translation backup buffer access method, a device, equipment and a storage medium, wherein the method comprises the following steps: obtaining a virtual address to be converted, and searching a page table corresponding to the virtual address in a primary translation backup buffer; if the primary translation look-aside buffer hits, converting a virtual address to a physical address by utilizing a page table in the primary translation look-aside buffer; if the primary translation look-up buffer is not hit, searching a page table item mapping relation table in the secondary translation look-up buffer according to the virtual address; if the secondary translation look-aside buffer hits, converting the virtual address into a physical address by using a page table item mapping relation table hit in the secondary translation look-aside buffer; if the secondary translation backup buffer is not in a miss, the secondary storage system is accessed through a page table walker PTW, and a page table corresponding to the virtual address is searched in the secondary storage system to convert the virtual address into a physical address. The method reduces the failure rate of the TLB.

Description

Translation look-aside buffer access method, device, equipment and storage medium

Technical Field

The present application relates to the field of computer processors, and in particular, to a method, an apparatus, a device, and a storage medium for accessing a translation look-aside buffer.

Background

The memory management unit (Memory Management Unit, MMU) is responsible for translating Virtual addresses into Physical addresses, so that a programmer does not need to consider the limitation of Physical Address space when writing programs, dynamically allocates Physical memory to each program, and translates Virtual addresses of each program into corresponding Physical addresses. Virtual-to-real address translation may be used to provide a virtual address space for program and data use that is larger than the capacity of physical memory that a processor system is capable of supporting. Virtual-to-real address translation allows each program to assume that it can occupy all the address space of the processor, and the program can use the address resources of the processor arbitrarily, so that address restrictions need not be considered when programming. In order to realize process isolation, each process has own address space, and the used addresses are virtual addresses. Through virtual-to-real address conversion, program protection can be realized, even if two programs use the same virtual address, the two programs can also correspond to different physical addresses, so that the content of each program can be ensured not to be rewritten by other programs at will. Furthermore, sharing among programs can also be achieved by converting different virtual addresses into the same physical addresses.

The MMU is responsible for translating virtual addresses into physical addresses in the processor and then accessing memory with this physical address. At the same time, a permission check is performed, such as whether the writing is possible or not, and the execution is possible. The Page Table is a key component of the MMU, and the Page Table of the MMU, that is, a virtual address to physical address translation Table, is stored in the memory. Since virtual to physical address translations require multiple accesses to memory, access performance is greatly reduced, and translation lookaside buffers (Translation Lookaside Buffer, TLB) are employed to cache on processor slices, with the TLB caching part of Page Table Entries (PTEs) of the Page Table. When a processor sends out a virtual address, the MMU accesses the TLB first, if the TLB contains a virtual-to-real address translation page table item corresponding to the virtual address, the page table item is called TLB hit, namely TLB hit, the address translation is directly carried out by using the page table item, otherwise, the page table item is called TLB miss, namely TLB miss, the MMU accesses the next-level storage system or the memory to find out the relevant virtual-to-real address translation table item for address translation, and meanwhile, the page table item is updated into the TLB. In the prior art, an independent full-connection TLB is adopted for address translation, virtual addresses and each TLB page table item need to be compared one by one to access the full-connection TLB until TLB hit or all TLB page table items are compared, and the storage capacity of the full-connection TLB capable of storing the virtual-real address translation page table items is limited, so that the TLB failure rate is higher, and the performance of a processor is affected.

Therefore, how to reduce TLB failure rate and improve processor performance is a highly desirable problem.

Disclosure of Invention

The application aims to provide a translation look-aside buffer access method, a translation look-aside buffer access device, translation look-aside buffer access equipment and a storage medium, so as to reduce the failure rate of a TLB and improve the performance of a processor.

In order to solve the above technical problems, the present application provides a translation look-aside buffer access method, comprising:

obtaining a virtual address to be converted, and searching a page table corresponding to the virtual address in a primary translation backup buffer;

if the primary translation look-aside buffer hits, converting the virtual address to a physical address using a page table in the primary translation look-aside buffer;

if the primary translation look-up buffer is not hit, searching a page table item mapping relation table in the secondary translation look-up buffer according to the virtual address;

if the secondary translation look-aside buffer is hit, converting the virtual address into a physical address by utilizing a page table item mapping relation table hit in the secondary translation look-aside buffer;

if the secondary translation backup buffer is not in a miss, accessing a lower storage system through a page table walker PTW, searching a page table corresponding to the virtual address in the lower storage system, and converting the virtual address into a physical address.

Preferably, the first-stage translation look-aside buffer comprises a fully-concatenated translation look-aside buffer and a directly-concatenated translation look-aside buffer, wherein the directly-concatenated translation look-aside buffer stores page tables composed of page table entries replaced in the fully-concatenated translation look-aside buffer;

preferably, if the primary translation look-aside buffer hits, the translating the virtual address to a physical address using a page table in the primary translation look-aside buffer includes:

converting the virtual address to a physical address using a page table of the fully-concatenated translation look-aside buffer when the fully-concatenated translation look-aside buffer hits, and converting the virtual address to a physical address using a page table of the directly-concatenated translation look-aside buffer when the directly-concatenated translation look-aside buffer hits;

when the page table of the fully-connected translation look-aside buffer is full and a new page table item needs to be added, determining an old page table item replaced in the page table of the fully-connected translation look-aside buffer according to a replacement policy, replacing the old page table item by the new page table item, writing the new page table item into the fully-connected translation look-aside buffer, and writing the replaced old page table item into the directly-connected translation look-aside buffer.

Preferably, said writing said replaced old page table entry into said directly linked translation look-aside buffer comprises:

dividing virtual address bits in the old page table entry into marks and indexes;

querying the index in the directly connected translation look-up buffer by taking the index as an index value to find a page table item corresponding to the index;

writing the contents of the old page table entry except the index into the searched page table entry of the directly connected translation look-aside buffer.

Preferably, the replacement policy includes Random replacement Random, least recently used LRU, least frequently used LFU, or first in first out FIFO.

Preferably, the second-stage translation look-aside buffer includes a first-stage page table to an N-stage page table, the virtual page number of the second-stage translation look-aside buffer includes a first-stage virtual page number to an N-stage virtual page number, N is a positive integer and N is greater than or equal to 2, and the page table entry mapping relation table includes a first-stage mapping relation table to an nth-stage mapping relation table;

the first-level mapping relation table stores the mapping relation between the first-level virtual page number and a first-level page table item of a first-level page table;

and in the second-level mapping relation table to the Nth-level mapping relation table, each level of mapping relation table stores the mapping relation between the combined virtual page number formed by all virtual page numbers from one level to the level and the level page table item of the level page table.

And if the numerical value of the part, which is the same as the number of the virtual page number and is stored in the mapping relation table, in the virtual address to be converted is the same, the mapping relation table of the level is hit.

Preferably, if the secondary translation look-aside buffer hits, the translating the virtual address into a physical address using a page table entry mapping table hit in the secondary translation look-aside buffer includes:

if the number of the virtual address to be converted is the same as the number of the virtual page number in the N-th level mapping relation table, namely the number of the combined virtual page number formed by all the virtual page numbers from one level to N levels in the virtual address to be converted is the same as the number of the combined virtual page, the N-th level mapping relation table is hit in the second-level translation backup buffer, and the N-level page table item of the N-level page table corresponding to the virtual address is acquired through the N-th level mapping relation table, so that a physical address is obtained;

if the N-level mapping relation table to the K+1-level mapping relation table in the second-level translation backup buffer are not hit, the numerical value of the part with the same number of virtual page numbers stored in the K-level mapping relation table in the virtual address to be translated is the same, namely, the numerical value of the part with the same number of combined virtual page numbers formed by all the virtual page numbers of the first level to the K level stored in the K-level mapping relation table in the virtual address to be translated is the same as the combined virtual page number, the K-level mapping relation table is hit, K is a positive integer, K is greater than or equal to 1 and less than or equal to N-1, the K-level page table item of the K-level page table corresponding to the virtual address is obtained through the K-level mapping relation table, the last-level page table item is utilized to access the current-level page table from the K+1-level page table, the corresponding current-level page table item is searched until the N-level page table is accessed, and the corresponding N-level page table item is searched from the N-level page table item, and the physical address is obtained.

Preferably, the method further comprises:

an N-level page table entry obtained through the second-level translation look-aside buffer is written into the first-level translation look-aside buffer.

Preferably, the method further comprises:

and if the primary translation reserve buffer is missed, acquiring a memory access instruction which is missed by the primary translation reserve buffer, and feeding the memory access instruction back to an emission queue for retransmission.

Preferably, the method further comprises:

setting an access state of the secondary translation look-aside buffer in the transmit queue;

and controlling a feedback retransmission mechanism of the access instruction through the state machine change of the access state.

Preferably, the method further comprises:

setting a counter in the transmission queue, and timing the interval time of feedback retransmission of the access instruction through the counter;

when the value of the counter reaches a timing period, the access state of the secondary translation look-aside buffer in the transmit queue is reset to a ready state.

Preferably, the lower storage system comprises M caches and memories, M is a positive integer and M is greater than or equal to 1, and the counter has m+2 timing periods;

When m=1, the lower-level storage system includes a second-level cache and a memory, where the counter has 3 timing periods, and corresponds to a return period of the second-level translation look-aside buffer hit, a return period of the second-level cache hit, and a return period of the memory, respectively;

when m=2, the lower storage system includes a second level cache, a third level cache, and a memory, where the counter has 4 timing periods, and corresponds to a return period of the second level translation look-aside buffer hit, a return period of the second level cache hit, a return period of the third level cache hit, and a return period of the memory, respectively;

when M is more than or equal to 3, the M caches comprise a second-level cache, a third-level cache, an M+1-level cache and a memory; the counter has M+2 timing periods, which correspond to: the second level translation look-aside buffer hits return cycles, the second level cache, the third level cache up to the m+1 level cache hits return cycles, respectively, and the memory returns cycles.

The application also provides a translation look-aside buffer access device, comprising:

the first searching module is used for acquiring a virtual address to be converted and searching a page table corresponding to the virtual address in the primary translation backup buffer;

A first translation module configured to translate, if the primary translation look-aside buffer hits, the virtual address to a physical address using a page table in the primary translation look-aside buffer;

the second searching module is used for searching a page table item mapping relation table in the second-level translation backup buffer according to the virtual address if the first-level translation backup buffer is not hit;

a second translation module configured to translate the virtual address to a physical address using a page table entry mapping table hit in a second translation look-aside buffer if the first translation look-aside buffer misses and the second translation look-aside buffer hits;

and the third searching module is used for accessing a lower storage system through a page table walker PTW if the primary translation backup buffer is not hit and the secondary translation backup buffer is not hit, searching a page table corresponding to the virtual address in the lower storage system and converting the virtual address into a physical address.

The application also provides a translation look-aside buffer access electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the translation look-aside buffer access method as claimed in any one of the preceding claims when said program is executed.

The present application also provides a computer readable storage medium storing a computer program for execution by a processor to implement the steps of the translation look-aside buffer access method of any of the above.

The application provides a translation look-up buffer access method, which is used for acquiring a virtual address to be translated and searching a page table corresponding to the virtual address in a first-level translation look-up buffer TLB; if the first-level TLB hits, the page table in the first-level TLB is utilized to convert the virtual address into a physical address; if the first level TLB is not hit, searching a page table item mapping relation table in the TLB of the second level translation look-up buffer according to the virtual address; if the second-level TLB is hit, converting the virtual address into a physical address by using a page table item mapping relation table hit in the second-level TLB; if the second-level TLB is not hit, the lower-level storage system is accessed through the page table traversing device PTW, and a page table corresponding to the virtual address is searched in the lower-level storage system to convert the virtual address into a physical address. Therefore, the application not only adopts the first-level TLB to translate the virtual address, but also adopts the second-level TLB to translate the virtual address under the condition that the first-level TLB is not hit, thus the combined use of the first-level TLB and the second-level TLB improves the hit rate of the whole TLB, reduces the failure rate of the TLB and improves the performance of the processor.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a method for accessing a translation look-aside buffer according to the present application;

FIG. 2 is a schematic diagram of address translation in a primary translation look-aside buffer;

FIG. 3 is a schematic diagram showing a memory management unit in a processor;

FIG. 4 is a schematic diagram of RISC-V instruction set Sv39 virtual address translation;

FIG. 5 is a schematic diagram of the overall architecture of a multi-stage translation look-aside buffer;

FIG. 6 is a diagram of a transmit queue feedback retransmission control State State machine transition;

FIG. 7 is a schematic diagram of a translation lookaside buffer accessing apparatus according to the present application;

fig. 8 is a schematic diagram of a translation lookaside buffer access device according to the present application.

Detailed Description

The core of the application is to provide a translation look-aside buffer access method, a device, equipment and a storage medium, so as to reduce the failure rate of TLB and improve the performance of a processor.

In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Referring to fig. 1, fig. 1 is a flowchart of a translation look-aside buffer access method according to the present application, the method includes the following steps:

s11: obtaining a virtual address to be converted, and searching a page table corresponding to the virtual address in a primary translation backup buffer;

s12: if the primary translation look-aside buffer hits, converting the virtual address to a physical address using a page table in the primary translation look-aside buffer;

s13: if the primary translation look-up buffer is not hit, searching a page table item mapping relation table in the secondary translation look-up buffer according to the virtual address;

s14: if the secondary translation look-aside buffer is hit, converting the virtual address into a physical address by using a page table item mapping relation table hit in the secondary translation look-aside buffer;

S15: if the secondary translation backup buffer is not in a miss, the secondary storage system is accessed through a page table traversing device, and a page table corresponding to the virtual address is searched in the secondary storage system to convert the virtual address into a physical address.

The lower-level storage system comprises a memory, and further comprises one or more Cache memories. When the number M of the caches is 1, the lower storage system comprises a second-level Cache and a memory. When the number M of the caches is 2, the lower storage system comprises a second-level Cache, a third-level Cache and a memory. When the number M of the caches is more than or equal to 3, the lower storage system comprises a second-level Cache, a third-level Cache, up to M+1-level Cache and a memory.

It should be noted that, the translation look-aside buffer is referred to as a TLB, the first-stage translation look-aside buffer is referred to as a first-stage TLB, and the second-stage translation look-aside buffer is referred to as a second-stage TLB. The full-concatenated translation look-aside buffer is referred to as a full-concatenated TLB, the direct-concatenated translation look-aside buffer is referred to as a direct-concatenated TLB, and the group-concatenated translation look-aside buffer is referred to as a group-concatenated TLB. In the present application, the TLB may be a multi-level TLB structure, in addition to a combination of the first-level TLB and the second-level TLB, and the combination of the first-level TLB and the second-level TLB may be plural, and is not limited.

Therefore, the method not only adopts the first-level TLB to translate the virtual address, but also adopts the second-level TLB to translate the virtual address under the condition that the first-level TLB is not hit, so that the combined use of the first-level TLB and the second-level TLB improves the hit rate of the whole TLB, reduces the failure rate of the TLB and improves the performance of the processor.

Based on step S11, the first-level TLB includes a full-join TLB, which is a full-join translation look-aside buffer, and a direct-join TLB, which is a direct-join translation look-aside buffer, in which the stored page table is composed of page table entries replaced in the full-join TLB. In detail, the virtual address to be translated is obtained, and the full-connection TLB and the direct-connection TLB in the first-level TLB are queried simultaneously according to the virtual address.

S12: if the primary translation look-aside buffer hits, the page table in the primary translation look-aside buffer is utilized to translate the virtual address to a physical address.

When the full-linked translation look-aside buffer hits, the page table of the full-linked translation look-aside buffer is utilized to convert the virtual address into a physical address, and when the direct-linked translation look-aside buffer hits, the page table of the direct-linked translation look-aside buffer is utilized to convert the virtual address into the physical address; when the page table of the fully-connected translation look-aside buffer is full and a new page table entry needs to be added, determining an old page table entry replaced in the page table according to a replacement policy, replacing the old page table entry by the new page table entry, writing the new page table entry into the fully-connected translation look-aside buffer, and writing the replaced old page table entry into the directly-connected translation look-aside buffer. Among them, the replacement policy includes Random replacement Random, least recently used LRU, least frequently used LFU, or first in first out FIFO.

In the method, for the virtual address, the full-connection TLB and the direct-connection TLB in the first-stage TLB are used for inquiring simultaneously, the direct-connection TLB stores the replaced old page table item content in the full-connection TLB, the full-connection TLB is used for address conversion or the direct-connection TLB is used for address conversion, and no single full-connection TLB is used for address conversion, so that the capacity of the full-connection TLB is reduced, the access speed of page table item comparison in the full-connection TLB is ensured, frequent conflict replacement is avoided, the direct-connection TLB has high access speed, larger capacity can be realized, and the hit rate and the access speed of the first-stage TLB are improved.

The full-connection TLB and the direct-connection TLB are used together, so that the hit rate of the whole first-level TLB is improved, the direct-connection TLB has a replacement buffer function on the full-connection TLB, the item which is replaced by the full-connection TLB recently is the item which is most likely to be accessed in the future, the failure rate of the TLB is reduced, and the performance of the processor is improved.

The first-level TLB adopts an organization structure combining full connection and direct connection, comprises a common page and a large page, can support multiple simultaneous accesses, is replaced by adopting a replacement strategy such as least recently used LRU, and the like, can support PMA (Physical Memory Attribute ), and can query the PMA and write the result into the first-level TLB when the first-level TLB is filled. The storage contents of the first-level TLB include Valid bit, virtual Page number TAG (also referred to as VPN), physical Page number PPN, page Size information Size bit identifying normal and big pages, control information PTE flags in Page table entry PTE, information PMA flags in physical memory attribute PMA, page Fault, and the like.

In detail, in the process of writing the replaced old page table item into the direct-connected TLB, firstly, dividing virtual address bits in the old page table item into marks and indexes, using the indexes as index values to search in the direct-connected TLB, searching the page table item corresponding to the indexes, and then writing the contents except the indexes in the old page table item into the searched page table item of the direct-connected TLB.

In the replacement process, a full-link TLB page table item to be replaced is selected according to a replacement strategy, then, according to an index in a virtual address bit of the full-link TLB page table item, a direct-link TLB page table item corresponding to the index is found out in a direct-link TLB, and contents except the index in the full-link TLB page table item are written into the direct-link TLB page table item corresponding to the index. And finally, writing the content of the new TLB page table entry into the full-connected TLB page table entry to be replaced.

The direct-connected TLB is originally an empty page table, no storage content exists, new page table entries are added after the full-connected TLB is full, new page table entries are written into the full-connected TLB, replaced old page table entries are written into the direct-connected TLB empty table, each time the new page table entries are added into the full-connected TLB, the original stored old page table entries are stored into the direct-connected TLB, and thus the direct-connected TLB gradually stores a plurality of old page table entries originally existing in the full-connected TLB.

FIG. 2 is a schematic diagram of address translation in a primary translation look-aside buffer, wherein the number of bits of the virtual address of the access instruction (i.e., the virtual address to be translated) is not limited in the present application, and the virtual address of the access instruction is 39 bits, wherein bits 0-11 are offset in a page, bits 12-23 are index bits, and bits 24-38 are tag bits.

When the first-level TLB is accessed for address translation, the full-contiguous TLB and the direct-contiguous TLB are queried simultaneously. The full-contiguous TLB is accessed, and address bits of the virtual address of the access instruction (namely, a mark bit and an index bit in the virtual address of the access instruction) except for an offset in a page are compared with the virtual address bits of each page table entry memory of the full-contiguous TLB, if one entry is equal, the full-contiguous TLB is hit, and the entry is a hit entry of the full-contiguous TLB. Accessing the direct-connected TLB, using index bit in virtual address of access instruction as index to search direct-connected TLB page table item correspondent to index bit, using mark bit of said direct-connected TLB page table item to make comparison with mark bit in virtual address of access instruction, if one item is identical, then the direct-connected TLB access is hit, and said item is hit item of direct-connected TLB. The selector in fig. 2 is a selector of either one, the input end is the left end, if the full-link TLB hits, the physical address bit of the full-link TLB hit is selected as the physical page number, if the direct-link TLB hits, the physical address bit of the direct-link TLB hit is selected as the physical page number, the physical page number and the intra-page offset are combined into a physical address, and the physical address is the physical address corresponding to the virtual address of the memory access instruction.

When the full-connected TLB and the direct-connected TLB are not hit, the first-level TLB access is disabled, and then the second-level TLB is accessed, and the corresponding page table item is fetched.

When the full-contiguous TLB is full and needs replacement, one item in the full-contiguous TLB is replaced according to a replacement algorithm, and the replaced item is written into a direct-contiguous TLB page table item corresponding to the index of the virtual address cached by the item. If the directly-coupled TLB is 4KB, then the index of the directly-coupled TLB page table entry is the lower 12 bits of the virtual address, except for offset, that the replacement entry in the fully-coupled TLB exists. Virtual address bits except for the offset and the index of the full-contiguous TLB page table entry stored in the replacement entry in the full-contiguous TLB are used as marking bits of the direct-contiguous TLB page table entry, and the marking bits are stored in the page table entry corresponding to the index of the direct-contiguous TLB.

The first level TLB includes a full-contiguous TLB and a direct-contiguous TLB, or the first level TLB includes a full-contiguous TLB and a group-contiguous TLB, or the first level TLB includes a group-contiguous TLB and a direct-contiguous TLB. The TLB is divided into a fully-contiguous, directly-contiguous, and group-contiguous organization. The combination of the TLBs may be that the full-connected TLB and the group-connected TLB are used together, or that the group-connected TLB and the direct-connected TLB are used together, and the number and combination of TLBs in different mapping modes are not limited in the present application.

In the application, the full-connection TLB and the direct-connection TLB are simultaneously queried, and the direct-connection TLB stores the replaced content in the full-connection TLB. The fully-connected TLB guarantees access speed for fully-connected comparisons by reducing capacity, while avoiding frequent conflicting substitutions. The access speed of the directly connected TLB is high, and larger capacity can be realized. The full-connected TLB and the direct-connected TLB are used together, so that the hit rate of the whole TLB is improved.

as shown in fig. 3, the memory management unit MMU in this embodiment includes a first-level translation look-aside buffer, abbreviated as a first-level TLB, and a second-level translation look-aside buffer, abbreviated as a second-level TLB, where virtual-to-real address translation is performed by the two-level TLB in a hardware implementation. The first-level Cache and the second-level Cache are positioned in the processor, the first-level Cache is called first-level Cache for short, and the second-level Cache is called second-level Cache for short. In order to avoid polluting the primary Cache, the page table walker directly accesses the secondary Cache for access, the bus width returned by the secondary Cache is generally one or half of the secondary Cache line, and the page table walker directly accesses the secondary Cache to obtain wider access bandwidth, such as 256 bits or 512 bits.

In detail, the second-level TLB is an inclusion relationship with respect to the first-level TLB, and a page table miss of the first-level TLB is automatically found and retrieved from the second-level TLB, and the hardware automatically maintains the inclusion relationship, wherein the second-level TLB includes all page tables stored in the first-level TLB. If the first level TLB misses, a request is sent to the second level TLB, and when the second level TLB misses, PTW (Page Table Walker ) is used to access page table contents in Cache or memory. When the Page table is not in the memory, the Page Fault access to the hard disk is triggered to finish.

Based on the method, after the second-level TLB is utilized to search the page table entry corresponding to the virtual address, the page table entry searched in the second-level TLB is written into the first-level TLB.

Currently, processors typically employ a multi-level page table structure that uses multi-level page tables to translate virtual addresses to physical addresses. For example, a RISC-V instruction set (Reduced Instruction Set Computer-Five generation reduced instruction set) processor supporting an Sv39 paging mechanism, the virtual address length is 39 bits, as shown in fig. 4, the virtual address is a RISC-V instruction set Sv39 virtual address, the low 12 bits of the virtual address are intra-page offsets, the middle 27 bits are divided into three segments, that is, three-layer page tables, which means that three memory accesses need to be performed to traverse the page tables, the middle 27 bits are divided into three segments of virtual page numbers, that is, a first-stage virtual page number VPN [2], a second-stage virtual page number VPN [1], and a third-stage virtual page number VPN [0], which represent virtual page numbers of the first-stage page table, the second-stage page table, and the third-stage page table, respectively. The PPN field in the satp (Supervisor Address Translation and Protection ) register holds the physical address of the root page table, which takes the page size of 4KB as a unit, PPN is the physical page number, so that the physical address of the root page table can be obtained according to the satp register, and the root page table can be searched. Sv39 denotes a virtual memory system with an address length of 39 bits, using a base page 4KB in size, the Sv39 page table contains 512 page table entries PTE, each page table entry being 8 bytes, each page occupying 512×8=4096 bytes, the page table entries being composed of Reserved bits Reserved, a physical page number PPN, a software Reserved bit RSW, and control information. Sv39 supports a three-level page table structure, with the low 12 bits of physical and virtual addresses representing the intra-page offset.

Referring to FIG. 4, FIG. 4 is a schematic diagram of a RISC-V instruction set Sv39 address translation, the satp.PPN gives a base address of a first-order page table, i.e., a root page table, and the virtual address VA [38:30] gives a first-order virtual page number, so that the processor obtains the first-order page table base address through the satp, searches the first-order page table, finds a page table entry address by using the first-order page table base address and the first-order virtual page number, and obtains a corresponding page table entry according to the page table entry address in the first-order page table, i.e., reads the page table entry located at the address (satp.PPN4096+VA [38:30 ]. Times.8) from the first-order page table. The read primary page table entry in the primary page table contains the base address of the secondary page table, the PPN field in the page table entry gives the base address of the secondary page table, the virtual address VA [29:21] gives the secondary virtual page number, the address of the page table entry is found by using the base address of the secondary page table and the secondary virtual page number to obtain the corresponding page table entry, so that the processor reads the page table entry located at the address (L1PTE.PPN4096+VA [29:21 ]. Times.8), namely the secondary page table entry, from the secondary page table. The read page table entry in the second-level page table contains the base address of the third-level page table, namely the leaf node page table, the PPN field in the page table entry gives the third-level page table base address, the third-level page table is searched, the virtual address VA [20:12] gives the third-level virtual page number, the page table entry address is found by using the third-level page table base address and the third-level virtual page number to obtain the corresponding page table entry, and therefore the processor reads the leaf node page table entry positioned at the address (L2PTE.PPN4096+VA [20:12 ]. Times.8), namely the third-level page table entry. The PPN field and intra-page offset (the lowest 12 valid bits of the original virtual address) of the leaf node page table entry constitute the final physical address, and the physical address corresponding to the Sv39 virtual address is (LeafPTE PPN 4096+VA 11:0). Therefore, in the process of address conversion by using the three-level page table, the first-level page table is searched, and the last page table item, namely the three-level page table item, is obtained after the three-level page table access, so that the physical address is obtained, the access times are more, and the access speed is influenced.

The second-level translation look-aside buffer comprises a first-level page table to an N-level page table, the virtual page number of the second-level translation look-aside buffer comprises a first-level virtual page number to an N-level virtual page number, N is a positive integer and is more than or equal to 2, and the page table item mapping relation table comprises a first-level mapping relation table to an N-level mapping relation table.

The first-level mapping relation table stores the mapping relation between the first-level virtual page number and the first-level page table item of the first-level page table;

Based on the method, the page table item mapping relation table comprises a first-level mapping relation table and a second-level mapping relation table when N=2; the second-level mapping relation table stores the mapping relation between the combined virtual page number formed by the first-level virtual page number and the second-level page table item of the second-level page table, and the first-level mapping relation table stores the mapping relation between the first-level virtual page number and the first-level page table item of the first-level page table; when n=3, the page table item mapping relation table comprises a first-level mapping relation table, a second-level mapping relation table and a third-level mapping relation table; the third-level mapping relation table stores the mapping relation between the combined virtual page number formed by the first-level virtual page number, the second-level virtual page number and the third-level page table item of the third-level page table, the second-level mapping relation table stores the mapping relation between the combined virtual page number formed by the first-level virtual page number and the second-level page table item of the second-level page table, and the first-level mapping relation table stores the mapping relation between the first-level virtual page number and the first-level page table item of the first-level page table.

When N is greater than or equal to 4, the page table item mapping relation table comprises a first-level mapping relation table and a second-level mapping relation table until an Nth-level mapping relation table; the N-1-th mapping relation table stores the mapping relation between the combined virtual page number formed by the first-stage virtual page number and the second-stage virtual page number up to all virtual page numbers of N stages and the N-stage page table item of the N-stage page table, the N-1-th mapping relation table stores the mapping relation between the combined virtual page number formed by the first-stage virtual page number and the second-stage virtual page number up to all virtual page numbers of N-1 stages and the N-1-stage page table item of the N-1 stage page table, and so on, the second-stage mapping relation table stores the mapping relation between the combined virtual page number formed by the first-stage virtual page number and the second-stage page table item of the second-stage page table, and the first-stage mapping relation table stores the mapping relation between the first-stage virtual page number and the first-stage page table item of the first-stage page table, wherein the N-stage page table item is located in the N-stage page table, and the N-1-stage page table item is located in the N-1-stage page table.

In this embodiment, taking N as 3 as an example, as shown in fig. 5, the second-level TLB includes a page table entry mapping table and a page table walker PTW, and the page table entry mapping table of the second-level TLB includes a first-level mapping table, a second-level mapping table and a third-level mapping table.

Based on step S13, in the process of searching the page table entry mapping table in the second-level translation look-up buffer according to the virtual address, first, the third-level mapping table in the page table mapping table is searched, if the third-level mapping table is not hit, the second-level mapping table is searched, and if the second-level mapping table is not hit, the first-level mapping table is searched.

Based on step S14, if the secondary translation look-aside buffer hits, the virtual address is translated to a physical address using the page table entry mapping table hit in the secondary translation look-aside buffer.

If the number of the virtual address to be converted is the same as the number of the virtual page number in the N-th level mapping relation table, namely the number of the combined virtual page number formed by all the virtual page numbers from one level to N levels in the virtual address to be converted is the same as the number of the combined virtual page number, the N-th level mapping relation table is hit in the second-level translation backup buffer, and the N-level page table item of the N-level page table corresponding to the virtual address is obtained through the N-th level mapping relation table, so that the physical address is obtained;

If the N-level mapping relation table to the K+1-level mapping relation table in the second-level translation backup buffer are missed, the numerical value of the same part of the virtual address to be translated, which is the same as the number of virtual page numbers stored in the K-level mapping relation table, is the same, namely the numerical value of the same part of the combined virtual page numbers formed by all the virtual page numbers of the first level to the K level stored in the K-level mapping relation table in the virtual address to be translated is the same as the combined virtual page numbers, the K-level mapping relation table is hit, K is a positive integer, K is greater than or equal to 1 and less than or equal to N-1, the K-level page table item of the K-level page table corresponding to the virtual address is obtained through the K-level mapping relation table, the last-level page table item is used for accessing the corresponding page table from the K+1-level page table until the N-level page table is accessed, and the corresponding N-level page table item is searched from the N-level page table is obtained, and the physical address is obtained.

Based on the method, in detail, when n=2, if the second-level mapping relation table hits, i.e. hits the nth-level mapping relation table, the second-level page table item of the second-level page table corresponding to the virtual address is obtained through the second-level mapping relation table, and a physical address is obtained; if the second-level mapping relation table is not hit, the first-level mapping relation table is hit, namely K=1, a first-level page table item of a first-level page table corresponding to the virtual address is obtained through the first-level mapping relation table, the second-level page table is accessed through the first-level page table item, and the second-level page table item is searched from the second-level page table to obtain the physical address.

When n=3, if the third-level mapping relation table hits, i.e. hits the nth-level mapping relation table, obtaining a third-level page table item of the third-level page table corresponding to the virtual address through the third-level mapping relation table, and obtaining a physical address; if the third-level mapping relation table is not hit, the second-level mapping relation table is hit, namely K=2, a second-level page table item of a second-level page table corresponding to the virtual address is obtained through the second-level mapping relation table, the third-level page table is accessed through the second-level page table item, and the third-level page table item is searched from the third-level page table to obtain a physical address; if the third-level mapping relation table is not hit and the second-level mapping relation table is not hit, the first-level mapping relation table is hit, namely K=1, a first-level page table item of a first-level page table corresponding to the virtual address is obtained through the first-level mapping relation table, the first-level page table item is utilized to access a second-level page table, the second-level page table item is searched from the second-level page table, the second-level page table item is utilized to access a third-level page table, the third-level page table item is searched from the third-level page table, and a physical address is obtained;

when N is greater than or equal to 4, if the N-level mapping relation table hits, obtaining an N-level page table item of an N-level page table corresponding to the virtual address through the N-level mapping relation table, and obtaining a physical address; if the N-level mapping relation table is not hit, the N-1-level mapping relation table is hit, namely K=N-1, the N-1-level page table item of the N-1-level page table corresponding to the virtual address is obtained through the N-1-level mapping relation table, the N-1-level page table item is utilized to access the N-level page table, the N-level page table item is searched from the N-level page table, and a physical address is obtained; if the N-level mapping relation table and the N-1-level mapping relation table are not hit until the K+1-level mapping relation table is hit, the K-level page table item of the K-level page table corresponding to the virtual address is obtained through the K-level mapping relation table, the K+1-level page table is accessed by the K-level page table item, the K+1-level page table item is searched from the K+1-level page table, and the like, until the N-level page table is accessed by the N-1-level page table, the N-level page table item is searched from the N-level page table, the physical address is obtained, K is a positive integer, and K is more than or equal to 1 and less than or equal to N-1.

Taking n=3 as an example, the second-level translation look-up buffer includes a first-level page table to a third-level page table, the virtual page number of the second-level translation look-up buffer includes a first-level virtual page number to a third-level virtual page number, 30-38 bits are the first-level virtual page number, 21-29 bits are the second-level virtual page number, and 12-20 bits are the third-level virtual page number, and in the process of converting the virtual address into the physical address by using the page table entry mapping relation table in the second-level TLB, the third-level mapping relation table of the second-level TLB is queried according to the virtual address; if the third-level mapping relation table hits, namely the 12-38 bits in the virtual address to be converted are the same as the combined virtual page number formed by the first-level virtual page number, the second-level virtual page number and the third-level virtual page number in the third-level mapping relation table, acquiring a third-level page table item of the third-level page table corresponding to the virtual address through the third-level mapping relation table, and obtaining the physical address. If the third-level mapping relation table is not hit, a second-level mapping relation table is queried, if the second-level mapping relation table is hit, namely, the 21-38 bits in the virtual address to be converted are the same as the combined virtual page number formed by the first-level virtual page number and the second-level virtual page number in the second-level mapping relation table, the second-level page table entry of the second-level page table corresponding to the virtual address is acquired through the second-level mapping relation table, the third-level page table is accessed by the second-level page table entry, and the third-level page table entry is queried from the third-level page table, so that the physical address is obtained. If the third-level mapping relation table is not hit, the second-level mapping relation table is not hit, the first-level mapping relation table is queried, if the first-level mapping relation table is hit, namely, 30-38 bits in a virtual address to be converted are the same as the numerical value of a first-level virtual page number in the first-level mapping relation table, a first-level page table item of a first-level page table corresponding to the virtual address is obtained through the first-level mapping relation table, a second-level page table is accessed through the first-level page table item, a second-level page table item is queried from the second-level page table, a third-level page table is accessed through the second-level page table item, and a third-level page table item is queried from the third-level page table, so that a physical address is obtained. If the third-level mapping relation table, the second-level mapping relation table and the first-level mapping relation table are all missed, the second-level TLB is indicated to be missed.

The physical address can be obtained after the three-level page table entry is searched, namely, the physical page number is obtained from the three-level page table entry, the physical page number is combined with the intra-page offset of the virtual address, and the combination result is the physical address corresponding to the virtual address.

Wherein, the tertiary page table entry is written into the first-level TLB after each search of the tertiary page table entry. Specifically, if the third-level mapping relation table hits, writing the third-level page table item searched in the third-level page table into the first-level TLB, and if the third-level mapping relation table misses and the second-level mapping relation table hits, writing the third-level page table item searched in the third-level page table into the first-level TLB; if the third-level mapping relation table is not hit and the second-level mapping relation table is not hit, the first-level mapping relation table is hit, and finally the third-level page table item searched from the third-level page table is written into the first-level TLB. In the prior art, in the process of performing address conversion by using a three-level page table, a first-level page table is searched, and a last page table item, namely a three-level page table item, is obtained after three-level page table access, so that a physical address is obtained, the access times are more, and the access speed is influenced. In the method, three mapping relation tables are arranged in the second-level TLB, if the third-level mapping relation table hits, the third-level page table item corresponding to the virtual address can be directly obtained without accessing the first-level page table, the second-level page table and the third-level page table. If the second-level mapping relation table hits, a second-level page table item is obtained from the second-level mapping relation table, the third-level page table is accessed through the second-level page table item, the third-level page table item is searched from the third-level page table, and only the third-level page table is required to be accessed, and the first-level page table and the second-level page table are not required to be accessed. If the first-level mapping relation table hits, a first-level page table item is obtained from the first-level mapping relation table, the second-level page table is accessed through the first-level page table item, the second-level page table item is searched from the second-level page table, the third-level page table item is searched from the third-level page table through the second-level page table item, and only the second-level page table and the third-level page table are required to be accessed, and the first-level page table is not required to be accessed. Therefore, the number of page table accesses in the whole access process is reduced, the page table access time is saved, and the access speed is improved.

The virtual address consists of a primary virtual page number, a secondary virtual page number, a tertiary virtual page number and an intra-page offset. The first level virtual page number corresponds to a first level page table entry, the second level virtual page number corresponds to a second level page table entry, and the third level virtual page number corresponds to a third level page table entry.

Based on step S15, if the secondary translation look-up buffer is not hit, the page table corresponding to the virtual address is searched in the lower storage system by accessing the lower storage system through the page table walker, and the virtual address is converted into the physical address. Wherein, three-stage page tables are used to translate virtual addresses to physical addresses.

Further, if the page table corresponding to the virtual address is not searched in the lower storage system, accessing the memory through a page table walker, searching the page table corresponding to the virtual address, and converting the virtual address into a physical address by adopting the three-level page table.

In the process of converting the virtual address into the physical address by adopting the three-level page table, acquiring a first-level page table item by using the first-level page table, acquiring a second-level page table item by using the second-level page table, acquiring a third-level page table item by using the third-level page table, and acquiring the physical address by using the third-level page table item. In the whole address conversion process, a first-stage page table item, a second-stage page table item and a third-stage page table item are acquired. Further, in the method, when the three-level page table is searched through the three-level page table each time, a mapping relation table between a first-level virtual page number and the first-level page table entry is stored in a first-level mapping relation table in the second-level TLB, a mapping relation table between a combined virtual page number formed by the first-level virtual page number and the second-level page table entry is stored in a second-level mapping relation table in the second-level TLB, and a mapping relation table between a combined virtual page number formed by the first-level virtual page number, the second-level virtual page number and the third-level page table entry is stored in a third-level mapping relation table in the second-level TLB.

The third-level page table entry is obtained through the second-level translation look-aside buffer, and is written into the first-level translation look-aside buffer.

Based on the method, further, if the first-level TLB is not hit, a memory access instruction which is not hit by the first-level TLB is acquired, and the memory access instruction is fed back to the transmission queue for retransmission. Setting the access state of the second-level TLB in the transmission queue; the feedback retransmission mechanism of access instructions is controlled by state machine changes in the access state of the second-level TLB. Setting a counter in a transmission queue, and timing the interval time of feedback retransmission of the access instruction through the counter; when the value of the counter reaches the timing period, the access state of the second level TLB in the issue queue is reset to the ready state.

The virtual-to-real address translation work of the TLB of the present embodiment is done by a two-level TLB in a hardware implementation. The first level TLB miss is followed by a lookup of the second level TLB. In order to avoid the TLB miss blocking the pipeline, the application proposes a mechanism for feeding back an instruction of the first level TLB miss to an emission queue to re-emit replay. Because the second-level TLB is possible to hit, the further second-level TLB is possible to hit in a third-level mapping relation table, or to miss in the third-level mapping relation table, or in the second-level mapping relation table, or in the first-level mapping relation table, the PTW needs to access the second-level Cache and the memory for different times, and the required access time is also different. Page Fault may also occur, requiring access to the hard disk, requiring an order of magnitude increase in time.

By setting the access state of the secondary TLB in the transmit queue or reservation station, the control of the TLB miss feedback retransmission mechanism is performed by state machine change of the state. Where in some processors the issue queue function is incorporated into the reservation station, the access state of the second level TLB is set in the reservation station. Meanwhile, a counter is arranged in the transmission queue to count the interval time of feedback retransmission, and the time counted each time is counted according to different levels of the time of the second-level TLB access. The value of the counter is reached, and the TLB access state of the issue queue access instruction is set to a ready state. Namely, a counter is added in a transmitting queue, and the multi-stage retransmission period adjustment is performed in cooperation with the PTW behavior.

For example, in four-level retransmission cycles, a counter is set per transmit queue entry. The retransmission needs to consider the behavior of the second-level TLB, the second-level TLB hits the third-level mapping relation table and returns directly, wherein the second-level TLB can be set to be 2-4 beats, and the 2-4 beats represent 2 times to 4 times of the clock period of the processor, and the clock period of the processor is equal to the reciprocal of the main frequency of the processor; hit in the second-level mapping relation table and one access; hit in the first-level mapping relation table, and access for two times; the mapping relation table is totally missed and accessed for three times; different periods are set according to access delay. The setting of these cycle times can be set statically or dynamically according to the secondary Cache access time access of the processor, the memory access time Memory Access Latency, and the number of accesses required.

When the lower level storage system includes M caches and memory, the counter has m+2 timer cycles. When m=1, the lower storage system includes a second-level Cache and a memory, and the counter has 3 timing periods, which respectively correspond to a return period of the second-level translation look-aside buffer hit, a return period of the second-level Cache hit, and a return period of the memory. When m=2, the lower storage system includes a second level Cache, a third level Cache and a memory, and the counter has 4 timing periods corresponding to a return period of the second level translation look-aside buffer hit, a return period of the second level Cache hit, a return period of the third level Cache hit, and a return period of the memory, respectively. When M is more than or equal to 3, the M caches comprise a second-level Cache, a third-level Cache, an M+1-level Cache and a memory; the counter has M+2 timing periods, corresponding respectively to: the second level translation backup buffer hits the return period, the second level Cache and the third level Cache hit the return period until the M+1 level Cache hits the return period respectively, and the return period of the memory.

And recording a resequencing Queue (Reorder Queue) number roqid transmitted by the access instruction of the secondary TLB miss in the secondary TLB, and for the instruction generating the Page Fault, setting exception to the information of the Page Fault when the secondary TLB is revisited, so as to inform the resequencing Queue to carry out exception processing.

The first level TLB multiport, the number of ports is equal to the number of simultaneously supported access components, including the components of the fetch instruction Load and the Store instruction Store. The result of the first level TLB access informs the issue queue. When a miss occurs in the first-level TLB query, the first-level TLB query is not blocked in the pipeline, and is re-executed later by a feedback re-sending mechanism of the transmission queue. The second level TLB is queried according to a scheduling policy, which is optionally selecting instructions older in program instruction sequence. If the second-level TLB hits, the result of the hit is written into the first-level TLB, and the replacement policy is a random replacement or LRU policy.

The TLB miss transmit queue supports a feedback retransmission mechanism, and in order to support the feedback retransmission mechanism, the state machine of the TLB access state in the transmit queue is as follows:

(1) EMPTY: the state is an empty item;

(2) RDY: the state is ready, is a non-empty item, and can be selected;

(3) TLBREF: accessing a translation look-aside buffer awaiting a feedback retransmission;

(4) Reproduction: waiting for a certain period and retransmitting.

State State machine switching as shown in FIG. 6, FIG. 6 is a diagram of a transmit queue feedback retransmission control State State machine transition. In detail, the memory access instruction enters an item with an EMPTY State in an emission queue, after entering, the State of the item is set as RDY, which indicates that the item is ready and is a non-EMPTY item, and can be selected, and when the operand of the memory access instruction is ready, the memory access instruction can emit and execute to carry out secondary TLB access. After the RDY-State access instruction is transmitted, the second-level TLB is not retired, the State is set as TLBREF, the second-level TLB waits for feedback, the second-level TLB hits the re-retired transmission queue, and the State is set as EMPTY after the re-retired transmission queue is retired, so that the new-entering instruction can be used.

In order to perform feedback of the first-level TLB access hit and the miss, when the transmission queue transmits the instruction, the re-sequence number roqid corresponding to the access instruction needs to be taken as a feedback signal to be transmitted back to the queue item identifier of the transmission queue, and the transmission queue number issueqid can also be used as the identifier of the queue item. The transmission queue receives feedback of the first-level TLB, compares the transmission queue number or the re-sequence number with the feedback transmission queue number or the re-sequence number, and receives a feedback result. If the feedback result is a first level TLB hit, the entry state is set to EMPTY, and the entry state is retired from the transmit queue. If the first level TLB miss, a feedback retransmission mechanism is used for processing, the state of the item is set to REPLAY, and retransmission is waited for. The memory access instruction in the REPLAY state waits until the time of the counter expires, and is set to the RDY state, and the item can be selected and retransmitted.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a translation look-aside buffer accessing apparatus according to the present application, where the apparatus is configured to implement the above-mentioned translation look-aside buffer accessing method, and includes:

a first lookup module 101, configured to obtain a virtual address to be translated, and lookup a page table corresponding to the virtual address in a first-level translation look-up buffer TLB;

A first translation module 102, configured to translate the virtual address into a physical address by using a page table in the first-level TLB if the first-level TLB hits;

a second lookup module 103, configured to, if the first-level TLB misses, lookup a page table entry mapping table in the second-level translation look-up buffer TLB according to the virtual address;

a second translation module 104, configured to translate the virtual address into a physical address using the page table entry mapping table hit in the second-level TLB if the first-level TLB is missed and the second-level TLB is hit;

the third lookup module 105 is configured to, if the first-level TLB is missed and the second-level TLB is not hit, access the lower-level storage system through the page table walker PTW, and lookup a page table corresponding to the virtual address in the lower-level storage system, thereby converting the virtual address into a physical address.

Therefore, the device not only adopts the first-level TLB to translate the virtual address for the virtual address, but also adopts the second-level TLB to translate the virtual address under the condition that the first-level TLB is not hit, so that the hit rate of the whole TLB is improved, the failure rate of the TLB is reduced, and the performance of the processor is improved by adopting the combined use of the first-level TLB and the second-level TLB.

Based on the above apparatus, further, the translation look-aside buffer accessing apparatus further includes:

The writing module is used for writing the tertiary page table item searched from the tertiary page table into the first-level TLB;

the feedback module is used for acquiring a memory access instruction which is missed by the first-level TLB if the first-level TLB is missed, and feeding the memory access instruction back to the transmission queue for retransmission;

the first setting module is used for setting the access state of the second-level TLB in the transmission queue; a feedback resending mechanism for controlling the access instruction through the state machine change of the access state of the second-level TLB;

the second setting module is used for setting a counter in the transmission queue, and timing the interval time of feedback retransmission of the access instruction through the counter; when the value of the counter reaches the timing period, the state of the second level TLB access in the issue queue is reset to the ready state.

It should be noted that, for the description of the translation look-aside buffer access device provided by the present application, reference is made to the foregoing embodiment of a translation look-aside buffer access method, and the description of the embodiment of the present application is omitted herein.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a translation look-aside buffer access device according to the present application, the device includes:

a memory 201 for storing a computer program;

a processor 202 for implementing the steps of the method as in the previous embodiment when executing a computer program.

For the description of a translation look-aside buffer access device provided by the present application, reference is made to the foregoing embodiment of a translation look-aside buffer access method, and the description of the embodiment of the present application is omitted herein.

The present application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs steps of a translation look-aside buffer access method as in the previous embodiments.

For the description of the computer readable storage medium provided by the present application, reference is made to the foregoing embodiment of a method for accessing a translation look-aside buffer, and the description of the embodiment of the present application is omitted herein.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The method, the device, the equipment and the storage medium for accessing the translation backup buffer provided by the application are described in detail. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.

Claims

1. A method of translation look-aside buffer access, comprising:

the first-stage translation look-aside buffer comprises a fully-concatenated translation look-aside buffer and a directly-concatenated translation look-aside buffer, wherein a page table stored in the directly-concatenated translation look-aside buffer consists of page table entries replaced in the fully-concatenated translation look-aside buffer;

if the primary translation look-aside buffer hits, the translating the virtual address to a physical address using the page table in the primary translation look-aside buffer includes:

when the page table of the fully-connected translation look-aside buffer is full and a new page table item needs to be added, determining a replaced old page table item in the page table of the fully-connected translation look-aside buffer according to a replacement policy, replacing the old page table item by the new page table item, writing the new page table item into the fully-connected translation look-aside buffer, and writing the replaced old page table item into the directly-connected translation look-aside buffer;

the second-level translation look-aside buffer comprises a first-level page table to an N-level page table, the virtual page number of the second-level translation look-aside buffer comprises a first-level virtual page number to an N-level virtual page number, N is a positive integer and is more than or equal to 2, and the page table item mapping relation table comprises a first-level mapping relation table to an N-level mapping relation table;

in the second-level mapping relation table to the Nth-level mapping relation table, each level of mapping relation table stores the mapping relation between a combined virtual page number formed by all virtual page numbers from one level to the level and the level page table item of the level page table;

If the N-level mapping relation table to the K+1-level mapping relation table in the second-level translation backup buffer are not hit, the numerical value of the part with the same number of virtual page numbers stored in the K-level mapping relation table in the virtual address to be translated is the same, namely the numerical value of the part with the same number of combined virtual page numbers formed by all the virtual page numbers of one level to the K level stored in the K-level mapping relation table in the virtual address to be translated is the same as the combined virtual page number, the K-level mapping relation table is hit, K is a positive integer, K is more than or equal to 1 and less than or equal to N-1, the K-level page table item of the K-level page table corresponding to the virtual address is obtained through the K-level mapping relation table, the last-level page table item is utilized to access the current-level page table from the K+1-level page table, the corresponding current-level page table item is searched until the N-level page table is accessed, and the corresponding N-level page table item is searched from the N-level page table is searched, and the physical address is obtained;

2. The translation look-aside buffer access method of claim 1 wherein writing the replaced old page table entry into the directly connected translation look-aside buffer comprises:

3. The method of claim 1, wherein the replacement policy comprises Random replacement of Random, least recently used LRU, least frequently used LFU, or first in first out FIFO.

4. The translation look-aside buffer access method of claim 1 further comprising:

5. The translation look-aside buffer access method of claim 1 further comprising:

6. The translation look-aside buffer access method of claim 5 further comprising:

7. The translation look-aside buffer access method of claim 6 further comprising:

8. The method of claim 7, wherein the lower level storage system comprises M caches and memory, M is a positive integer and M is greater than or equal to 1, the counter having m+2 timer periods;

9. A translation look-aside buffer access apparatus comprising:

a second translation module configured to translate the virtual address to a physical address using a page table entry mapping table hit in the second translation look-aside buffer if the first translation look-aside buffer misses and the second translation look-aside buffer hits;

and the third searching module is used for accessing a lower storage system through a page table walker PTW if the primary translation backup buffer is not hit and the secondary translation backup buffer is not hit, searching a page table corresponding to a virtual address in the lower storage system and converting the virtual address into a physical address.

10. A translation look-aside buffer access device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the translation look-aside buffer access method of any of claims 1 to 8 when the program is executed by the processor.

11. A computer readable storage medium storing a computer program for execution by a processor to implement the translation look-aside buffer access method of any one of claims 1 to 8.