CN116405024A - Clock compatible phase-locked loop module, clock compatible method and open wireless unit - Google Patents
Clock compatible phase-locked loop module, clock compatible method and open wireless unit Download PDFInfo
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- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
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- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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Abstract
The embodiment of the invention discloses a clock compatible phase-locked loop module, a clock compatible method and an open wireless unit. According to the embodiment of the invention, the first phase-locked loop unit and the second phase-locked loop unit in the phase-locked loop module are configured, so that the first phase-locked loop unit and the second phase-locked loop unit respectively receive the time synchronization adjustment quantity and the synchronous Ethernet clock, and the time synchronization can be carried out through the time synchronization adjustment quantity and/or the synchronous Ethernet clock. Therefore, the clock compatible phase-locked loop module of the embodiment of the invention can be simultaneously applied to a site with time synchronization capacity of only time synchronization adjustment amount, and also can be applied to a site with time synchronization capacity of both time synchronization adjustment amount and synchronous Ethernet clock, thereby realizing clock synchronization to achieve the purpose of clock compatibility and reducing equipment deployment cost and complexity.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a clock compatible phase locked loop module, a clock compatible method, and an open wireless unit.
Background
In the current communication networks, radio access networks, such as 2G/3G/4G/5G, established by telecom operators for public services are common public radio access networks. However, most of the conventional wireless access networks are closed wireless access networks, that is, the hardware devices in the access networks are proprietary hardware devices of all device merchants, the corresponding application software is also proprietary software of all device merchants, and devices among different device merchants cannot be directly replaced, so that network operators (such as China Mobile, china telecom and the like) can only select hardware products and application software of one device merchant when planning network base stations, and in order to solve the problem, domestic and foreign network operators such as China Mobile and the like propose open wireless access networks (Open Radio Access Network, abbreviated as O-RAN).
Wherein the conditions are dependent on the operator when planning the communication site. Therefore, in practical application, for the same O-RU device, only the clock synchronization requirement in one environment can be met, and the communication sites in different environments need to work with devices of different configurations, so that the configuration of the devices in different environments increases the workload of site deployment, and other serious consequences can be caused once the clock scheme configuration is wrong.
Disclosure of Invention
In view of this, the embodiment of the invention provides a clock compatible phase-locked loop module, a clock compatible method and an open wireless unit, so as to achieve clock synchronization to achieve clock compatibility, and reduce equipment deployment cost and complexity.
In a first aspect, an embodiment of the present application provides a clock compatible phase locked loop module, where the module includes a first phase locked loop unit, a second phase locked loop unit, and at least one synchronous phase locked loop unit;
the first phase-locked loop unit is configured to receive a time synchronization adjustment amount, and control the first phase-locked loop unit and each of the synchronous phase-locked loop units to perform time synchronization according to the time synchronization adjustment amount;
the second phase-locked loop unit is configured to receive a synchronous Ethernet clock and control the first phase-locked loop unit and each synchronous phase-locked loop unit to perform time synchronization according to the synchronous Ethernet clock.
Further, the first pll unit is further configured to output a second pulse signal according to the time synchronization adjustment amount, and send the second pulse signal to a control module and each pll unit, so that the control module adjusts the time synchronization adjustment amount according to the second pulse signal, and causes each pll unit to perform time synchronization based on the second pulse signal.
Further, the initial amount of time synchronization adjustment is determined by parsing a corresponding network data packet, the network data packet including a reference time and a local time.
Further, the second phase-locked loop unit is configured to determine a synchronization frequency difference between the synchronous ethernet clock and the reference clock, and send the synchronization frequency difference to the first phase-locked loop unit and the at least one synchronous phase-locked loop unit.
In a second aspect, an embodiment of the present invention provides a clock compatible method, including:
receiving time synchronization information;
responding to the time synchronization information including a synchronous Ethernet clock and a time synchronization adjustment amount, and synchronizing a clock output by a clock compatible phase-locked loop module with an upstream high-precision time synchronization protocol clock according to the synchronous frequency difference information of the synchronous Ethernet clock and the clock synchronization adjustment amount;
and responding to the time synchronization information to comprise a time synchronization adjustment amount, and enabling the output of the clock compatible phase-locked loop module to be in clock synchronization with an upstream high-precision clock protocol according to the time synchronization adjustment amount.
Further, the clock compatible phase-locked loop module comprises a first phase-locked loop unit, a second phase-locked loop unit and at least one synchronous phase-locked loop unit;
the receiving time synchronization information includes:
receiving the time synchronization adjustment amount by the first phase-locked loop unit;
and receiving the synchronous Ethernet clock through the second phase-locked loop unit.
Further, synchronizing the clock output by the clock compatible phase-locked loop module with the upstream high-precision time synchronization protocol clock according to the synchronization frequency difference information and the clock synchronization adjustment amount of the synchronous Ethernet clock comprises:
determining a synchronization frequency difference between the synchronous Ethernet clock and a reference clock through the second phase-locked loop unit;
transmitting the synchronization frequency difference to the first phase-locked loop unit and at least one of the synchronization phase-locked loop units;
and the first phase-locked loop unit and at least one synchronous phase-locked loop unit perform time synchronization according to the synchronous frequency difference.
Further, synchronizing the clock output by the clock compatible phase-locked loop module with the upstream high-precision time synchronization protocol clock according to the time synchronization adjustment amount includes:
the first phase-locked loop unit generates a second pulse signal according to the time synchronization adjustment quantity;
and sending the second pulse signals to a corresponding control module and each synchronous phase-locked loop unit, so that the control module adjusts the time synchronization adjustment amount according to the second pulse signals, and each synchronous phase-locked loop unit performs time synchronization based on the second pulse signals.
In a third aspect, embodiments of the present invention provide an open wireless unit, the unit comprising:
the control module is configured to analyze the received network data packet and acquire time synchronization information, wherein the time synchronization information comprises a synchronous Ethernet clock and/or a time synchronization adjustment quantity; and
the clock compatible phase locked loop module of the first aspect.
Further, the open wireless unit further includes:
the photoelectric conversion module is configured to convert a signal input into the open wireless unit from an optical signal into an electric signal, generate and send the network data packet to the control module;
a clock generation module configured to provide a reference clock to the clock compatible phase locked loop module;
a power conversion module configured to power each module in the open wireless unit;
and the signal receiving and transmitting module is configured to perform down-conversion demodulation or up-conversion debugging on the received or transmitted signals.
According to the embodiment of the invention, the first phase-locked loop unit and the second phase-locked loop unit in the phase-locked loop module are configured, so that the first phase-locked loop unit and the second phase-locked loop unit respectively receive the time synchronization adjustment quantity and the synchronous Ethernet clock, and the time synchronization can be carried out through the time synchronization adjustment quantity and/or the synchronous Ethernet clock. Therefore, the clock compatible phase-locked loop module of the embodiment of the invention can be simultaneously applied to a site with time synchronization capacity of only time synchronization adjustment amount, and also can be applied to a site with time synchronization capacity of both time synchronization adjustment amount and synchronous Ethernet clock, thereby realizing clock synchronization to achieve the purpose of clock compatibility and reducing equipment deployment cost and complexity.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic diagram of a clock-compatible open wireless unit according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a clock compatible application principle of an embodiment of the present application;
FIG. 3 is a schematic diagram of a clock compatible application principle of a time synchronization process according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a clock compatible phase locked loop module according to an embodiment of the present application;
fig. 5 is a schematic diagram of a clock compatible phase locked loop module of a time synchronization process according to an embodiment of the present application;
fig. 6 is a flow chart of a clock compatible method of an embodiment of the present application.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, the words "comprise," "comprising," and the like in the description are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
Meanwhile, it should be understood that in the following description, "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical connection or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
An O-RU (Open Radio Unit) is a key device for communication based on an O-RAN (Open Radio Access Network ) architecture, and is directly connected to a user equipment through a communication signal. The O-RU and the O-DU (Open Distributed unit, open distribution unit) generally communicate through an optical fiber, and a time synchronization manner between the O-RU and the O-DU adopts a mainstream ptp+synce (i.e., a base station site has a clock synchronization function and an ethernet synchronization function) or PTP only (i.e., the base station site only has a clock synchronization function), and specifically adopts PTP only or ptp+synce, depending on conditions in planning the base station site by an operator. In practice, for the same type of O-RU device, it is possible to use both site A and site B, where site A has only PTP and site B has both PTP and SyncE. Thus, operators may require that these O-RU devices have both PTP only time synchronization capability and ptp+synce synchronization capability. However, ptponly and ptp+synce are completely different clock management schemes, in order to meet the requirement of operators on the O-RU device having both PTP only and ptp+synce time synchronization capability, this requires that the O-RU device manages two different clock schemes, one set of clock scheme is adapted to the application scenario of PTP only, and the other set of clock scheme is used to adapt to the scheme of ptp+synce, which leads to the problem of clock scheme switching.
Fig. 1 is a schematic diagram of a clock-compatible open wireless unit according to an embodiment of the present invention.
As shown in fig. 1, the clock-compatible open wireless unit according to the embodiment of the present invention includes a photoelectric conversion module 100, a control module 110, a clock-compatible phase-locked loop module 120, a signal transceiver module 130, a clock generation module 140, and a power conversion module 150. The photoelectric conversion module 100 is configured to convert a signal input to an open wireless unit from an optical signal to an electrical signal, generate the electrical signal, and send the network data packet to the control module 110. The control module 110 is configured to parse the received data packet to obtain time synchronization information including a synchronization ethernet clock and/or a time synchronization adjustment.
Further, when the corresponding base station only has the clock synchronization function (that is, PTP only), the control module 110 analyzes the acquired network data packet to acquire the clock synchronization data packet. Further, the control module 110 compares the reference time contained in the parsed clock synchronization data packet with the local time, and calculates the deviation between the current local time and the reference time. The control module 110 processes the time deviation of more than second directly in the process of time stamping, converts the time deviation of less than second into a frequency difference or a phase difference (i.e. the time synchronization adjustment amount) and sends the frequency difference or the phase difference to the clock compatible phase-locked loop module 120. The clock compatible pll module 120 performs clock synchronization according to the frequency difference and/or the phase difference (i.e., the real time synchronization adjustment amount) output from the control module 110.
When the corresponding base station has a clock synchronization function (PTP only) and an ethernet synchronization function (SyncE), the control module 110 analyzes the acquired network data packet, and may obtain a clock synchronization data packet and a synchronization ethernet data packet. The control module 110 compares the reference time and the local time contained in the parsed clock synchronization data packet, calculates the deviation between the current local time and the reference time, directly processes the time deviation above second in the processing process of the time stamp, converts the time deviation below second into a frequency difference or a phase difference (i.e. the time synchronization adjustment amount), and sends the time synchronization adjustment amount to the clock compatible phase-locked loop module 120. Meanwhile, the control module 110 parses the synchronous ethernet packet to obtain a synchronous ethernet clock, and sends the synchronous ethernet clock to the clock compatible phase-locked loop module 120.
The clock compatible pll module 120 performs clock synchronization according to the frequency difference and/or the phase difference (i.e., the real time synchronization adjustment amount) output from the control module 110. The synchronous ethernet clock serves as an input reference clock for the clock compatible phase locked loop module 120. At the same time, the clock compatible phase locked loop module 120 receives the reference clock from the clock generation module 140. The clock compatible pll module 120 reads the frequency difference between the reference clock and the reference clock, and processes the frequency difference read many times to obtain synchronization frequency difference information, and the clock compatible pll 120 can accelerate the time synchronization process according to the synchronization frequency difference information.
Further, the signal transceiver module 130 in the clock-compatible open wireless unit is configured to down-convert demodulation or up-convert debugging of the received or transmitted signal. And the power conversion module is configured to supply power to each module in the open wireless unit.
Fig. 2 is a schematic diagram of a clock compatible application principle of an embodiment of the present application. When the corresponding base station has a clock synchronization function (PTP only) and an ethernet synchronization function (SyncE), as shown in fig. 2, the clock compatible application principle of the embodiment of the present application is as follows:
specifically, the control module 210 analyzes the acquired network data packet, separates the time synchronization data packet and the synchronization ethernet data packet, compares the reference time contained in the time synchronization data packet with the local time, calculates the deviation between the current local time and the reference time, processes the time deviation above second in the timestamp processing process directly, and converts the time deviation below second into a frequency difference or a phase difference as an initial time synchronization adjustment amount, and sends the frequency difference or the phase difference to the clock compatible phase-locked loop module 220. Meanwhile, the control module 210 parses the synchronous ethernet clock from the synchronous ethernet packet and sends the synchronous ethernet clock to the clock compatible phase locked loop module 220.
The clock compatible pll module 220 performs clock synchronization according to the frequency difference and/or the phase difference (i.e., the amount of time synchronization adjustment) output from the control module 210. Specifically, the clock compatible pll module 220 receives the initial time synchronization adjustment amount and the reference clock sent by the clock generating module 230, and performs clock synchronization on the pll unit inside the clock Zhong Jianrong pll module 220. In this embodiment, the received synchronous ethernet clock is used as a reference clock for the clock compatible phase locked loop 220. The reference clock and the reference clock may have a frequency difference, and in this embodiment, the frequency difference value is read for multiple times and is processed to obtain synchronization frequency difference information, and clock synchronization is performed on the pll unit inside the pll module 220 by using the synchronization frequency difference information.
Further optionally, in this embodiment, the second pulse signal output by the clock compatible phase-locked loop module 220 is sent to the control module 210 as feedback information, and the control module 210 adjusts the time synchronization adjustment amount based on the received feedback information and sends the time synchronization adjustment amount to the clock compatible phase-locked loop module 220 for clock synchronization until the adjusted time synchronization adjustment amount converges, and the clock compatible phase-locked loop module 220 also achieves clock synchronization. Furthermore, the embodiment also uses the synchronous frequency difference information to execute clock synchronous operation so as to accelerate the convergence of time synchronous adjustment quantity and improve the clock synchronous efficiency.
Fig. 3 is a schematic diagram of a clock compatible application principle of a time synchronization process according to an embodiment of the present application.
Alternatively, when the corresponding base station only has a clock synchronization function (PTP only), the clock compatible application principle of the clock synchronization process is shown in fig. 3.
As shown in fig. 3, the control module 310 analyzes the acquired network data packet, separates the time synchronization data packet from the network data packet, calculates the deviation between the current local time and the reference time in the time synchronization data packet, directly processes the time deviation above second in the time stamp processing process, converts the time deviation below second into a frequency difference or a phase difference as an initial time synchronization adjustment amount, and sends the frequency difference or the phase difference to the clock compatible phase-locked loop module 320.
The clock compatible phase-locked loop module 320 receives the initial time synchronization adjustment amount, adjusts the frequency of the internal phase-locked loop unit, outputs a second pulse signal as a feedback signal to the control module 310, adjusts the time synchronization adjustment amount based on the received feedback information, and sends the time synchronization adjustment amount to the clock compatible phase-locked loop module 320 for clock synchronization until the adjusted time synchronization adjustment amount converges, and the clock compatible phase-locked loop module 320 also realizes clock synchronization.
Therefore, the clock compatible phase-locked loop application principle of the embodiment of the invention can be applied to an environment with time synchronization capacity of only time synchronization adjustment amount, and also can be applied to an environment with time synchronization capacity of both time synchronization adjustment amount and synchronous Ethernet clock, so that the purpose of clock compatibility is achieved by clock synchronization, the situation that communication stations under different environments need equipment with different configurations is avoided, and the equipment deployment cost and complexity are reduced.
Fig. 4 is a schematic diagram of a clock compatible pll module according to an embodiment of the invention.
As shown in fig. 4, the clock compatible phase locked loop module 400 of the embodiment of the present invention includes a first phase locked loop module 410, a second phase locked loop module 440, and at least one synchronous phase locked loop module 420. The first pll unit 410 is configured to receive a time synchronization adjustment amount, and control the first pll unit and each of the pll units to perform time synchronization according to the time synchronization adjustment amount. The second phase locked loop unit 440 is configured to receive the synchronous ethernet clock and to take the synchronous ethernet clock as a reference clock. The first pll unit 410 is connected to the control module 450, each pll unit 420, etc. to transmit a second pulse signal output based on the time synchronization adjustment amount to the control module 450 and each pll unit (e.g., pll units 420, 430, etc.). Further, the second pll unit 440 is connected to the first pll unit 410, each pll unit 420, etc. to transmit the synchronization frequency difference corresponding to the synchronous ethernet clock to the first pll unit 410, each pll unit, etc.
In an alternative implementation, the time synchronization adjustment and the synchronized ethernet clock are determined based on the received network data packets by the control module 450. Specifically, the control module 450 parses the acquired network data packet to obtain a clock synchronization data packet and/or a synchronization ethernet data packet. The control module 450 compares the reference time and the local time contained in the parsed clock synchronization data packet, calculates the deviation between the current local time and the reference time, directly processes the time deviation above second in the timestamp processing process, converts the time deviation below second into a frequency difference or a phase difference (i.e. an initial time synchronization adjustment amount), and sends the time synchronization adjustment amount to the clock compatible phase-locked loop module 400. Meanwhile, the control module 450 parses the synchronous ethernet packet to obtain a synchronous ethernet clock, and sends the synchronous ethernet clock to the clock compatible phase-locked loop module 400.
Optionally, the first pll unit 410 is configured in a voltage controlled oscillator mode and has a feedback function.
Further, when the corresponding base station has a clock synchronization function (ptponly) and an ethernet synchronization function (SyncE), the first phase-locked loop unit 410 is configured to output a second pulse signal according to the time synchronization adjustment amount, and send the second pulse signal to the control module 450 and the at least one phase-locked loop unit 420, so that the control module 450 adjusts the time synchronization adjustment amount according to the second pulse signal, and makes each phase-locked loop unit 420 perform time synchronization based on the second pulse signal until the time synchronization adjustment amount converges, that is, clock synchronization is achieved. Meanwhile, the clock compatible pll module 400 receives the reference clock sent from the clock generating module 460, the second pll unit 440 is further configured to determine a frequency difference between the received reference clock and the reference clock, process the frequency difference read multiple times and perform data processing to obtain synchronization frequency difference information, send the synchronization frequency difference information to the first pll unit 410 and each pll unit (e.g. pll units 420, 430, etc.) to control the first pll unit 410 and at least one pll unit 420 to perform frequency synchronization, thereby accelerating convergence of time synchronization adjustment, and improving clock synchronization efficiency, that is, achieving clock synchronization between the O-RU and the O-DU.
Fig. 5 is a schematic diagram of a clock compatible phase locked loop module of a time synchronization process according to an embodiment of the present application. Those skilled in the art will appreciate that the clock compatible pll module hardware and configuration is not changed during this time synchronization, and only the transmission data is changed (i.e., the dashed line in fig. 5 indicates the case where there is a wired connection but no data transmission).
When the corresponding base station only has the clock synchronization function (that is, PTP only), the control module 550 does not synchronize the ethernet clock output, and the second pll unit 540 does not participate in the time synchronization process when it is in the idle state.
Specifically, the control module 550 only sends the time synchronization adjustment to the clock compatible phase locked loop module 500. It should be appreciated that the method for determining the initial time synchronization adjustment is similar to that described above, and will not be described in detail herein. The first pll unit 510 is configured to output a second pulse signal according to the time synchronization adjustment amount, and send the second pulse signal to the control module and the at least one pll unit 520, so that the control module 550 adjusts the time synchronization adjustment amount according to the second pulse signal, and each pll unit 520 performs time synchronization based on the second pulse signal until the time synchronization adjustment amount converges, that is, clock synchronization between the O-RU and the O-DU is achieved.
Therefore, the clock compatible phase-locked loop module of the embodiment of the invention realizes a corresponding clock synchronization scheme by respectively configuring corresponding phase-locked loop units for the PTP time synchronization function and the SyncE clock Ethernet clock synchronization function, so that the clock compatible phase-locked loop module can be applied to an environment with time synchronization capacity of only time synchronization adjustment quantity and an environment with time synchronization capacity of both time synchronization adjustment quantity and synchronous Ethernet clock, realizes clock synchronization, achieves the purpose of clock compatibility, and reduces equipment deployment cost and complexity.
Fig. 6 is a flow chart of a clock compatible method of an embodiment of the invention. As shown in fig. 4, the clock compatible method of the embodiment of the present invention includes:
step S610 receives time synchronization information.
Specifically, the time synchronization information in the embodiment of the present invention includes a time synchronization adjustment amount (PTP adjustment amount, precision Time Protocol, high precision time synchronization protocol) and a synchronous ethernet clock (Synchronous Ethernet clock). Alternatively, taking the clock compatible phase-locked loop module shown in fig. 6 as an example, the embodiment may receive the time synchronization adjustment amount through a first phase-locked loop unit, and receive the synchronous ethernet clock through a second phase-locked loop unit.
Step S620, in response to the time synchronization information including the synchronization ethernet clock and the time synchronization adjustment, synchronizes the clock output by the clock compatible phase-locked loop module with the upstream high-precision time synchronization protocol clock according to the synchronization frequency difference information of the synchronization ethernet clock and the clock synchronization adjustment.
Specifically, when the time synchronization information includes a synchronization ethernet clock and a time synchronization adjustment amount, that is, when the current base station has a clock synchronization function (PTP only) and an ethernet synchronization function (SyncE), referring to fig. 2 and 4, the clock generation module sends a reference clock to the clock compatible phase-locked loop module, and a second phase-locked loop unit inside the clock compatible phase-locked loop module determines synchronization frequency difference information of the synchronization ethernet clock and the reference clock, and sends the synchronization frequency difference information to the first phase-locked loop unit and at least one of the synchronization phase-locked loop units, so that the first phase-locked loop unit and the at least one of the synchronization phase-locked loop units perform time synchronization according to the synchronization frequency difference. The first phase-locked loop unit receives an initial time synchronization adjustment quantity, generates a second pulse signal according to the time synchronization adjustment quantity, and sends the second pulse signal to a corresponding control module and each synchronous phase-locked loop unit, so that the control module adjusts the time synchronization adjustment quantity according to the second pulse signal, and enables each synchronous phase-locked loop unit to perform time synchronization based on the second pulse signal until the time synchronization adjustment quantity converges, namely clock synchronization is achieved. Therefore, the embodiment can accelerate the time synchronization adjustment quantity convergence through the synchronous Ethernet clock, thereby improving the clock synchronization efficiency, realizing the clock synchronization between the output of the clock compatible phase-locked loop module and the upstream high-precision clock protocol, namely realizing the clock synchronization between the O-RU and the O-DU.
Step S630, in response to the time synchronization information including a time synchronization adjustment, synchronizes the clock compatible phase locked loop module output with the upstream high precision clock protocol clock according to the time synchronization adjustment.
Specifically, in the case that the time synchronization information only includes the time synchronization adjustment amount, that is, the current base station only has a clock synchronization function (PTP only), referring to fig. 3 and 5, the second phase locked loop unit does not play any role in this step because there is no synchronous ethernet clock input. The first phase-locked loop unit receives an initial time synchronization adjustment quantity, generates a second pulse signal according to the time synchronization adjustment quantity, and sends the second pulse signal to a corresponding control module and each synchronous phase-locked loop unit, so that the control module adjusts the time synchronization adjustment quantity according to the second pulse signal, and each synchronous phase-locked loop unit performs time synchronization based on the second pulse signal until the time synchronization adjustment quantity converges, and clock synchronization between the output of the clock compatible phase-locked loop module and an upstream high-precision clock protocol is achieved, namely clock synchronization between the O-RU and the O-DU is achieved.
It should be understood that step S620 and step S630 are not performed sequentially, and that the above two steps are performed in two different environments.
By the clock compatible method, the clock can be simultaneously applied to the sites with the time synchronization capacity of only the time synchronization regulating quantity, and the sites with the time synchronization capacity of both the time synchronization regulating quantity and the synchronous Ethernet clock, so that the clock synchronization can achieve the purpose of clock compatibility, and the equipment deployment cost and complexity are reduced.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A clock compatible phase locked loop module, the module comprising a first phase locked loop unit, a second phase locked loop unit and at least one synchronous phase locked loop unit;
the first phase-locked loop unit is configured to receive a time synchronization adjustment amount, and control the first phase-locked loop unit and each of the synchronous phase-locked loop units to perform time synchronization according to the time synchronization adjustment amount;
the second phase-locked loop unit is configured to receive a synchronous Ethernet clock and control the first phase-locked loop unit and each synchronous phase-locked loop unit to perform time synchronization according to the synchronous Ethernet clock.
2. The clock-compatible phase-locked loop module of claim 1, wherein the first phase-locked loop unit is further configured to output a second pulse signal according to the time synchronization adjustment amount and send the second pulse signal to a control module and each of the phase-locked loop units, such that the control module adjusts the time synchronization adjustment amount according to the second pulse signal and such that each of the phase-locked loop units performs time synchronization based on the second pulse signal.
3. The clock-compatible phase-locked loop module of claim 1, wherein the initial amount of time synchronization adjustment is determined by parsing a corresponding network data packet, the network data packet comprising a reference time and a local time.
4. The clock-compatible phase-locked loop module of claim 1, wherein the second phase-locked loop unit is configured to determine a synchronization frequency difference of the synchronous ethernet clock and a reference clock, and to send the synchronization frequency difference to the first phase-locked loop unit and the at least one synchronous phase-locked loop unit.
5. A clock compatible method, the method comprising:
receiving time synchronization information;
responding to the time synchronization information including a synchronous Ethernet clock and a time synchronization adjustment amount, and synchronizing a clock output by a clock compatible phase-locked loop module with an upstream high-precision time synchronization protocol clock according to the synchronous frequency difference information of the synchronous Ethernet clock and the clock synchronization adjustment amount;
and responding to the time synchronization information to comprise a time synchronization adjustment amount, and enabling the output of the clock compatible phase-locked loop module to be in clock synchronization with an upstream high-precision clock protocol according to the time synchronization adjustment amount.
6. The method of claim 5, wherein the clock compatible phase locked loop module comprises a first phase locked loop unit, a second phase locked loop unit, and at least one synchronous phase locked loop unit;
the receiving time synchronization information includes:
receiving the time synchronization adjustment amount by the first phase-locked loop unit;
and receiving the synchronous Ethernet clock through the second phase-locked loop unit.
7. The method of claim 6, wherein synchronizing the clock output by the clock compatible phase locked loop module with the upstream high precision time synchronization protocol clock based on the synchronization frequency difference information and the clock synchronization adjustment amount of the synchronized ethernet clock comprises:
determining a synchronization frequency difference between the synchronous Ethernet clock and a reference clock through the second phase-locked loop unit;
transmitting the synchronization frequency difference to the first phase-locked loop unit and at least one of the synchronization phase-locked loop units;
and the first phase-locked loop unit and at least one synchronous phase-locked loop unit perform time synchronization according to the synchronous frequency difference.
8. The method of claim 6, wherein synchronizing the clock output by the clock-compatible phase-locked loop module with the upstream high precision time synchronization protocol clock based on the time synchronization adjustment comprises:
the first phase-locked loop unit generates a second pulse signal according to the time synchronization adjustment quantity;
and sending the second pulse signals to a corresponding control module and each synchronous phase-locked loop unit, so that the control module adjusts the time synchronization adjustment amount according to the second pulse signals, and each synchronous phase-locked loop unit performs time synchronization based on the second pulse signals.
9. An open wireless unit, the unit comprising:
the control module is configured to analyze the received network data packet and acquire time synchronization information, wherein the time synchronization information comprises a synchronous Ethernet clock and/or a time synchronization adjustment quantity; and
a clock compatible phase locked loop module as claimed in any one of claims 1 to 4.
10. The open wireless unit of claim 9, wherein the open wireless unit further comprises:
the photoelectric conversion module is configured to convert a signal input into the open wireless unit from an optical signal into an electric signal, generate and send the network data packet to the control module;
a clock generation module configured to provide a reference clock to the clock compatible phase locked loop module;
a power conversion module configured to power each module in the open wireless unit;
and the signal receiving and transmitting module is configured to perform down-conversion demodulation or up-conversion debugging on the received or transmitted signals.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN119254376A (en) * | 2024-12-06 | 2025-01-03 | 杭州初灵信息技术股份有限公司 | A time synchronization device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN119254376A (en) * | 2024-12-06 | 2025-01-03 | 杭州初灵信息技术股份有限公司 | A time synchronization device |
| CN119254376B (en) * | 2024-12-06 | 2025-03-18 | 杭州初灵信息技术股份有限公司 | Time synchronization device |
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