CN116488596B

CN116488596B - LVDS receiving circuit and chip with wide input common mode range

Info

Publication number: CN116488596B
Application number: CN202310060754.5A
Authority: CN
Inventors: 黄泽祥; 张开伟
Original assignee: Mouxin Technology Shanghai Co ltd
Current assignee: Mouxin Technology Shanghai Co ltd
Priority date: 2023-01-19
Filing date: 2023-01-19
Publication date: 2025-07-04
Anticipated expiration: 2043-01-19
Also published as: CN116488596A

Abstract

The present invention discloses a low voltage differential signal LVDS receiving circuit and chip with a wide input common mode range, and relates to the technical field of data processing circuits. The input stage of the LVDS receiving circuit includes a first-stage input terminal and a second-stage input terminal, two groups of PMOS tube input differential pairs, a level shift module, and a PMOS transistor PM5 used as a switch, a reference voltage module and a bias circuit module; the bias circuit module is used to provide a bias current I0 and its control configuration, and is used to reduce the output bias current I0 when the input common mode level is at an intermediate level or near the reference voltage to compensate for the increase in the circuit transconductance Gm when the two groups of PMOS tube input differential pairs work simultaneously. The present invention can not only achieve an input common mode range close to rail-to-rail at a low power supply voltage, but also the circuit transconductance Gm changes less with the common mode, which significantly reduces the speed, gain, hysteresis, etc. of the circuit affected by the input common mode change.

Description

LVDS receiving circuit with wide input common mode range and chip

Technical Field

The present invention relates to the field of data processing circuits, and in particular, to an LVDS receiving circuit and chip with a wide input common mode range.

Background

Low-Voltage DIFFERENTIAL SIGNALING (LVDS) transmission technology has been proposed in the 1990 s, which uses differential small-swing signals to transmit data, so that the Low-Voltage differential signal transmission technology can achieve higher transmission speed, lower electromagnetic radiation interference, better noise immunity and greatly reduced power consumption, and is widely used in various communication systems.

The LDVS data transmission system includes an LDVS transmitting circuit and an LDVS receiving circuit, and according to the standard of the current LVDS protocol, the input common mode range of the LVDS receiving circuit needs to be wide enough (must be significantly larger than the common mode range of the LDVS transmitting circuit) for robust operation, and especially when the power supply voltage of the receiving end is low, it is desirable that the input common mode range of the LVDS receiving circuit can reach a voltage range close to a rail-to-rail voltage range, taking into consideration the ground voltage difference between the transmitting end and the receiving end, direct coupling interference, transmitting end interference, and the like. By way of example, fig. 1 illustrates a prior art LVDS receiver circuit, where PMOS transistors PM1 and PM2 form a differential input pair, and according to the positive and negative magnitudes of the differential input (VP-VN) which represents a positive signal, VN represents a negative signal, the differential input signal is equal to VP-VN), the magnitude of the constant source current IBIAS flowing to the drains of PM1 and PM2 is adjusted, and NMOS transistors NM1, NM2, NM3, NM4 form a diode load with positive feedback in combination to achieve signal amplification and required hysteresis, and further signal amplification and differential to single-ended output VOUT are achieved through the output stage formed by NM5, NM6 and PM3, PM 4. However, this structure cannot realize a wide input common mode range, and assuming that the absolute value of the gate-source voltages of PM1 and PM2 is |v _GS |, and the overdrive voltage required for the constant source current IBIAS is V _DSAT,IBIAS, the input common mode level V _CM,IN = (vp+vn)/2 should be smaller than VDD-V _DSAT,_IBIAS-|V_GS |, and it is difficult to satisfy the standard range required by the LVDS protocol when the power supply voltage VDD is low.

In order to achieve an input common mode range close to a rail-to-rail range, a typical input stage of an LVDS receiving circuit generally uses a combination mode of a PMOS (Positive CHANNEL METAL Oxide Semiconductor) tube differential pair and an NMOS (NEGATIVE CHANNEL METAL Oxide Semiconductor) tube differential pair at present, wherein the PMOS tube differential pair works when an input common mode level is low, the NMOS tube differential pair works when the input common mode level is high, and the PMOS tube differential pair and the NMOS tube differential pair work simultaneously when the input common mode level is at an intermediate level. Referring to fig. 2, a conventional LVDS receiver circuit for implementing a common-mode range of a rail-to-rail input is illustrated, and the scheme uses PMOS differential input pairs PM1 and PM2 and NMOS differential input pairs NM1 and NM2 in a mixed manner to form a folded operational amplifier, so as to expand the input common-mode range. The PMOS differential input pair PM1, PM2 operates when the input common mode level is low, the NMOS differential input pair NM1, NM2 operates when the input common mode level is high, and the PMOS differential input pair PM1, PM2 and the NMOS differential input pair NM1, NM2 operate simultaneously when the input common mode level is at an intermediate level. However, this working mode may cause significant changes of the total transconductance Gm, bias current, etc. of the circuit along with the input common mode, resulting in larger circuit delay and smaller gain in some cases, and because the gain of the input stage varies greatly along with the process, temperature, and supply voltage, it is difficult to implement stable hysteresis voltage.

Accordingly, the prior art also provides solutions for extending the input common mode range by adding level shifting, such as the input stage for an LVDS receiver circuit disclosed in chinese patent application CN201880065454.3, comprising at least one supply voltage connection and a first stage input and a second stage input for applying differential input signal pairs, the input stage further comprising a first differential stage and a second differential stage, wherein the stage inputs are directly connected to the inputs of the first differential stage respectively and indirectly connected to the inputs of the second differential stage respectively by means of level shifting circuits, the input stage further comprising two stage outputs having a connection made up of each of the outputs of the first differential stage and the second differential stage respectively, the first differential stage and the second differential stage being connected to the supply voltage connection respectively by means of a transistor of a third differential stage, wherein the control inputs of one of these transistors are connected to a measurement path which connects the stage inputs to each other and the control inputs of the other transistors are connected to the input for providing a reference voltage. The core of the above scheme is that the extension of the common-mode input range is achieved by using two sets of input differential pairs and a level shift circuit for reducing the input common-mode level, while a third set of differential pairs is provided, the first and second differential pairs are connected to the power supply voltage connection via the transistors of the third differential pair, respectively, the control input of one transistor of the third differential pair is connected to the reference voltage, the control input of the other transistor of the third differential pair is connected to the measurement path (in particular, the measurement path (which may be a series circuit consisting of two identical resistors, see the measurement path 20 consisting of resistors 32, 20 in fig. 3) connects the two stage inputs to each other, the reference voltage is V _REF, the input VP (positive signal) and VN (negative signal) are connected to each other via the two identical resistors of the aforementioned measurement path, the potential at the junction of the two resistors is the input common-mode level V _CM,IN = (vp+vn)/2, the other transistor of the third differential pair is connected to R1 = R2, by comparing the reference voltage V _REF with the input common mode level V _CM,IN to adjust the constant source current to the drains of the two transistors in the third differential pair, the input stage has the advantages of maximizing the allowable common mode range, having a fixed bias current (i.e. not changing with the input common mode), easily integrating hysteresis function, eliminating the correlation between current consumption and common mode, reducing hysteresis, correlation of circuit parameters such as delay time with common mode. However, the above solution still has the disadvantage that the total transconductance Gm of the circuit varies greatly with the common mode (especially when the two transistors of the first differential pair and the two transistors of the second differential pair operate simultaneously, the total transconductance Gm of the circuit increases relatively significantly), resulting in significant variations in speed, gain, hysteresis, etc. of the circuit with the common mode.

In summary, how to provide an LVDS receiving circuit capable of realizing an input common mode range close to rail-to-rail at a low power supply voltage and having a small circuit transconductance Gm with a small common mode variation is a technical problem to be solved currently.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides an LVDS receiving circuit and a chip with wide input common mode range. The LVDS receiving circuit with the wide input common mode range provided by the invention not only can realize the input common mode range close to the rail-to-rail under the low power supply voltage, but also has smaller circuit transconductance Gm along with the common mode change, so that the speed, gain, hysteresis and the like of the circuit along with the common mode change are smaller, and the influence of the input common mode change on the speed, gain, hysteresis and the like of the circuit is obviously reduced.

In order to achieve the above object, the present invention provides the following technical solutions:

The low voltage differential signaling LVDS receiving circuit with a wide input common mode range comprises an input stage, wherein the input stage comprises a first stage input end, a second stage input end, a first group of PMOS (P-channel metal oxide semiconductor) transistor input differential pairs, a second group of PMOS transistor input differential pairs and a level shift module, the first stage input end and the second stage input end are used for applying differential input signal pairs VP and VN, the differential input signal pairs VP and VN are respectively and directly connected with the grid electrodes of two transistors of the second group of PMOS transistor input differential pairs and used for controlling leakage currents of the two transistors, and the differential input signal pairs VP and VN are also indirectly connected with the grid electrodes of the two transistors of the first group of PMOS transistor input differential pairs through the level shift module and used for controlling the leakage currents of the two transistors;

The input stage further comprises a PMOS transistor PM5 serving as a switch, a reference voltage module, and a bias circuit module;

The drain electrode of the transistor PM5 is connected with the source electrodes of the two transistors of the first group of PMOS transistor input differential pairs to a first node, the source electrodes of the transistor PM5 and the source electrodes of the two transistors of the second group of PMOS transistor input differential pairs are connected to a second node, and the grid electrode of the transistor PM5 is connected with a reference voltage module;

The reference voltage module provides a reference voltage V _REF to the transistor PM5, V _REF as a gate voltage of the transistor PM 5;

The bias circuit module is used for providing bias current I0 of an input stage and performing control configuration of the bias current, wherein the bias circuit module is configured to reduce the output bias current I0 when the input common mode level is judged to be at the middle level or the difference value between the input common mode level and the reference voltage V _REF is judged to be within a preset range, so that the bias current I0 flowing to the first node and the second node is reduced.

Further, the bias current I0 output by the bias circuit module is related to an input common mode level V _CM,IN, where the input common mode level V _CM,IN = (vp+vn)/2, VP represents a positive side signal, and VN represents a negative side signal;

The relation between the bias current I0 and the input common mode level V _CM,IN is expressed as I0=I _Fixing+f(V_CM,IN), wherein I _Fixing is irrelevant to the input common mode level V _CM,IN, and f (V _CM,IN) represents a function related to the input common mode level V _CM,IN;

The weight ratio of the input common mode level V _CM,IN to the bias current I0 is reduced by configuring f (V _CM,IN) in the relation expression, wherein f (V _CM,IN) =0 is set when the difference value between the input common mode level V _CM,IN and the power supply voltage or the ground voltage is in a preset range when the f (V _CM,IN) function is configured, and f (V _CM,IN) is set to be a preset negative value when the difference value between the power supply voltage and the reference voltage V _REF is in the preset range.

Further, the bias circuit module comprises a comparison unit and a bias current I0 control unit;

The comparison unit is configured to compare the input common mode level with a reference voltage V _REF, a power supply voltage and a ground voltage, and send the comparison result to the bias current I0 control unit;

The bias current I0 control unit is configured to obtain the comparison result, determine that the input common mode level is close to the ground voltage when the difference value between the input common mode level and the ground voltage is within a preset range, the transistor PM5 is in an off state, the bias current I0 is all flowed to the second node, the two transistors PM3 and PM4 of the second group of PMOS transistor input differential pairs are operated at the same time, and

When the difference between the input common mode level and the power supply voltage is within the preset range, the input common mode level is judged to be close to the power supply voltage, the two transistors of the input differential pair of the second group of PMOS tubes are turned off, the bias current I0 mainly flows to the source electrode of the transistor PM5, at the moment, the two transistors PM1 and PM2 of the input differential pair of the first group of PMOS tubes work, the direct current level of the differential input signal pairs VP and VN is reduced through the level shifting module, and

When the difference between the input common mode level and the reference voltage V _REF is within the preset range, the common mode level is judged to be near the reference voltage V _REF, the bias current I0 flows to the first node and the second node at the same time, the two transistors of the first group of PMOS tube input differential pairs and the two transistors of the second group of PMOS tube input differential pairs work at the same time, and the output bias current I0 is regulated down, so that the bias current I0 flowing to the two groups of PMOS tube input differential pairs is reduced.

Further, the bias circuit module includes PMOS transistors PM0, PM8, PM9, PM10, and PM11, NMOS transistors NM1, NM2, and NM3, and two resistors R3 and R4 having equal resistance values;

The drain electrode of the transistor PM0 is connected with the source electrodes of the transistors PM3 and PM4 of the second group of PMOS transistor input differential pairs to provide bias current I0 for the input stage, the source electrode of the transistor PM0 is connected with the power supply voltage VDD, the gate electrode of the transistor PM0 is connected with the gate electrode and the drain electrode of the transistor PM8, and simultaneously connected with the drain electrode of the transistor NM1 and simultaneously connected with the drain electrode of the transistor PM9, the transistors PM0 and PM8 form a current mirror, and the source electrodes of the transistors PM8 and PM9 are connected with the power supply voltage VDD;

The gate of the transistor NM1 is connected with a bias voltage V _BIAS, and the source electrode is grounded with a voltage VSS to form a current source;

The grid electrode of the transistor PM9 is connected with the grid electrode and the drain electrode of the transistor PM10, the transistors PM9 and PM10 form a current mirror, the source electrode of the transistor PM10 is connected with the power supply voltage VDD, the drain electrode of the transistor PM10 is also connected with the source electrode of the transistor PM11, the drain electrode of the transistor PM11 is connected with the drain electrode of the transistor NM2, the source electrode of the transistor NM2 is simultaneously connected with the drain electrode and the grid electrode of the transistor NM3, the source electrode of the transistor NM3 is grounded to the ground voltage VSS, the grid electrodes of the transistor PM11 and the transistor NM2 are both connected with the junction of the resistors R3 and R4, the other end of the resistor R3 is connected with the input positive end signal VP of the receiving circuit, the other end of the resistor R4 is connected with the input negative end signal VN of the receiving circuit, and the potential at the junction of the resistors R3 and R4 is the input common mode level V _CM,IN.

Further, let the ratio of the aspect ratio of the transistor PM0 to the transistor PM8 be m, and the ratio of the aspect ratio of the transistor PM9 to the transistor PM10 be 1, the bias current i0=mχi _NM1-m*I_PM10 provided by the transistor PM0, where I _NM1 represents the current of the transistor NM1, mχi _NM1 is a fixed part and does not vary with the input common mode level V _CM,IN, I _PM10 represents the current of the transistor PM10, mχi _PM10 is a variable part and varies with the input common mode level V _CM,IN;

When the input common mode level is higher than a preset threshold or lower than the preset threshold, the transistor PM11 or the transistor NM2 is turned off, when I _PM10 = 0 and the bias current I0 = m x I _NM1, and when the input common mode level is at an intermediate level or near the reference voltage V _REF, the bias circuit module enables the transistors PM11 and NM2 to be turned on by adjusting the sizes of the transistors PM11, NM2 and NM3 so that I _PM10 >0 reduces the bias voltage I0, thereby compensating the increase of the total transconductance Gm of the circuit caused by the simultaneous operation of the first group of PMOS tube input differential pairs PM1 and PM2 and the second group of PMOS tube input differential pairs PM3 and PM 4.

Further, the input stage further comprises a load module;

The drain electrode of one transistor in the first PMOS tube input differential pair and the drain electrode of one transistor in the second PMOS tube input differential pair are connected to the negative end output VON1 of the input stage, and the drain electrode of the other transistor in the first PMOS tube input differential pair and the drain electrode of the other transistor in the second PMOS tube input differential pair are connected to the positive end output VOP1 of the input stage; the load module is connected with the VOP1 and the VON1 and used for primary amplification of signals and generating an input common mode level of a rear-stage circuit;

the load module comprises two grounding resistors R1 and R2 with equal resistance values, one end of the resistor R1 is grounded, the other end of the resistor R2 is grounded, and the other end of the resistor R is grounded.

Further, the output signal VOD comprises a comparator module positioned behind the input stage, the VOP1 and the VON1 are respectively connected to the positive end input and the negative end input of the comparator module, and the VOP1 and the VON1 signals are amplified and/or shaped through the comparator module to obtain the output signal VOUT.

Further, the comparator module includes PMOS transistors PM12, PM13, and PM14, NMOS transistors NM6, NM7, NM8, and NM9, and an output stage;

transistors PM13 and PM14 are used as input differential pairs, the gates of the transistors PM13 and PM14 are respectively connected to the VOP1 and VON1 signals, and the sources of the transistors PM13 and PM14 are connected to the drain of the transistor PM12 at the same time;

The drain of the transistor PM13 is connected to the drain and the gate of the transistor NM8, and is connected to the drain of the transistor NM6, and is connected to the gate of the transistor NM7, and is connected to the negative input terminal of the output stage, and the drain of the transistor PM14 is connected to the drain and the gate of the transistor NM9, and is connected to the drain of the transistor NM7, and is connected to the gate of the transistor NM6, and is connected to the positive input terminal of the output stage;

transistors NM6, NM7, NM8 and NM9 form a diode load with positive feedback for realizing hysteresis;

the output stage is used for amplifying, differentiating, converting to single end and/or shaping the signal and outputting the signal VOUT.

Further, the level shifting block comprises NMOS transistors NM4 and NM5 and NMOS transistors NM16 and NM17, wherein the gates of the transistors NM16 and NM17 are respectively connected to the differential input signal pairs VP and VN, the sources of the transistors NM16 and NM17 are respectively connected to the gates of the transistors PM1 and PM2, and are respectively connected to the drains of the transistors NM4 and NM5, the drains of the transistors NM16 and NM17 are both connected to a power supply voltage VDD, the gates of the transistors NM4 and NM5 are both connected to a first bias voltage V _BIAS1, the sources of the transistors NM4 and NM5 are both connected to a ground voltage VSS, and the transistors NM4 and NM5 are used for the function of a current source;

And/or the reference voltage module comprises a PMOS transistor PM15 and an NMOS transistor NM10, wherein the source electrode of the transistor NM10 is grounded to the voltage VSS, the grid electrode is connected to the first bias voltage V _BIAS1, the transistor NM10 is used for acting as a current source, meanwhile, the drain electrode of the transistor NM10 is connected to the grid electrode and the drain electrode of the transistor PM15, the source electrode of the transistor PM15 is connected to the power supply voltage VDD, and the drain electrode output of the transistor NM10 provides the grid voltage V _REF for the transistor PM 5.

The invention also provides a chip, and a receiver capable of converting LVDS signals is integrated on the chip, and comprises the LVDS receiving circuit.

Compared with the prior art, the LVDS receiving circuit with the wide input common mode range has the advantages and positive effects that the LVDS receiving circuit with the wide input common mode range can achieve the input common mode range close to the rail-to-rail range under low power supply voltage, the circuit transconductance Gm is smaller along with the common mode change, the speed, the gain, the hysteresis and the like of the circuit are smaller along with the common mode change, and the influence of the input common mode change on the speed, the gain, the hysteresis and the like of the circuit is obviously reduced.

Drawings

Fig. 1 is a schematic diagram of a LVDS receiver circuit in the prior art.

Fig. 2 is a schematic diagram of a structure of an LVDS receiver circuit for implementing a common mode range of a rail-to-rail input according to the prior art.

Fig. 3 is an input stage block diagram of another LVDS receiver circuit implementing a near rail-to-rail input common mode range provided in the prior art.

Fig. 4 is a schematic structural diagram of an LVDS receiving circuit with a wide input common mode range according to the present invention.

Fig. 5 is a schematic circuit diagram of each module of the LVDS receiving circuit provided by the present invention.

Reference numerals illustrate:

A level shift module 10;

a reference voltage module 20;

A bias circuit module 30;

a load module 40;

A comparator module 50.

Detailed Description

The wide input common mode range LVDS receiving circuit and the chip disclosed in the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be regarded as being isolated, and they may be combined with each other to achieve a better technical effect. In the drawings of the embodiments described below, like reference numerals appearing in the various drawings represent like features or components and are applicable to the various embodiments. Thus, once an item is defined in one drawing, no further discussion thereof is required in subsequent drawings.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings are merely used in conjunction with the disclosure of the present specification, and are not intended to limit the applicable scope of the present invention, but rather to limit the scope of the present invention. The scope of the preferred embodiments of the present invention includes additional implementations in which functions may be performed out of the order described or discussed, including in a substantially simultaneous manner or in an order that is reverse, depending on the function involved, as would be understood by those of skill in the art to which embodiments of the present invention pertain.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values.

Examples

Referring to fig. 4, an LVDS receiving circuit with a wide input common mode range is provided in this embodiment.

The LVDS receiving circuit comprises an input stage and a comparator module positioned behind the input stage.

The input stage comprises a first-stage input end and a second-stage input end, a first group of PMOS tube input differential pairs PM1 and PM2 and a second group of PMOS tube input differential pairs PM3 and PM4, a level shift circuit module, a PMOS transistor PM5 used as a switch, a reference voltage module for providing grid voltage for the transistor PM5, a bias circuit module and a load module.

The first stage input and the second stage input are used to apply differential input signal pairs VP (positive side signal) and VN (negative side signal).

The differential input signal pair VP and VN are respectively and directly connected to the gates of the two transistors PM3 and PM4 of the second PMOS transistor input differential pair, so as to control the leakage currents of the two transistors PM3 and PM 4. Meanwhile, the differential input signal pair VP and VN are also indirectly connected to the gates of the two transistors PM1 and PM2 of the first group of PMOS transistor input differential pair through the level shift circuit module, respectively, for leakage currents of the two transistors PM1 and PM 2.

The level shifting module is used for reducing the input common mode level.

The drain of the transistor PM5 is connected to a first node with the sources of the two transistors PM1 and PM2 of the first set of PMOS transistor input differential pairs, see point A in FIG. 4, while the source of the transistor PM5 is connected to a second node with the sources of the two transistors PM3 and PM4 of the second set of PMOS transistor input differential pairs, see point B in FIG. 4, and the gate of the transistor PM5 is connected to a reference voltage block.

The reference voltage module provides a reference voltage V _REF to the transistor PM5, V _REF as a gate voltage of the transistor PM 5.

The bias circuit module is used for providing bias current I0 of the input stage and performing control configuration of the bias current, and is used for realizing the bias current and control thereof in FIG. 4. Specifically, the bias circuit module is configured to reduce the output bias current I0 such that the bias current I0 flowing to the first node and the second node is reduced when it is determined that the input common mode level is at the intermediate level or the difference between the input common mode level and the reference voltage V _REF is within a preset range.

The load module is connected with the positive end output VOP1 and the negative end output VON1 of the input stage and is used for primary amplification of signals and generation of input common mode level of a later-stage circuit. Specifically, the drain electrodes of one transistor in the first group of PMOS transistor input differential pair and one transistor in the second group of PMOS transistor input differential pair are connected to the negative end output VON1 of the input stage, the drain electrodes of the other transistor in the first group of PMOS transistor input differential pair and the other transistor in the second group of PMOS transistor input differential pair are connected to the positive end output VOP1 of the input stage, and the load module is connected with the VOP1 and the VON1 for primary amplification of signals and generating the input common mode level of the post-stage circuit.

The comparator module is connected with the positive end output VOP1 and the negative end output VON1 of the input stage and is used for amplifying and/or shaping signals so as to obtain an output signal VOUT.

In this embodiment, the bias current I0 output by the bias circuit module is related to an input common mode level V _CM,IN, where V _CM,IN = (vp+vn)/2, VP represents the positive side signal and VN represents the negative side signal. That is, the value of the bias current I0 is affected by the input common mode level V _CM,IN = (vp+vn)/2.

Specifically, the output bias current I0 is a correlation function of the input common mode level V _CM,IN, and the relation expression is denoted by i0=i _Fixing+f(V_CM,IN), where I _Fixing is independent of the input common mode level V _CM,IN, and f (V _CM,IN) represents a function related to the input common mode level V _CM,IN. In connection with the example of fig. 4, the I _Fixing=I_B, i.e., fixed portion of the bias current I0, is equal to the point B current value I _B.

The weight duty cycle of the configuration f (V _CM,IN) in the foregoing relation represents the formula i0=i _Fixing+f(V_CM,IN) to reduce the influence of the input common mode level V _CM,IN on the bias current I0. In this way, the weight of f (V _CM,IN) in the configuration current is made relatively small, thereby reducing the degree to which the bias current varies with the variation of the input common mode level.

When the function f (V _CM,IN) is configured, when the difference between the input common mode level V _CM,IN and the power supply voltage or the ground voltage is within a preset range, i.e., when the input common mode level is close to the power supply voltage and the ground voltage, f (V _CM,IN) =0, and when the difference between the power supply voltage and the reference voltage V _REF is within the preset range, i.e., when the power supply voltage is close to the vicinity of V _REF, f (V _CM,IN) is made to be a preset negative value, so that the bias current I0 is reduced.

In this embodiment, the bias circuit module may specifically include a comparing unit and a bias current I0 control unit.

The comparing unit is configured to compare the input common mode level with a reference voltage V _REF, a power supply voltage, and a ground voltage, and to transmit the comparison result to the bias current I0 control unit.

The bias current I0 control unit is configured to acquire the comparison result, determine that the input common mode level is close to the ground voltage when the difference value between the input common mode level and the ground voltage is within a preset range, determine that the transistor PM5 is in an off state, make the bias current I0 flow to the second node entirely, determine that the two transistors PM3 and PM4 of the second group of PMOS input differential pairs operate when the difference value between the input common mode level and the power supply voltage is within the preset range, determine that the input common mode level is close to the power supply voltage when the difference value between the input common mode level and the power supply voltage is within the preset range, make the two transistors of the second group of PMOS input differential pairs turn off, bias current I0 mainly flows to the source of the transistor PM5, determine that the two transistors PM1 and PM2 of the first group of PMOS input differential pairs operate, reduce the direct current level of the differential input signal pairs VP and VN through the level shift module, and determine that the common mode level is close to the reference voltage V _REF when the difference value between the input common mode level and the reference voltage V _REF is within the preset range, make the bias current I0 flow to the first node and the second node, and bias current I0 flow to the first group of PMOS input differential pairs simultaneously, and bias the two transistors I0 input differential pairs are reduced.

As will be understood with reference to the LVDS receiver circuit shown in fig. 4, when the input common mode level approaches the ground voltage, the voltage at the point B is also lower, the transistor PM5 is in an off state, the bias current I0 output by the bias circuit module flows to the point B, at this time, the two transistors PM3 and PM4 of the second PMOS transistor input differential pair operate, and the input signal is amplified and shaped by the load and the comparator circuit at the later stage to obtain the output signal VOUT. When the input common mode level approaches to the power supply voltage, the two transistors PM3 and PM4 of the second group of PMOS input differential pair are turned off, the voltage at the point B is higher, the bias current I0 mainly flows to the source of the transistor PM5, at this time, the level shift circuit will reduce the dc level of the differential input signal pair VP and VN, the two transistors PM1 and PM2 of the first group of PMOS input differential pair work, and the input signal is amplified and shaped by the load and the comparator circuit at the later stage to obtain the output signal VOUT. When the input common mode level is near the reference voltage V _REF, the bias current I0 flows to the point a and the point B at the same time, the two transistors PM1 and PM2 of the first group of PMOS input differential pairs and the two transistors PM3 and PM4 of the second group of PMOS input differential pairs work at the same time, at this time, the bias circuit module can reduce the output bias current I0, and then the input signals are amplified and shaped to obtain the output VOUT by the load module and the comparator circuit of the later stage. The bias current I0 output by the circuit is regulated down, so that the increase of the total transconductance Gm of the circuit caused by the simultaneous operation of the two groups of PMOS tube input differential pairs PM1, PM2, PM3 and PM4 can be compensated, the change of the transconductance Gm of the circuit along with the common mode is smaller, the change of the speed, gain, hysteresis and the like of the circuit along with the common mode is also smaller, and the working stability of the circuit is improved.

As a typical preferred mode, referring to fig. 5, the bias circuit module may specifically include PMOS transistors PM0, PM8, PM9, PM10, and PM11, NMOS transistors NM1, NM2, and NM3, and two resistors R3 and R4 having equal resistance values.

The drain electrode of the transistor PM0 is connected with the source electrodes of the transistors PM3 and PM4 of the second group of PMOS transistor input differential pairs to provide bias current I0 for the input stage, the source electrode of the transistor PM0 is connected with the power supply voltage VDD, the gate electrode of the transistor PM0 is connected with the gate electrode and the drain electrode of the transistor PM8, the drain electrode of the transistor NM1 is connected with the drain electrode of the transistor PM9, the transistors PM0 and PM8 form a current mirror, and the source electrodes of the transistors PM8 and PM9 are connected with the power supply voltage VDD.

The gate of the transistor NM1 is connected to the bias voltage V _BIAS, and the source is connected to the ground voltage VSS to form a current source.

The gate of the transistor PM9 is connected to the gate and drain of the transistor PM10, and the transistors PM9 and PM10 constitute a current mirror. The source of the transistor PM10 is connected to the power supply voltage VDD, the drain of the transistor PM10 is also connected to the source of the transistor PM11, the drain of the transistor PM11 is connected to the drain of the transistor NM2, the source of the transistor NM2 is simultaneously connected to the drain and the gate of the transistor NM3, and the source of the transistor NM3 is grounded to the voltage VSS.

The gates of the transistor PM11 and the transistor NM2 are connected to the junction of the resistors R3 and R4, the other end of the resistor R3 is connected to the input positive terminal signal VP of the receiving circuit, the other end of the resistor R4 is connected to the input negative terminal signal VN of the receiving circuit, and the potential at the junction of the resistors R3 and R4 is the input common mode level V _CM,IN.

The regulation and control process of the bias circuit module is as follows, let the ratio of the width-to-length ratio of the transistor PM0 to the transistor PM8 be m, and the ratio of the width-to-length ratio of the transistor PM9 to the transistor PM10 be 1.

The bias current I0=I_PM0=m*I_PM8=m*(I_NM1-I_PM9)=m*I_NM1-m*I_PM9= m*I_NM1-m*I_PM10, provided by the transistor PM0, wherein I _PM0 represents the current of the transistor PM0, I _PM8 represents the current of the transistor PM8, I _PM9 represents the current of the transistor PM9, I _PM10 represents the current of the transistor PM10, I _NM1 represents the current of the transistor NM1, m×i _NM1 is a fixed part and does not change with the input common mode level V _CM,IN, and m×i _PM10 is a variable part and changes with the input common mode level V _CM,IN.

When the input common mode level is higher than or lower than the preset threshold, i.e. when the input common mode level is higher or lower, the transistor PM11 or the transistor NM2 is turned off, when I _PM10 =0, the bias current i0=mχi _NM1 is a fixed value, and when the input common mode level is at an intermediate level or near the reference voltage V _REF, the bias circuit module can adjust the sizes of the transistors PM11, NM2 and NM3 to make the transistors PM11 and NM2 turned on, when I _PM10 >0, so that i0=mχi _NM1-m*I_NM10 is smaller than the m×i _NM1, i.e. the bias voltage I0 is reduced, thereby compensating the increase of the total circuit transconductance Gm caused by the simultaneous operation of the first PMOS input differential pair PM1 and PM2 and the second PMOS input differential pair PM3 and PM 4.

With continued reference to fig. 5, for the preferred embodiment of each module in the LVDS receiving circuit provided by the present invention, the circuit composition of the level shifting module 10, the reference voltage module 20, and the load module 40 and the comparator module 50 is also illustrated.

The level shift module 10 may specifically include NMOS transistors NM4, NM5 and NMOS transistors NM16, NM17. The gates of the transistors NM16 and NM17 are respectively connected to the differential input signal pair VP and VN, the sources of the transistors NM16 and NM17 are respectively connected to the gates of the transistors PM1 and PM2, and are respectively connected to the drains of the transistors NM4 and NM5, the drains of the transistors NM16 and NM17 are both connected to the power supply voltage VDD, the gates of the transistors NM4 and NM5 are both connected to the first bias voltage V _BIAS1, the sources of the transistors NM4 and NM5 are both connected to the ground voltage VSS, and the transistors NM4 and NM5 are used for the function of a current source.

The reference voltage module 20 may specifically include a PMOS transistor PM15 and an NMOS transistor NM10. The source electrode of the transistor NM10 is grounded to the voltage VSS, the grid electrode is connected to the first bias voltage V _BIAS1, the transistor NM10 is used for acting as a current source, meanwhile, the drain electrode of the transistor NM10 is connected to the grid electrode and the drain electrode of the transistor PM15, the source electrode of the transistor PM15 is connected to the power supply voltage VDD, and the drain electrode output of the transistor NM10 provides the grid electrode voltage V _REF for the transistor PM 5.

The load module 40 may specifically include two resistors R1 and R2 with equal resistance values, one end of the resistor R1 is grounded, the other end of the resistor R2 is grounded, and the other end of the resistor R2 is connected to VOP1.

The latter comparator block 50 has a hysteresis function and may include PMOS transistors PM12, PM13, PM14, NMOS transistors NM6, NM7, NM8, NM9, and an output stage.

The gates of the transistors PM13 and PM14 are connected to the VOP1 and VON1 signals respectively, the sources of the transistors PM13 and PM14 are connected to the drain of the transistor PM12, the gate of the transistor PM12 is connected to the second bias voltage V _BIAS2, and the source is connected to the power supply V _DDCORE to provide bias current for the transistors PM13 and PM 14.

The drain of the transistor PM13 is connected to the drain and gate of the transistor NM8 and to the drain of the transistor NM6 and to the gate of the transistor NM7 and to the negative input terminal of the output stage, and the drain of the transistor PM14 is connected to the drain and gate of the transistor NM9 and to the drain of the transistor NM7 and to the gate of the transistor NM6 and to the positive input terminal of the output stage.

Transistors NM6, NM7, NM8 and NM9 constitute a diode load with positive feedback for implementing hysteresis.

According to the LVDS receiving circuit with the input common mode range, on one hand, the input common mode level of the circuit can reach the range close to the rail under the low power supply voltage through the two groups of PMOS (P-channel metal oxide semiconductor) input differential pairs, the level shifting module, the PMOS transistor serving as a switching function and the reference voltage module, and on the other hand, the bias circuit module is used for adjusting and controlling bias current to compensate the increase of the total transconductance Gm of the circuit caused by the simultaneous operation of the two groups of PMOS transistor input differential transistor pairs, so that the change of the transconductance Gm of the circuit along with the common mode is smaller, the influence of the change of the input common mode on the speed, the gain, the hysteresis and the like of the circuit is reduced, and the working stability of the circuit is improved.

In another embodiment of the present invention, a chip is further provided, and a receiver capable of converting LVDS signals is integrated on the chip, where the receiver includes the LVDS receiving circuit.

Other technical features are described in the previous embodiments and are not described in detail here.

In the above description, the disclosure of the present invention is not intended to limit itself to these aspects. Rather, the components may be selectively and operatively combined in any number within the scope of the present disclosure. In addition, terms like "comprising," "including," and "having" should be construed by default as inclusive or open-ended, rather than exclusive or closed-ended, unless expressly defined to the contrary. All technical, scientific, or other terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Common terms found in dictionaries should not be too idealized or too unrealistically interpreted in the context of the relevant technical document unless the present disclosure explicitly defines them as such. Any alterations and modifications of the present invention, which are made by those of ordinary skill in the art based on the above disclosure, are intended to be within the scope of the appended claims.

Claims

1. The low voltage differential signaling LVDS receiving circuit with the wide input common mode range comprises an input stage, wherein the input stage comprises a first stage input end, a second stage input end, a first group of PMOS (P-channel metal oxide semiconductor) tube input differential pair, a second group of PMOS tube input differential pair and a level shift module, the first stage input end and the second stage input end are used for applying differential input signal pairs VP and VN, the differential input signal pairs VP and VN are respectively and directly connected with the gates of two transistors of the second group of PMOS tube input differential pair and used for controlling leakage currents of the two transistors, the differential input signal pairs VP and VN are also indirectly connected with the gates of the two transistors of the first group of PMOS tube input differential pair through the level shift module and used for controlling the leakage currents of the two transistors, and the level shift module is used for reducing the input common mode level and is characterized in that:

2. The LVDS receiving circuit according to claim 1, wherein the bias current I0 output by the bias circuit module is related to an input common mode level V _CM,IN, the input common mode level V _CM,IN = (VP+VN)/2, VP represents a positive side signal, and VN represents a negative side signal;

3. The LVDS receiving circuit according to claim 1 or 2, wherein the bias circuit module comprises a comparing unit and a bias current I0 control unit;

4. The LVDS receiving circuit according to claim 3, wherein said bias circuit module comprises PMOS transistors PM0, PM8, PM9, PM10 and PM11, NMOS transistors NM1, NM2 and NM3, and two resistors R3 and R4 having equal resistance values;

5. The LVDS receiving circuit of claim 4, wherein let the ratio of the width to length ratio of the transistor PM0 to the transistor PM8 be m and the ratio of the width to length ratio of the transistor PM9 to the transistor PM10 be 1, the bias current I0=mI _NM1-m*I_PM10 provided by the transistor PM0, wherein I _NM1 represents the current of the transistor NM1, mI _NM1 is a fixed portion and does not vary with the input common mode level V _CM,IN, I _PM10 represents the current of the transistor PM10, and mI _PM10 is a variable portion and varies with the input common mode level V _CM,IN;

6. The LVDS receiving circuit of claim 1, wherein the input stage further comprises a load module;

7. The LVDS receiving circuit of claim 6, further comprising a comparator module located after the input stage, wherein said VOP1 and VON1 are connected to a positive side input and a negative side input of said comparator module, respectively, and wherein the VOP1 and VON1 signals are amplified and/or shaped by said comparator module to obtain an output signal VOUT.

8. The LVDS receiving circuit according to claim 7, wherein said comparator module comprises PMOS transistors PM12, PM13 and PM14, NMOS transistors NM6, NM7, NM8 and NM9, and an output stage;

9. The LVDS receiving circuit according to claim 1, wherein said level shifting block comprises NMOS transistors NM4 and NM5, and NMOS transistors NM16 and NM17, wherein gates of said transistors NM16 and NM17 are respectively connected to differential input signal pairs VP and VN, sources of said transistors NM16 and NM17 are respectively connected to gates of said transistors PM1 and PM2, and are respectively connected to drains of said transistors NM4 and NM5, drains of said transistors NM16 and NM17 are both connected to a power supply voltage VDD, gates of said transistors NM4 and NM5 are both connected to a first bias voltage V _BIAS1, sources of said transistors NM4 and NM5 are both connected to a ground voltage VSS, and said transistors NM4 and NM5 are used for current source operation;

10. A chip on which a receiver capable of converting LVDS signals is integrated, characterized in that the receiver comprises the LVDS receiving circuit as set forth in any one of claims 1 to 9.