CN116482215B - Dielectric layer reliability evaluation method and dielectric layer reliability evaluation test system - Google Patents
Dielectric layer reliability evaluation method and dielectric layer reliability evaluation test system Download PDFInfo
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Abstract
本公开实施例涉及半导体领域，提供一种介质层可靠性评估方法和评估介质层可靠性的测试系统，方法包括：提供存储器，存储器包括多个子字线驱动器和多条子字线，每个子字线驱动器包括多个晶体管，每个晶体管包括栅极、源极、漏极和介质层，多个晶体管共用栅极和源极，多条子字线与多个漏极一一对应电连接；给存储器提供预充电指令，给至少一个子字线驱动器进行预充电，且所有子字线处于关断状态，至少一个子字线驱动器经历至少一次预充电，实时获取每一预充电所经历的实际时长；进行预充电的子字线驱动器中的介质层为目标介质层，基于实际时长实现对目标介质层的可靠性评估。本公开实施例至少可以实现对子字线驱动器中目标介质层的可靠性评估。
The disclosed embodiments relate to the semiconductor field, and provide a dielectric layer reliability evaluation method and a test system for evaluating the dielectric layer reliability. The method includes: providing a memory, the memory includes multiple sub-word line drivers and multiple sub-word lines, each sub-word line driver includes multiple transistors, each transistor includes a gate, a source, a drain and a dielectric layer, multiple transistors share a gate and a source, and multiple sub-word lines are electrically connected to multiple drains in a one-to-one correspondence; providing a precharge instruction to the memory, precharging at least one sub-word line driver, and all sub-word lines are in an off state, at least one sub-word line driver undergoes at least one precharge, and the actual duration of each precharge is obtained in real time; the dielectric layer in the sub-word line driver that is precharged is the target dielectric layer, and the reliability evaluation of the target dielectric layer is realized based on the actual duration. The disclosed embodiments can at least realize the reliability evaluation of the target dielectric layer in the sub-word line driver.
Description
Technical Field
The embodiment of the disclosure relates to the field of semiconductors, and provides a dielectric layer reliability evaluation method and a test system for evaluating the reliability of a dielectric layer.
Background
As the integration density of memory increases, the thickness of the dielectric layer of the transistor in the memory decreases. In addition, as the dielectric layer of the transistor is continuously developed towards the direction of the thin film, the power supply voltage in the memory and the voltages on various circuits are not easy to be reduced, so that higher requirements are put on the anti-electric performance of the thin film of the dielectric layer under higher electric field intensity. The poor anti-electrical performance of the dielectric layer may cause unstable electrical parameters of the memory, such as threshold voltage drift, transconductance decrease or leakage current increase, and further may cause breakdown of the dielectric layer, resulting in failure of the memory, and thus the whole integrated circuit is in a breakdown state. It is therefore necessary to evaluate and test the reliability of the dielectric layer to evaluate the reliability of the memory.
At present, the reliability of a dielectric layer is evaluated, the dielectric layer to be evaluated is generally tested, an external circuit is electrically connected with the dielectric layer, the voltage at two ends of the dielectric layer when the dielectric layer is broken down, the current flowing through the dielectric layer, the time from the beginning of the test to the breakdown and the like are measured in real time, the reliability of the dielectric layer is represented by the parameters, and the service life of the dielectric layer can be predicted.
However, there is currently a lack of a method for reliability evaluation of dielectric layers of multiple transistors in a memory, such as in a sub-word line driver.
Disclosure of Invention
The embodiment of the disclosure provides a dielectric layer reliability evaluation method and a test system for evaluating the reliability of a dielectric layer, which are at least beneficial to the realization of the reliability evaluation of a target dielectric layer in a sub-word line driver.
According to some embodiments of the present disclosure, an aspect of the embodiments provides a method for evaluating reliability of a dielectric layer, including providing a memory, where the memory includes a plurality of sub-word line drivers and a plurality of sub-word lines, each sub-word line driver includes a plurality of transistors, each transistor includes a gate, a source, a drain, and a dielectric layer, the plurality of transistors share the gate and the source, the plurality of sub-word lines are electrically connected to the plurality of drains in a one-to-one correspondence manner, providing a precharge instruction to the memory, performing precharge on at least one sub-word line driver, and all sub-word lines are in an off state, at least one sub-word line driver undergoes at least one precharge, an actual duration undergone by each precharge is acquired in real time, and the dielectric layer in the sub-word line driver performing the precharge is a target dielectric layer, and reliability evaluation on the target dielectric layer is achieved based on the actual duration.
In some embodiments, the step of evaluating the reliability of the target dielectric layer based on the actual time length includes determining, in real time, the actual time length and a maximum time length allowed to be experienced by the precharge, and if the actual time length is greater than the maximum time length, determining that the target dielectric layer fails.
In some embodiments, the step of acquiring the actual duration of each precharge in real time further includes acquiring a standby current of the memory in each precharge step in real time, where the standby current is a quiescent current when all memory cells in the memory are in an idle state in the precharge step, and determining in real time the standby current and a maximum standby current allowed to pass through the memory when the memory is precharged, if the actual duration is less than or equal to the maximum duration and the standby current is greater than the maximum standby current, determining that the target dielectric layer fails.
In some embodiments, the memory further includes a first terminal for applying an operating voltage and a second terminal for grounding, and the step of obtaining the standby current in each of the precharging steps includes obtaining a current flowing from the first terminal through the second terminal in real time in the precharging step.
In some embodiments, the standby current acquired for the first time is taken as an initial standby current, and the ratio of the maximum standby current to the initial standby current is greater than or equal to 2.
In some embodiments, in the step of precharging at least one of the sub-word line drivers, the gate is at a first potential, a plurality of the drains are all at a second potential, and the second potential is lower than the first potential, the first potential and the second potential both being constant values.
In some embodiments, the evaluating method further comprises evaluating the reliability of the dielectric layer a plurality of times, and in different of the evaluating steps, the first potential is different in magnitude.
In some embodiments, in the step of precharging at least one of the sub word line drivers, the gate is at a first potential, a plurality of the drains are all at a second potential, and the second potential is lower than the first potential, and while the second potential is a constant value, in any of the steps of precharging, the magnitude of the first potential gradually increases with the progress time of the precharge.
In some embodiments, the evaluating method further comprises evaluating the reliability of the dielectric layer a plurality of times, and in different of the evaluating steps, the magnitude of the first potential is different in magnitude as the precharge proceeds.
In some embodiments, each of the sub-word line drivers includes at least 4 of the transistors arranged in an array, and the common gate of a plurality of the transistors is a ring structure.
In some embodiments, in the step of providing the precharge instruction for the memory, the precharge is performed for all the sub-word line drivers in the memory, all the sub-word line drivers undergo the precharge at least once at the same time, the actual duration of each of the precharges is obtained in real time, and the reliability evaluation of the target dielectric layer is implemented based on the actual duration.
In some embodiments, the memory includes a plurality of main word lines electrically connected to the gates of the plurality of sub-word line drivers in a one-to-one correspondence, and at least one of the main word lines controls at least one of the gates to be at a first potential in the step of providing the precharge instruction to the memory.
According to some embodiments of the present disclosure, another aspect of the embodiments further provides a test system for evaluating reliability of a dielectric layer, including a memory including a plurality of sub-word line drivers and a plurality of sub-word lines, each of the sub-word line drivers including a plurality of transistors, each of the transistors including a gate, a source, a drain, and a dielectric layer, the plurality of transistors sharing the gate and the source, the plurality of sub-word lines being electrically connected to the plurality of drains in one-to-one correspondence, a precharge module configured to provide a precharge instruction to the memory, precharge at least one of the sub-word line drivers, and all of the sub-word lines being in an off state, an acquisition module, during a period of operation of the memory, the sub-word line drivers undergoing at least one of the precharging, the acquisition module being configured to acquire an actual time period that each of the precharging is undergone, a determination module, the dielectric layer in the sub-word line drivers undergoing the precharging being a target layer, the determination module being configured to implement the reliability evaluation of the dielectric layer based on the target time period.
In some embodiments, the medium layer in the sub word line driver performing the pre-charging is a target medium layer, and the judging module comprises a parameter setting module configured to provide a maximum duration allowed to be experienced by the pre-charging, and a comparing module configured to judge the actual duration and the maximum duration in real time, and judge that the target medium layer fails if the actual duration is greater than the maximum duration.
In some embodiments, the acquisition module is further configured to acquire a standby current of the memory during the step of pre-charging, the standby current being a quiescent current of all memory cells in the memory during the step of pre-charging when the memory cells are in an idle state.
In some embodiments, the parameter setting module is further configured to provide a maximum standby current allowed to pass through the memory when the pre-charging is performed, and the comparison module is further configured to determine the standby current and the maximum standby current in real time, and determine that the target dielectric layer fails if the actual duration is less than or equal to the maximum duration and the standby current is greater than the maximum standby current.
In some embodiments, in the step of precharging at least one of the sub-word line drivers, the gate is at a first potential, a plurality of the drains are all at a second potential, and the second potential is lower than the first potential, the precharge module is further configured to control both the first potential and the second potential to be constant values.
In some embodiments, in the step of precharging at least one of the sub-word line drivers, the gate is at a first potential, a plurality of the drains are all at a second potential, and the second potential is lower than the first potential, the precharge module is further configured to control the magnitude of the first potential to gradually increase with an proceeding time of the precharge while controlling the second potential to be a constant value in any of the steps of precharging.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages:
In the technical scheme, the operating characteristics of the memory are utilized, in the precharge stage, all transistors in at least one sub-word line driver are in an on state, in the precharge stage, all transistors in the at least one sub-word line driver are in an off state, so that a plurality of transistor drains electrically connected with the sub-word lines are in the same potential, on one hand, if one sub-word line driver is precharged, all transistors in the sub-word line driver share a grid electrode, the voltages at two ends of a dielectric layer of all transistors in the sub-word line driver are consistent, and therefore reliability evaluation of the dielectric layer of all transistors in the sub-word line driver is achieved, on the other hand, in the precharge stage, all transistors in the sub-word line driver are in an on state, and the precharge stage applies voltages to a plurality of common grid electrodes of the sub-word line driver to be consistent, and therefore reliability evaluation of the dielectric layers of the sub-word line driver can be achieved simultaneously. In addition, based on the actual duration of the precharge experience, whether the electrical resistance of the target dielectric layer is reduced or not and whether the target dielectric layer fails or is broken down or not are judged, and the reliability evaluation of the target dielectric layer can be realized without additionally adding test equipment for measuring the voltage at two ends of the target dielectric layer and the current flowing through the target dielectric layer.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
FIG. 1 is a schematic diagram of a circuit for evaluating reliability of a transistor dielectric layer;
FIG. 2 is a flowchart of a method for evaluating reliability of a dielectric layer according to an embodiment of the present disclosure;
FIG. 3 is a schematic top view of a sub-word line driver according to an embodiment of the disclosure;
FIG. 4 is a schematic circuit diagram schematically illustrating a dielectric layer reliability evaluation method according to an embodiment of the present disclosure;
FIG. 5 is a graph of the broken line of the actual time duration experienced by each precharge as the memory run time increases, according to one embodiment of the present disclosure;
FIG. 6 is a graph showing a broken line of the standby current of the memory in each precharge step according to an embodiment of the present disclosure as the memory operation time increases;
fig. 7 is a schematic functional block diagram of a test system for evaluating reliability of a dielectric layer according to another embodiment of the present disclosure.
Detailed Description
According to analysis, as the dielectric layer of the transistor is continuously developed towards the direction of the film, higher requirements are put on the anti-electric performance of the dielectric layer film under higher electric field intensity. Therefore, the reliability of the dielectric layer needs to be evaluated and tested to determine under which conditions the dielectric layer will break down. Breakdown of the dielectric layer generally includes Time dependent dielectric Breakdown (TDDB, time-DEPENDENT DIELECTRIC break down) and transient Breakdown (TZDB, time-ZeroDielectric Breakdown), wherein Time dependent dielectric Breakdown is also referred to as Time dependent Breakdown.
In the current evaluation method, the dielectric layer is generally tested for time-lapse breakdown, an electric field is externally applied to the transistor, and parameters such as breakdown electric quantity, breakdown time and the like are actually measured to represent the advantages and disadvantages of the dielectric layer in terms of the anti-electric property and reliability. In addition, when the reliability evaluation is performed on the dielectric layer, in general, for regular transistors, that is, for the case that one gate, one source, one drain or one dielectric layer is not shared among a plurality of transistors, the reliability evaluation is only performed on the dielectric layer of a specific transistor, and the reliability evaluation cannot be performed on the dielectric layers of a plurality of transistors in the memory at the same time.
Referring to fig. 1, fig. 1 is a schematic circuit diagram of a transistor dielectric layer reliability evaluation, in which an external power source is directly applied to a gate 110 of a transistor 100, an anode of the external power source is electrically connected to the gate 110, a cathode of the external power source is electrically connected to a substrate 130, the substrate 130 and the gate 110 are isolated from each other by a dielectric layer 120, a voltage across the dielectric layer 120, i.e., a voltage between the substrate 130 and the gate 110, is measured by a voltmeter, a current flowing through the dielectric layer 120 is measured by a ammeter, and whether the dielectric layer 120 fails, e.g., a sudden increase in current, is determined, so that the dielectric layer 120 is broken down, and a time elapsed during this time is a lifetime of the dielectric layer 120 under this voltage.
However, there is currently a lack of methods for reliability evaluation of dielectric layers of a plurality of transistors in a memory, and a lack of methods for reliability evaluation of a plurality of dielectric layers in a memory at the same time.
The embodiment of the disclosure provides a dielectric layer reliability evaluation method and a test system for evaluating the reliability of a dielectric layer, wherein in the method, at least one sub-word line driver is precharged by utilizing a memory precharge stage, so that all transistors in the at least one sub-word line driver for precharging are in an on state, and in the precharge stage, all the sub-word lines are in an off state, on one hand, if one sub-word line driver is precharged, all the transistors in the sub-word line driver are in an on state, thereby realizing the reliability evaluation of the dielectric layer in the sub-word line driver, on the other hand, in the precharge stage, if a plurality of sub-word line drivers are precharged, all the transistors in the plurality of sub-word line drivers are in an on state, thereby simultaneously evaluating the reliability of a plurality of dielectric layers in the plurality of sub-word line drivers for precharging. In addition, based on the actual duration of the precharge experience, whether the electrical resistance of the target dielectric layer is reduced or not and whether the target dielectric layer fails or is broken down or not are judged, and the reliability evaluation of the target dielectric layer can be realized without additionally adding test equipment for measuring the voltage at two ends of the target dielectric layer and the current flowing through the target dielectric layer.
Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the various embodiments of the present disclosure. The technical solutions claimed in the embodiments of the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.
An embodiment of the present disclosure provides a method for evaluating reliability of a dielectric layer, and the method for evaluating reliability of a dielectric layer provided in an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Fig. 2 is a flowchart of a dielectric layer reliability evaluation method according to an embodiment of the present disclosure, fig. 3 is a schematic diagram of a top view structure of a sub-word line driver according to an embodiment of the present disclosure, fig. 4 is a schematic diagram schematically illustrating a circuit in the dielectric layer reliability evaluation method according to an embodiment of the present disclosure, fig. 5 is a schematic diagram of a broken line in which an actual time period of each precharge provided by an embodiment of the present disclosure changes with an increase in a memory operation time, and fig. 6 is a schematic diagram of a broken line in which a standby current of a memory in each precharge step provided by an embodiment of the present disclosure changes with an increase in the memory operation time.
Note that SWL in fig. 4 indicates a sub-word line, MWL indicates a main word line, VKK indicates a potential at which the four transistors 102 share the source 122.
Referring to fig. 2 and 3 in combination, the dielectric layer reliability evaluation method includes the steps of:
S101, providing a memory (not shown in the figure), wherein the memory comprises a plurality of sub word line drivers 101 and a plurality of sub word lines (not shown in the figure), each sub word line driver 101 comprises a plurality of transistors 102, each transistor 102 comprises a gate 112, a source 122, a drain 132 and a dielectric layer (not shown in the figure), the plurality of transistors 102 share the gate 112 and the source 122, and the plurality of sub word lines are electrically connected to the plurality of drains 132 in a one-to-one correspondence.
In the memory, a plurality of sub word lines are located in the memory cell array, and the sub word line driver 101 is configured to apply a voltage to the sub word lines in the memory cell array, so that the sub word line driver 101 can selectively control the plurality of sub word lines and realize fast switching of signal levels on the sub word lines.
In some embodiments, referring to fig. 3 and 4, each sub-word line driver 101 includes at least 4 transistors 102 arranged in an array, and the common gate 112 of the plurality of transistors 102 is a ring structure. In one example, each sub-word line driver 101 may include 4 transistors 102,4 transistors 102 arranged in a2×2 array, and the common gate 112 of the 4 transistors 102 is in a ring-shaped structure. Thus, one sub-word line driver 101 can simultaneously control 4 transistors 102 through one common gate 112. Since the drains 132 of the 4 transistors 102 are not shared, and one sub-word line is electrically connected to one drain 132, one sub-word line driver 101 can control 4 sub-word lines through the 4 drains 132, respectively, and the sub-word lines are at the same potential as the drains 132 corresponding to the sub-word lines.
It should be noted that, in fig. 3, the ring structure is exemplified by a square ring, the ring structure may also be a circular ring, in practical application, the specific shape of the ring structure is not limited, and in other embodiments, the common gate 112 may also be other shapes, such as a rectangle, which only needs to satisfy the channel regions of the 4 transistors 102. In addition, the dielectric layers are not illustrated in fig. 3, in some embodiments, the dielectric layers in the 4 transistors 102 of one sub-word line driver 101 may be the same film structure, that is, the 4 transistors 102 share the dielectric layer, which is located between the gate 112 and the channel region of the transistor 102 to realize insulation between the gate 112 and the channel region of the transistor 102, and in other embodiments, the dielectric layers in the 4 transistors 102 of one sub-word line driver 101 may be layered structure, that is, two dielectric layers of adjacent transistors 102 are spaced from each other, where any one dielectric layer only needs to be located between the gate 112 and the channel region of the transistor 102 corresponding to the dielectric layer.
In some embodiments, the dielectric layer of the transistor 102 in the sub-word line driver 101 is generally composed of a gate oxide layer, which is a silicon oxide insulating film formed by oxidizing a silicon substrate at a high temperature. In other embodiments, the material of the dielectric layer of the transistor may include silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or other high dielectric constant materials.
S102, a precharge command is provided for the memory, at least one sub word line driver 101 is precharged, and all sub word lines are in an off state.
Wherein, since all sub word lines are in the off state, the potential of all sub word lines is the same. The drains 132 of all transistors 102 in all sub-word line drivers 101 electrically connected to the sub-word line are thus at the same potential, so that the transistors 102 in the plurality of sub-word line drivers 101 can be controlled to be turned on or off by controlling the common gate 112 of the sub-word line driver 101.
It should be noted that, precharging at least one sub word line driver 101 by the precharge command may include the following three cases:
In some embodiments, the precharge command may be used to precharge one sub-word line driver 101, and since all the transistors 102 in the single sub-word line driver 101 share the gate 112, the gate 112 of all the transistors 102 in the single sub-word line driver 101 is at the same potential, and the drain 132 of all the transistors 102 in the single sub-word line driver 101 is at the same potential, which is beneficial to making the voltages across the dielectric layers of all the transistors 102 in the single sub-word line driver 101 uniform, thereby implementing the subsequent reliability evaluation of the dielectric layers of all the transistors 102 in the single sub-word line driver 101, i.e., the target dielectric layer.
In other embodiments, the precharge command may be used to precharge the plurality of sub-word line drivers 101, so that the common gates 112 of the plurality of sub-word line drivers 101 are controlled to have the same potential, and the drains 132 of all the transistors 102 of the plurality of sub-word line drivers 101 are controlled to have the same potential, so that the voltages across the dielectric layers of all the transistors 102 of the plurality of sub-word line drivers 101 are uniform, thereby realizing the subsequent reliability evaluation of the dielectric layers of all the transistors 102 of the plurality of sub-word line drivers 101, i.e., the target dielectric layer.
In still other embodiments, all sub-word line drivers 101 in the memory may be precharged by a precharge command, so that all common gates 112 in all sub-word line drivers 101 may be controlled to be at the same potential, and all drains 132 in all sub-word line drivers 101 may be controlled to be at the same potential, which is beneficial to make voltages across all dielectric layers of all transistors 102 in all sub-word line drivers 101 uniform, thereby enabling subsequent reliability evaluation of all dielectric layers of all transistors 102 in all sub-word line drivers 101, i.e., target dielectric layers.
In all of the above three cases of precharging the sub word line drivers 101, the operation characteristics of the memory itself are utilized, that is, at least one sub word line driver 101 is precharged in a precharge phase, so that all transistors in the at least one sub word line driver to be precharged are in an on state, and all sub word lines are in an off state in the precharge phase, thereby facilitating reliability evaluation of a dielectric layer in a single sub word line driver 101 to be precharged, or reliability evaluation of a plurality of dielectric layers in a plurality of sub word line drivers 101 to be precharged simultaneously.
In some embodiments, referring to fig. 3, in the case of precharging the sub word line drivers 101 in the above three cases, the memory may further include a plurality of main word lines 103, the plurality of main word lines 103 being electrically connected to the gates 112 of the plurality of sub word line drivers 101 in one-to-one correspondence, and at least one main word line 103 controlling at least one gate 112 to be at a first potential in the step of providing the precharge command to the memory. Note that the main word line 103 may extend through the memory cell array region, and thus, an electric signal may be applied to a predetermined number of main word lines 103 in the peripheral circuit, and then transferred to a predetermined number of gates 112 electrically connected to the main word lines 103 through the main word lines 103 to realize the precharge of a predetermined number of sub word line drivers 101. The predetermined number may be one or more, or may be the total number of all the sub word line drivers 101 in the corresponding memory.
The step of precharging at least one sub word line driver 101 may include two methods:
in some embodiments, in the step of precharging the at least one sub-word line driver 101, the gate 112 is at a first potential, the plurality of drains 132 are all at a second potential, and the second potential is lower than the first potential, and the first potential and the second potential are both constant values.
In practical applications, the transistor 102 may be an NMOS transistor, the first potential may be a voltage of an electrical signal applied to the gate 112 through the main word line 103, for example, 3V, the second potential may be 0V, and since the plurality of transistors 102 share the source 122, the source 122 may be grounded such that the source 122 is at a potential of 0V. Thus, by controlling the voltage of the electric signal applied to the gate 112 by the main word line 103, the voltage at two ends of the target dielectric layer can be known, no additional voltage detection equipment is needed to measure the voltage at two ends of the target dielectric layer, the voltage at two ends of the target dielectric layer is not interfered by the additional voltage detection equipment, and the accuracy of acquiring the voltage at two ends of the target dielectric layer is improved.
In addition, in practical application, the reliability of the dielectric layer can be evaluated for multiple times, and the first potential is different in magnitude in different evaluation steps. In this way, it is beneficial to compare the difference of the stability of the target dielectric layers in the same sub-word line driver 101 under different voltage conditions, and further can compare the difference of the electrical resistance and the failure time of the target dielectric layers in the same sub-word line driver 101 under different voltage conditions.
In other embodiments, in the step of precharging the at least one sub-word line driver 101, the gate 112 is at a first potential, the plurality of drains 132 are all at a second potential, and the second potential is lower than the first potential, and the magnitude of the first potential is gradually increased with the time of the precharging in any of the steps of precharging while the second potential is at a constant value.
It should be noted that, in practical applications, the transistor 102 may be an NMOS transistor, the first potential may be determined by an electrical signal applied to the gate 112 through the main word line 103, and by changing the electrical signal, the magnitude of the first potential is gradually increased with the duration of the precharge, for example, the first potential may be gradually changed from Vt to Vb, where Vt is the on threshold voltage of the transistor 102, and Vb is 80% of the breakdown voltage of the transistor 102, and in addition, the second potential may be 0V, and since the plurality of transistors 102 share the source 122, the source 122 may be grounded, so that the potential where the source 122 is located is 0V. Thus, by controlling the change of the electric signal applied to the gate 112 by the main word line 103, the change of the voltage at two ends of the target dielectric layer can be known, no additional voltage detection equipment is needed to measure the voltage at two ends of the target dielectric layer in real time, the voltage at two ends of the target dielectric layer is not interfered by the additional voltage detection equipment, and the accuracy of acquiring the voltage at two ends of the target dielectric layer is improved. In addition, in the process of the actual working of the target dielectric layer, the voltage at the two ends of the target dielectric layer may fluctuate, and in the evaluation method, the simulation of the actual working state of the target dielectric layer is facilitated by changing the first potential, so that the evaluation accuracy of the stability of the target dielectric layer is facilitated to be improved.
In addition, in practical application, the reliability of the dielectric layer may be evaluated multiple times, and in different evaluation steps, the magnitude of the first potential gradually increases with the duration of the precharge. In this way, it is beneficial to compare the difference of the stability of the target dielectric layers in the same sub-word line driver 101 under different voltage conditions, and further can compare the difference of the electrical resistance and the failure time of the target dielectric layers in the same sub-word line driver 101 under different voltage conditions.
S103, at least one sub word line driver undergoes at least one precharge, and the actual duration of each precharge is acquired in real time.
In some embodiments, in the step of providing the precharge command to the memory, if all the sub-word line drivers in the memory are precharged, all the sub-word line drivers 101 undergo at least one precharge at the same time, so as to obtain the actual duration of each precharge in real time, which is beneficial to the subsequent implementation of evaluating the reliability of the dielectric layer in all the sub-word line drivers 101 in the memory, i.e. the reliability evaluation of the dielectric layer of the entire memory.
In some embodiments, the step of acquiring the actual duration of each precharge in real time may further include acquiring a standby current of the memory in the step of each precharge in real time, where the standby current is a quiescent current when all memory cells in the memory are in an idle state in the step of precharging.
Since the dielectric layer has a change in its anti-electric property with the increase of the use time of the dielectric layer in the sub-word line driver 101, it affects not only the actual duration of the precharge but also the standby current of the memory. Therefore, the standby current of the memory in the precharge step is acquired, the reliability of the target dielectric layer is comprehensively analyzed based on the actual duration of the acquired precharge and the standby current of the memory, and the accuracy of the evaluation of the stability of the target dielectric layer is further improved.
In some embodiments, the memory further includes a first terminal for applying an operating voltage and a second terminal for grounding, and the step of acquiring the standby current in each of the precharging steps may include acquiring the current flowing from the first terminal through the second terminal in real time in the precharging step.
And S104, the dielectric layer in the sub word line driver 101 subjected to precharging is used as a target dielectric layer, and reliability evaluation of the target dielectric layer is realized based on the actual duration.
In some embodiments, in the step of providing the precharge command to the memory, if all the sub-word line drivers 101 in the memory are precharged, all the sub-word line drivers 101 undergo at least one precharge at the same time, the actual duration of each precharge is obtained in real time, so that the reliability evaluation of the target dielectric layer can be implemented based on the actual duration.
It should be noted that, as is apparent from the above description, the precharge command is used to precharge at least one sub-word line driver 101, and the target dielectric layer may be a dielectric layer of all transistors 102 in a single sub-word line driver 101, a plurality of dielectric layers of all transistors 102 in a plurality of sub-word line drivers 101, or all dielectric layers of all transistors 102 in all sub-word line drivers 101 in the memory.
In some embodiments, the step of evaluating the reliability of the target dielectric layer based on the actual time length includes determining, in real time, the actual time length and the maximum time length allowed to be experienced by the precharge, and if the actual time length is greater than the maximum time length, determining that the target dielectric layer fails. In other embodiments, if the actual time period is greater than or equal to the maximum time period, it may also be determined that the target dielectric layer is invalid. Wherein the maximum duration may be 18ns. In practical applications, the maximum duration allowed to be experienced by the precharge may be provided in the step of implementing the reliability evaluation of the target dielectric layer based on the actual duration, or may be provided in any step before the step of determining the magnitude of the actual duration and the maximum duration allowed to be experienced by the precharge, that is, the maximum duration is preset.
In some embodiments, the total working time of the memory, that is, the service life of the target dielectric layer, may be recorded while the target dielectric layer is determined to be invalid.
In some embodiments, the dielectric layer reliability evaluation method may further include determining, in real time, a standby current and a maximum standby current allowed to pass through the memory during precharge, and if the actual duration is less than or equal to the maximum duration and the standby current is greater than the maximum standby current, determining that the target dielectric layer fails. In practical applications, the maximum standby current may be provided after the actual time length and the maximum time length are determined in real time and before the failure of the target dielectric layer is determined, or may be provided in any step before the step of determining the standby current and the maximum standby current, that is, the maximum standby current is preset.
Since the dielectric layer has a change in its anti-electric property with the increase of the use time of the dielectric layer in the sub-word line driver 101, it affects not only the actual duration of the precharge but also the standby current of the memory. Thus, when there is an actual period of time that the precharge has experienced that is not greater than the maximum period of time, the standby current has become very large, such as greater than the maximum standby current, at which point the dielectric layer has failed. Therefore, if the actual duration is less than or equal to the maximum duration and the standby current is greater than the maximum standby current, the failure of the target dielectric layer is judged, so that the failure moment of the target dielectric layer can be accurately determined, and whether the target dielectric layer fails or not can be effectively determined.
In other embodiments, if the actual duration is less than or equal to the maximum duration and the standby current is greater than or equal to the maximum standby current, the target dielectric layer failure may be determined, or if the actual duration is less than the maximum duration and the standby current is greater than the maximum standby current, the target dielectric layer failure may be determined.
In some embodiments, the standby current obtained for the first time is taken as an initial standby current, and the ratio of the maximum standby current to the initial standby current is greater than or equal to 2.
In some embodiments, referring to fig. 5, T RP is the actual duration that each precharge experiences, and T is the running time of the memory, as can be seen from fig. 5, T RP tends to increase gradually with increasing running time of the memory, so that as the running time of the memory increases, the size of T RP gradually approaches the maximum duration that the precharge is allowed to experience. In addition, referring to fig. 6, I DD2P is the standby current of the memory in each precharge step, and T is the operation time of the memory, as can be seen from fig. 6, I DD2P has a tendency to gradually increase with the increase of the operation time of the memory, so as to gradually approach the maximum standby current allowed to pass through the memory when the precharge is performed with the increase of the operation time of the memory, I DD2P. As can be seen from fig. 5and 6, the reliability of the dielectric layer of the transistor 102 tends to gradually decline with the increase of the operation duration of the dielectric layer. In summary, by utilizing the operation characteristics of the memory, at least one sub-word line driver 101 is precharged in the precharge phase, so that all transistors 102 in the at least one sub-word line driver 101 are in an on state, and all sub-word lines are in an off state in the precharge phase, on one hand, if one sub-word line driver 101 is precharged, reliability evaluation can be performed on the dielectric layer, i.e., the target dielectric layer, of all transistors 102 in the single sub-word line driver 101, and on the other hand, in the precharge phase, precharge can be performed on the plurality of sub-word line drivers 101, and reliability evaluation can be performed on the plurality of dielectric layers in the plurality of sub-word line drivers 101 that are precharged. In addition, whether the electrical resistance of the target dielectric layer is reduced or not and whether the target dielectric layer fails or is broken down or not are judged based on the actual duration of the precharge experience, and the reliability evaluation of the target dielectric layer can be realized without additionally adding test equipment to measure the voltage at two ends of the target dielectric layer and the current flowing through the target dielectric layer.
The other embodiment of the disclosure also provides a test system for evaluating the reliability of the dielectric layer, which is used for realizing the reliability evaluation method of the dielectric layer. A test system for evaluating reliability of a dielectric layer according to another embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. Fig. 7 is a schematic functional block diagram of a test system for evaluating reliability of a dielectric layer according to another embodiment of the present disclosure.
Referring to fig. 7, the test system for evaluating reliability of a dielectric layer includes a memory 200 including a plurality of sub-word line drivers each including a plurality of transistors each including a gate, a source, a drain, and a dielectric layer, and a plurality of transistors sharing the gate and the source, the plurality of sub-word lines being electrically connected in one-to-one correspondence with the plurality of drains, a precharge module 201 configured to provide a precharge instruction to the memory, precharge at least one sub-word line driver, and all sub-word lines in an off state, an acquisition module 202 that performs at least one precharge during a memory cycle operation, the acquisition module configured to acquire an actual time period to which each precharge is performed in real time, and a judgment module 203 that performs reliability evaluation of the target dielectric layer based on the actual time period, the dielectric layer in the sub-word line drivers that performs the precharge being the target dielectric layer.
In some embodiments, the judging module 203 comprises a parameter setting module 213 configured to provide a maximum duration allowed to be experienced by the precharge, and a comparing module 223 configured to judge the actual duration and the maximum duration in real time, and judge that the target dielectric layer fails if the actual duration is greater than the maximum duration. In this way, the operating characteristics of the memory during the precharge phase can be utilized to indirectly obtain the failure time of the target dielectric layer based on the actual duration of the precharge experience.
In some embodiments, the acquisition module 202 may be further configured to acquire a standby current of the memory during the step of precharging, the standby current being a quiescent current of all memory cells in the memory while in an idle state during the step of precharging. Therefore, comprehensive analysis of the reliability of the target dielectric layer based on the acquired actual duration and standby current of the precharge is facilitated, and accuracy of evaluation of the stability of the target dielectric layer is facilitated to be improved.
In addition, the parameter setting module 213 may be further configured to provide a maximum standby current allowed to pass through the memory when the precharge is performed, and the comparison module 223 may be further configured to determine the standby current and the maximum standby current in real time, if the actual duration is less than or equal to the maximum duration and the standby current is greater than the maximum standby current, the target dielectric layer fails.
Since the dielectric layer has a change in its anti-electric property with the increase of the use time of the dielectric layer in the sub-word line driver 101, it affects not only the actual duration of the precharge but also the standby current of the memory. Thus, when there is an actual period of time that the precharge has experienced that is not greater than the maximum period of time, the standby current has become very large, such as greater than the maximum standby current, at which point the dielectric layer has failed. Therefore, if the actual duration is less than or equal to the maximum duration and the standby current is greater than the maximum standby current, the target dielectric layer is judged to fail, so that the failure moment of the target dielectric layer can be more accurately determined, and whether the target dielectric layer fails or not can be more effectively determined.
Among them, precharging at least one sub word line driver 101 may include two methods:
In some embodiments, in the step of precharging the at least one sub-word line driver 101, the gate 112 is at a first potential, the plurality of drains 132 are all at a second potential, and the second potential is lower than the first potential, the precharge module may be further configured to control both the first potential and the second potential to be constant values. Therefore, the change of the voltage at the two ends of the target medium layer can be known by controlling the first potential and the second potential, the voltage at the two ends of the target medium layer is not required to be measured in real time by additional voltage detection equipment, the voltage at the two ends of the target medium layer cannot be interfered by the additional voltage detection equipment, and the accuracy of acquiring the voltage at the two ends of the target medium layer is improved.
In other embodiments, in the step of precharging the at least one sub-word line driver 101, the gate 112 is at a first potential, the plurality of drains 132 are all at a second potential, and the second potential is lower than the first potential, and the precharge module may be further configured to control the magnitude of the first potential to gradually increase with the progress time of the precharge in any one of the steps of precharging while controlling the second potential to be a constant value. In the evaluation method, the simulation of the actual working state of the target medium layer is facilitated by changing the first potential, so that the accuracy of the stability evaluation of the target medium layer is facilitated.
In summary, the precharge module 201 is used to precharge at least one sub-word line driver 101, so that all transistors 102 in the at least one sub-word line driver 101 are in an on state, and in the precharge phase, all sub-word lines are in an off state, on one hand, the precharge module 201 may be used to precharge one sub-word line driver 101, and the acquisition module 202 and the determination module 203 may be used to perform reliability evaluation on the dielectric layer, i.e., the target dielectric layer, of all transistors 102 in the single sub-word line driver 101, and on the other hand, the precharge module 201 may be used to precharge a plurality of sub-word line drivers 101, and the acquisition module 202 and the determination module 203 may be used to perform reliability evaluation on a plurality of dielectric layers in the plurality of sub-word line drivers 101. In addition, based on the actual duration of the precharge experience, whether the electrical resistance of the target dielectric layer is reduced or not and whether the target dielectric layer fails or is broken down or not are judged, and the reliability evaluation of the target dielectric layer can be realized without additionally adding test equipment for measuring the voltage at two ends of the target dielectric layer and the current flowing through the target dielectric layer.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the disclosure, and the scope of the embodiments of the disclosure should be assessed accordingly to that of the appended claims.
Claims (14)
1. The dielectric layer reliability evaluation method is characterized by comprising the following steps of:
Providing a memory, wherein the memory comprises a plurality of sub word line drivers and a plurality of sub word lines, each sub word line driver comprises a plurality of transistors, each transistor comprises a grid electrode, a source electrode, a drain electrode and a dielectric layer, the grid electrode and the source electrode are shared by the transistors, and the sub word lines are electrically connected with the drain electrodes in a one-to-one correspondence manner;
Providing precharge instructions to the memory, precharging at least one of the sub-word line drivers, and all of the sub-word lines being in an off state;
At least one sub word line driver is subjected to at least one pre-charge, the actual duration of each pre-charge is obtained in real time, and the standby current of the memory in each pre-charge step is obtained in real time, wherein the standby current is the static current of all memory cells in the memory in the pre-charge step in an idle state;
The dielectric layer in the sub word line driver for the precharge is a target dielectric layer, reliability assessment on the target dielectric layer is achieved based on the actual duration, the reliability assessment comprises the steps of judging the magnitude of the actual duration and the maximum duration allowed to be experienced by the precharge in real time, judging that the target dielectric layer fails if the actual duration is longer than the maximum duration, judging the magnitude of the standby current and the maximum standby current allowed to pass through the memory in real time if the actual duration is shorter than or equal to the maximum duration, and judging that the target dielectric layer fails if the standby current is longer than the maximum standby current.
2. The method of evaluating claim 1, wherein the memory further comprises a first terminal for applying an operating voltage and a second terminal for grounding, and wherein the step of acquiring the standby current in each of the precharging steps comprises acquiring a current flowing from the first terminal through the second terminal in real time in the precharging step.
3. The evaluation method according to claim 1, wherein the standby current obtained for the first time is taken as an initial standby current, and a ratio of the maximum standby current to the initial standby current is 2 or more.
4. The evaluation method according to claim 1, wherein in the step of precharging at least one of the sub word line drivers, the gate is at a first potential, a plurality of the drains are each at a second potential, and the second potential is lower than the first potential, and the first potential and the second potential are each constant.
5. The method of evaluating according to claim 4, further comprising evaluating reliability of the dielectric layer a plurality of times, and in the step of different of the evaluations, the magnitudes of the first potentials are different.
6. The evaluation method according to claim 1, wherein in the step of precharging at least one of the sub word line drivers, the gate is at a first potential, a plurality of the drains are all at a second potential, and the second potential is lower than the first potential, and the magnitude of the first potential is gradually increased with the progress time of the precharge in any of the steps of precharging while the second potential is a constant value.
7. The evaluation method according to claim 6, further comprising evaluating reliability of the dielectric layer a plurality of times, and in the different evaluating steps, magnitudes of the first electric potential are different in a gradual increase in magnitude with an proceeding time of the precharge.
8. The evaluation method of claim 1, wherein each of said sub-word line drivers includes at least 4 of said transistors arranged in an array, and said common gate of a plurality of said transistors is in a ring-shaped configuration.
9. The evaluation method according to claim 1, wherein in the step of providing the precharge instruction to the memory, the precharge is performed to all of the sub word line drivers in the memory;
and simultaneously carrying out at least one time of pre-charging on all the sub word line drivers, acquiring the actual duration of each pre-charging, and realizing the reliability evaluation on the target dielectric layer based on the actual duration.
10. The evaluation method according to claim 1 or 9, wherein the memory includes a plurality of main word lines electrically connected to the gates of the plurality of sub-word line drivers in one-to-one correspondence, and wherein at least one of the main word lines controls at least one of the gates to be at a first potential in the step of providing the precharge command to the memory.
11. A test system for evaluating the reliability of a dielectric layer, comprising:
A memory including a plurality of sub word line drivers and a plurality of sub word lines, each sub word line driver including a plurality of transistors, each transistor including a gate, a source, a drain, and a dielectric layer, the plurality of transistors sharing the gate and the source, the plurality of sub word lines being electrically connected in one-to-one correspondence with the plurality of drains;
a precharge module configured to provide precharge instructions to the memory, precharge at least one of the sub-word line drivers, and all of the sub-word lines are in an off state;
The acquisition module is configured to acquire the actual duration of each precharge and acquire the standby current of the memory in real time in the precharge step, wherein the standby current is the static current of all memory cells in the memory in the idle state in the precharge step;
the judgment module is used for realizing reliability evaluation of the target dielectric layer based on the actual duration, and comprises a parameter setting module and a data processing module, wherein the parameter setting module is used for providing the maximum duration allowed to be experienced by the precharging;
And the comparison module is configured to judge the actual time length and the maximum time length in real time, and judge that the target medium layer fails if the actual time length is longer than the maximum time length.
12. The test system of claim 11, wherein the parameter setting module is further configured to provide a maximum standby current allowed to pass by the memory when the pre-charging is performed, and wherein the comparison module is further configured to determine the standby current and the maximum standby current in real time, and determine that the target dielectric layer fails if the actual duration is less than or equal to the maximum duration and the standby current is greater than the maximum standby current.
13. The test system of claim 11, wherein in the step of precharging at least one of the sub-word line drivers, the gate is at a first potential, a plurality of the drains are each at a second potential, and the second potential is lower than the first potential, the precharge module is further configured to control both the first potential and the second potential to be constant values.
14. The test system of claim 11, wherein in the step of precharging at least one of the sub-word line drivers, the gate is at a first potential, a plurality of the drains are all at a second potential, and the second potential is lower than the first potential, the precharge module is further configured to control the magnitude of the first potential to gradually increase with an proceeding time of the precharge while controlling the second potential to be a constant value.
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| CN109166842A (en) * | 2018-08-27 | 2019-01-08 | 长江存储科技有限责任公司 | For assessing the test structure and test method of grid oxide layer TDDB polarity difference |
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| CN109166842A (en) * | 2018-08-27 | 2019-01-08 | 长江存储科技有限责任公司 | For assessing the test structure and test method of grid oxide layer TDDB polarity difference |
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