CN116541340B

CN116541340B - Peripheral interconnection device, processor and system on chip

Info

Publication number: CN116541340B
Application number: CN202310791645.0A
Authority: CN
Inventors: 岳阳; 刘征宇; 林韬
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2023-06-30
Filing date: 2023-06-30
Publication date: 2024-03-22
Anticipated expiration: 2043-06-30
Also published as: CN116541340A

Abstract

The embodiment of the invention provides a peripheral interconnection device, a processor and a system-on-chip, wherein the peripheral interconnection device is applied to the system-on-chip comprising at least two peripheral devices, and the device comprises: the dynamic peripheral interface matrix network is used for receiving communication signals generated by the at least two peripheral devices and distributing the communication signals to different channels according to channel configuration information; at least two dynamic peripheral interface matrix overwrites, wherein each peripheral is provided with the corresponding dynamic peripheral interface matrix overwrites, and the dynamic peripheral interface matrix overwrites are used for enabling the peripheral subscribed to the channel to execute the task corresponding to the communication signal sent by the dynamic peripheral interface matrix network according to the channel subscription information; the channel configuration information, the channel subscription information, and the tasks are pre-configured by a controller.

Description

Peripheral interconnection device, processor and system on chip

Technical Field

The embodiment of the invention relates to the technical field of peripheral interconnection, in particular to a peripheral interconnection device, a processor and a system on a chip.

Background

The peripheral devices in the chip are mutually independent, work of the peripheral devices is required to be scheduled and coordinated through a controller (such as a CPU (Central processing Unit), an MCU (micro control Unit) and the like), the controller is communicated with the peripheral devices through interrupt and read-write registers (for example, one task is required to be completed together by the peripheral device A and the peripheral device B, information cannot be fully exchanged between the peripheral device A and the peripheral device B directly in many cases, and the tasks are required to be completed through communication with the controller respectively). This approach takes up controller resources and consumes higher power. Meanwhile, because the time consumption of each response of the controller is inconsistent, the time consumption of each communication among the peripheral devices through the controller is inconsistent, and the application sensitive to the stability of some communication time is not friendly.

Therefore, how to reduce the dependence of the interconnection communication between the peripheral devices on the controller is a technical problem to be solved in the prior art.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a peripheral interconnection device, a processor and a system-on-chip to at least partially solve the above-mentioned problems.

According to a first aspect of an embodiment of the present invention, there is provided a peripheral interconnection apparatus applied to a system on a chip including at least two peripheral devices, the apparatus including: the dynamic peripheral interface matrix network is used for receiving communication signals generated by the at least two peripheral devices and distributing the communication signals to different channels according to channel configuration information; at least two dynamic peripheral interface matrix overwrites, wherein each peripheral is provided with the corresponding dynamic peripheral interface matrix overwrites, and the dynamic peripheral interface matrix overwrites are used for enabling the peripheral subscribed to the channel to execute the task corresponding to the communication signal sent by the dynamic peripheral interface matrix network according to the channel subscription information; the channel configuration information, the channel subscription information, and the tasks are pre-configured by a controller.

In another implementation of the present invention, the channel configuration information, the channel subscription information, and the tasks are pre-configured by the controller through software.

In another implementation of the present invention, the channel configuration information is sent by the controller to the dynamic peripheral interface matrix network through a dynamic peripheral interface matrix register; and the channel subscription information and the task are sent to the dynamic peripheral interface matrix outer cladding layer by the controller through the dynamic peripheral interface matrix register.

In another implementation of the present invention, the dynamic peripheral interface matrix register is connected to the controller through a system bus; the dynamic peripheral interface matrix register is connected with the dynamic peripheral interface matrix network and the dynamic peripheral interface matrix register is connected with the dynamic peripheral interface matrix outer cladding layer through a local connecting line.

In another implementation of the present invention, each of the dynamic peripheral interface matrix overwrites is disposed inside the peripheral corresponding thereto; or, the at least two dynamic peripheral interface matrix overwraps are centrally disposed within any one of the peripheral devices; or, the at least two dynamic peripheral interface matrix overwrites are centrally disposed outside the peripheral.

In another implementation of the present invention, the dynamic peripheral interface matrix network includes: a selection logic port, configured to receive communication signals generated by the at least two peripheral devices, and select the received communication signals according to the channel configuration information, so as to transmit the selected communication signals; the communication signal synchronous pulse module is used for receiving the communication signal and converting the communication signal into a pulse signal with uniform pulse width; and the matrix network is used for receiving the pulse signals with the uniform pulse width and transmitting the pulse signals with the uniform pulse width to the channel selected according to the channel configuration information.

In another implementation of the present invention, the dynamic peripheral interface matrix network further includes: and the pulse expansion module is used for carrying out pulse signal broadening on the pulse signals with uniform pulse width received by each channel so as to send the pulse signals after the pulse broadening to the channel selected according to the channel configuration information.

In another implementation of the present invention, the selection logic port includes a plurality of ports and a selector, at least one port selecting at least two of the communication signals received through the selector according to the channel configuration information; the at least two communication signals are generated by the same said peripheral or by at least two different said peripherals, respectively.

In another implementation of the present invention, the dynamic peripheral interface matrix network further includes: and the interrupt generation module is used for generating an interrupt instruction and sending the interrupt instruction to the controller to inform the controller that the communication signal is received by the selection logic port when the communication signal is received by the selection logic port.

In another implementation of the present invention, the dynamic peripheral interface matrix outer cladding includes: the communication signal decoder is used for acquiring a communication signal sent to the subscribed channel by the dynamic peripheral interface matrix network according to the channel subscription information; the task engine is used for obtaining a task corresponding to the communication signal according to the communication signal obtained by the communication signal decoder, so that the peripheral equipment executes the task; and the communication signal generation module is used for enabling the communication signals generated by the peripheral to be sent to the dynamic peripheral interface matrix network.

In another implementation manner of the present invention, the communication signal decoder is further configured to obtain a start address and an end address of a task corresponding to the communication signal in an instruction table, where the instruction table is used to store instructions corresponding to each task, and the start address and the end address are used to indicate an instruction to start execution and an instruction to end execution corresponding to the task; the task engine is specifically configured to: obtaining instructions corresponding to the starting address and the ending address from an instruction table according to the starting address and the ending address; and decoding the instruction, and configuring a peripheral register according to the decoded instruction so as to control the peripheral to realize the function corresponding to the task.

In another implementation of the invention, the instruction table is stored in a dynamic peripheral interface matrix control register or in a peripheral static memory comprised by the dynamic peripheral interface matrix wrapper.

In another implementation of the invention, the depth of the instruction table and the bit width of the stored instructions are set by the dynamic peripheral interface matrix control register or the peripheral's static memory.

In another implementation of the present invention, when the dynamic peripheral interface matrix network sends the communication signal through the channel, the task engine of the dynamic peripheral interface matrix wrapper obtains the control right of the peripheral register; otherwise, the controller obtains the control right of the peripheral register.

In another implementation of the present invention, the dynamic peripheral interface matrix wrapper shares control of the peripheral registers with the controller through a multiplexer.

In another implementation of the present invention, the task engine is mounted on a universal bus interface through a universal bus protocol conversion module; when the task engine of the dynamic peripheral interface matrix outer cladding obtains the control right of the peripheral register, the universal bus protocol conversion module selects a first bus to be connected with the peripheral register; when the controller obtains the control right of the peripheral register, the universal bus protocol conversion module selects a second bus to be connected with the peripheral register, the first bus is different from the second bus, the first bus is an advanced peripheral bus, and the second bus is an advanced high-performance bus.

In another implementation of the present invention, the instruction table supports five instructions: a write register command, a bit segment write register command, a delay wait command, a compare decision command, and a bit segment compare decision command.

In another implementation manner of the present invention, the communication signal decoder is further configured to receive a short triggering instruction sent by the peripheral, where the short triggering instruction is to enable the peripheral to implement a corresponding function according to triggering of the peripheral, the short triggering instruction includes one of an interrupt, a communication signal, or an indication signal generated by the peripheral, and the communication signal decoder sends a start address and an end address of the short triggering instruction to the task engine.

In another implementation manner of the present invention, the communication signal decoder is further configured to receive a task termination instruction, where the task termination instruction is a task that is currently executed and when the task is interrupted, cause the task engine to execute a next task or continue to execute the interrupted task.

In another implementation of the present invention, the communication signal decoder includes: the network signal module is used for receiving the communication signals of the reservation channel, carrying out AND processing and bit pressing or processing on the register of each task after the processing of the synchronization unit and the inverting, obtaining an output result, and generating a network execution signal for the output result after detecting the rising edge or the falling edge of the output result; the short trigger signal module receives the communication signals, performs bit pressing or processing after synchronous processing and respectively follows the inverted registers of each task to obtain an output result, and generates a short trigger execution signal for the output result after detecting a rising edge or a falling edge of the output result; and the task termination module receives the termination communication signal, and generates a termination execution signal after the output result detects a rising edge or a falling edge after the synchronization processing and the enabling register phase of the task termination function.

In another implementation of the present invention, the communication signal decoder includes: the network signal module is used for receiving the communication signals of the reservation channel, carrying out AND processing and bit pressing or processing on the register of each task after the processing of the synchronization unit, obtaining an output result, and if the task engine detects a rising edge or a falling edge on the output result, generating a network execution signal on the output result or the output result, and in addition, the output result is used as a selection signal of the multiplexer to select and send out corresponding task starting and ending addresses; the short trigger signal module receives the communication signals, performs bit pressing or processing after synchronization processing and respectively follows the inverted registers of each task to obtain an output result, and generates a short trigger execution signal for the output result if the task engine detects a rising edge or a falling edge of the output result, and in addition, the output result is also used as a selection signal of a multiplexer to select corresponding task starting and ending addresses to send; and the task termination module receives the termination communication signal, and generates a termination execution signal after synchronous processing and after the enabling register phase of the task termination function, if the task engine detects a rising edge or a falling edge on the output result.

According to a second aspect of an embodiment of the present invention, there is provided a processor including: a processor core; and, the above-mentioned peripheral interconnection device; the processor core comprises a controller, the controller is used for controlling the peripheral equipment, and the peripheral equipment interconnection device is used for realizing interconnection of the peripheral equipment according to the preset of the controller.

According to a third aspect of an embodiment of the present invention, there is provided a system on a chip, including: the system comprises a plurality of processors and at least two peripheral devices, wherein the processors are the processors.

In the solution of the embodiment of the present application, the dynamic peripheral interface matrix network of the embodiment of the present application receives the communication signals generated by the at least two peripheral devices, and distributes the communication signals to different channels according to channel configuration information, each peripheral device has a dynamic peripheral interface matrix outer cladding layer corresponding to the peripheral device, and according to channel subscription information, the peripheral devices subscribing to the channels execute tasks corresponding to the communication signals, where the channel configuration information, the channel subscription information, and the tasks are configured in advance by the controller. In the process of interconnection of the peripheral devices, the controller can realize interconnection of the peripheral devices and realize any function of the peripheral devices only by configuring channel configuration information, channel subscription information and tasks.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present invention, and other drawings may be obtained according to these drawings for a person having ordinary skill in the art.

Fig. 1 is a schematic diagram of a DPPI solution.

Fig. 2 is a schematic diagram of a DPPI solution peripheral task.

FIG. 3 is a schematic diagram of the task of a DPIM solution peripheral device in accordance with an embodiment of the present invention.

Fig. 4 is a schematic diagram of a peripheral interconnection device according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of a specific application scenario of the peripheral interconnection device according to the embodiment of the present invention.

Fig. 6 is a schematic diagram of a dynamic peripheral interface matrix network of a peripheral interconnect device according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a dynamic peripheral interface matrix outer wrapper of a peripheral interconnect device according to an embodiment of the present invention.

Fig. 8 is a schematic diagram of an instruction format stored in an instruction table of the peripheral interconnection device according to an embodiment of the present invention.

Fig. 9 is a schematic diagram of an instruction table of a peripheral interconnection apparatus according to an embodiment of the present invention.

Fig. 10 is a schematic diagram of a task engine of the peripheral interconnection device according to an embodiment of the present invention taking a finger from an instruction table.

Fig. 11 is a schematic diagram of a workflow of a task engine internal state machine of a peripheral interconnect device according to an embodiment of the present invention.

Fig. 12 is a schematic block diagram of a communication signal decoder of a peripheral interconnection device according to an embodiment of the present invention.

Fig. 13 is a schematic diagram of a network signal module of a communication signal decoder of a peripheral interconnection device according to an embodiment of the present invention.

Fig. 14 is a schematic diagram of a short trigger signal module of a communication signal decoder of a peripheral interconnection device according to an embodiment of the present invention.

Fig. 15 is a schematic diagram of a task termination module of a communication signal decoder of a peripheral interconnection device according to an embodiment of the present invention.

Fig. 16 is a block diagram of a processor according to another embodiment of the invention.

Fig. 17 is a schematic diagram of a system-on-chip according to another embodiment of the present invention.

Detailed Description

In order to make the technical solutions in the embodiments of the present invention better understood by those skilled in the art, the technical solutions in the embodiments of the present invention will be clearly and specifically described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the present invention, shall fall within the scope of protection of the embodiments of the present invention.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and which illustrate exemplary embodiments. In addition, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that the directions and references (e.g., upper, lower, top, bottom, etc.) may be used merely to facilitate the description of the features in the drawings. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and equivalents thereof.

In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art that the embodiments herein may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments herein. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment herein. Thus, the appearances of the phrases "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment in any event that particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe a functional or structural relationship between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "coupled" may be used to indicate that two or more elements are in direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that two or more elements co-operate or interact with each other (e.g., as in a causal relationship).

The terms "above …," "below …," "between …," and "on …" as used herein refer to the relative position of one component or material with respect to other components or materials, wherein such physical relationships are notable. For example, in the context of materials, one material or materials disposed above or below another material may be in direct contact, or may have one or more intermediate materials. Also, one material disposed between two materials or materials may be in direct contact with both layers or may have one or more intermediate layers. In contrast, a first material or material "on" a second material or material is in direct contact with the second material/material. Similar distinction is made in the context of assembly of components.

As used throughout this description and in the claims, a list of items connected by the term "at least one of" or "one or more of" may mean any combination of the listed items. For example, the phrase "at least one of A, B or C" can mean a; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; or A, B and C.

The term "circuit" or "module" may refer to one or more passive and/or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, or magnetic signal. The terms "substantially," "near," "approximately," "near," and "approximately" generally refer to within +/-10% of a target value.

To reduce the reliance on the controller for interconnect communication between peripherals, a DPPI (Dynamic Programmable Peripheral Interconnect) solution is proposed. Referring to fig. 1, the DPPI solution publishes communication Signals (EVENTs) originally intended for communication with a controller in each peripheral into the DPPI network. The network is composed of a plurality of channels (channels), and each peripheral device transmits communication signals to different channels according to channel configuration information. Meanwhile, each peripheral device can subscribe communication signals on different channels according to the channel subscription information, and execute different TASKs (TASK) according to the received communication signals. The channel configuration information and the channel subscription information may be configured by registers.

The DPPI solution requires no controller involvement and the communication latency is fixed. The controller only needs to complete the configuration of the communication signal release in advance, namely the configuration of which channels each peripheral communication signal is sent to, and the configuration of channel subscription, namely the configuration of which channels each peripheral receives the communication signals of.

However, in DPPI solutions, the tasks that the peripheral can perform are hardware circuits that are encapsulated in the chip design phase, and the kinds of tasks that the peripheral can perform are fixed and simple, lacking in flexibility.

Referring to fig. 2, since the tasks executable by the peripheral devices are completed by the hardware circuit design, the number of tasks executable by each peripheral device is fixed, the task content is also preset, and these tasks are implemented in hardware and cannot be changed. The user can only select among these preset contents to configure use in the DPPI network. In the using process, the user cannot customize the required tasks. If a more complex task is added in the design stage, the problems of overlarge newly added area, increased design complexity and the like are brought. If a new peripheral is to be added, a new task circuit is designed according to the type and the use scene of the peripheral, and the task circuit cannot be simply integrated and commonly used. And, when a certain peripheral is executing a certain task, if another task is triggered to be executed, the internal state of the peripheral may be confused.

The embodiment of the application provides a dynamic peripheral interface matrix (Dynamic Peripheral Interface Matrix, DPIM) solution which can be applied to a general system on chip (soc), a controller is not needed to participate in the peripheral interconnection process, the controller only needs to pre-configure channel configuration information, channel subscription information and tasks, and any one or more functions of the peripheral can be realized. The controller of the embodiment of the application not only configures the channel configuration information and the channel subscription information through software, but also realizes the number of the executable tasks of the peripheral equipment and the content of the tasks through software configuration.

Referring to fig. 3, the controller of the present application pre-configures channel configuration information, channel subscription information, and tasks, so that mutually independent peripherals can cooperate.

The implementation of the embodiments of the present invention will be further described below with reference to the accompanying drawings.

Referring to fig. 4, an embodiment of the present application provides a peripheral interconnection device, which is applied to a system on a chip including at least two peripheral devices, and the device includes:

a dynamic peripheral interface matrix Network (dpim_network) 31 for receiving communication signals generated by at least two peripheral devices (peripheral device 1, peripheral device 2, peripheral device 3) and for distributing the communication signals to different channels according to the channel configuration information.

At least two dynamic Peripheral interface matrix overwrites (DPIM_peripheral_wrapper) 32, wherein the dynamic Peripheral interface matrix overwrites 32 are in one-to-one correspondence with the Peripheral devices, and the dynamic Peripheral interface matrix overwrites 32 are configured to enable the Peripheral devices subscribed to the channel to execute tasks corresponding to communication signals sent by the dynamic Peripheral interface matrix network 31 according to the channel subscription information.

Referring specifically to fig. 4, the dynamic peripheral interface matrix network 31 is connected to three dynamic peripheral interface matrix overwrites 32 corresponding to the peripheral 1, the peripheral 2, and the peripheral 3 respectively through thin lines.

Specifically, the channel configuration information, the channel subscription information, and the tasks are configured in advance by the controller through software. The controller pre-configures the channel configuration information, the channel subscription information and the tasks through software, so that a user can customize the required tasks in the use process without re-designing the chip. The newly added task does not increase the chip area, and is convenient for reconfiguring the task of the peripheral according to the type of the peripheral and the use scene.

The implementation of the embodiment of the application is described in detail below through an application scenario.

Fig. 5 is a typical scenario where an analog-to-digital converter (Analog to Digital Converter, ADC), timer (timer), universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART), direct memory access (Direct Memory Access, DMA), and four peripherals work cooperatively. First, the controller performs channel configuration information, channel subscription information, and task execution software pre-configuration. When the timer times out, a timeout communication signal (EVENT) is generated. The dynamic peripheral interface matrix network 31 receives the timeout communication signals and distributes the timeout communication signals to different channels according to the channel configuration information. The corresponding dynamic peripheral interface matrix outer cladding 31 of the analog-to-digital converter receives the overtime communication signal according to the channel subscription information, and executes the corresponding data acquisition task. After the task of acquiring data by the analog-to-digital converter is completed, an acquired data completion communication signal is generated, the dynamic peripheral interface matrix network 31 receives the acquired data completion communication signal, and the acquired data completion communication signal is distributed to different channels according to the channel configuration information. The direct memory access corresponding dynamic peripheral interface matrix wrapper 32 receives the collected data according to the channel subscription information to complete the communication signal, and performs the corresponding data handling to the memory task. After the transfer data to memory task is completed, a transfer data to memory completion communication signal is generated, and the dynamic peripheral interface matrix network 31 receives the transfer data to memory completion communication signal and distributes the transfer data to memory completion communication signal to different channels according to the channel configuration information. The dynamic peripheral interface matrix wrapper 32 corresponding to the universal asynchronous receiver/transmitter receives the handling data to the memory according to the channel subscription information to complete the communication signal, and performs the print information task. After the print information task is completed, a print information completion communication signal is generated, and the dynamic peripheral interface matrix network 31 receives the print information completion communication signal and distributes the print information completion communication signal to different channels according to the channel configuration information. The corresponding dynamic peripheral interface matrix wrapper 32 of the timer receives the print information to complete the communication signal according to the channel subscription information, performs the corresponding restart count task, and then loops the workflow. In this workflow, the controller only pre-configures channel configuration information, channel subscription information, and tasks. Illustratively, the tasks of the peripheral include: the timeout time of the timer, the sampling rate of the analog-to-digital converter, the source and destination addresses of the direct memory access, the baud rate of the universal asynchronous receiver-transmitter, etc.

Taking the scenario of fig. 2 as an example, when the task of directly accessing the memory to transfer data to the memory is completed, the universal asynchronous receiver-transmitter performs the task of printing information, and the task automatically performed by the universal asynchronous receiver-transmitter is only a simple action of "turning on print enable"; but taking the scenario of fig. 3 as an example, the tasks of "modify baud rate", "set print content", "set print length", "wait 5ms", "turn on print enable" universal asynchronous receiver are software programmable, with great flexibility.

The embodiment of the application can be applied to all systems with controllers, buses and peripherals, such as wireless communication systems, household appliances and the like. The embodiment of the application can also be applied to a system without a controller, and the system can directly configure channel configuration information, channel subscription information and tasks through an external interface by adopting the external controller. The controller in the embodiment of the present application may be an external controller that exists in a system on chip applied in the embodiment of the present application, or connected to the system on chip, which is not limited in the embodiment of the present application.

Specifically, the dynamic peripheral interface matrix network 31 is responsible for collecting communication signals generated by all peripheral devices, distributing the communication signals to different channels according to channel configuration information by using a decoding rule configured by software, so that the peripheral devices subscribed to the channels can receive the communication signals, and complete tasks.

The dynamic peripheral interface matrix outer cladding 32 is responsible for receiving the communication signals forwarded by the dynamic peripheral interface matrix network 31 according to the channel subscription information, and triggering the peripheral to execute tasks corresponding to the communication signals. Each peripheral is associated with a dynamic peripheral interface matrix wrapper 32.

The peripheral devices are physically connected to the controller via a system bus, but may be programmatically disconnected. The software may not require the controller to directly access the peripheral, and the controller may directly control the peripheral when the controller is idle.

Specifically, the dynamic peripheral interface matrix network 31 and the dynamic peripheral interface matrix wrapper 32 are not mounted on the System bus (System bus), and the controller can only access the dynamic peripheral interface matrix network 31 and the dynamic peripheral interface matrix wrapper 32 by configuring the dynamic peripheral interface matrix registers 33. The dynamic peripheral interface matrix network 31 and the dynamic peripheral interface matrix wrapper 32 are not directly connected to the system bus, so the controller cannot directly access both modules, but can only indirectly control them by configuring the dynamic peripheral interface matrix registers 33. The dynamic peripheral interface matrix register 33 is connected with the controller through a System bus, so that the accuracy of the pre-configuration of the dynamic peripheral interface matrix register 33 is ensured.

The dynamic peripheral interface matrix overwrites 32 and the peripheral devices (peripheral device 1, peripheral device 2, peripheral device 3) may interact using a Local wired connection, and the dynamic peripheral interface matrix registers 33 and the dynamic peripheral interface matrix overwrites 32 are connected using a Local wired connection (Local bus). The connection does not need to pass through a bus, so that the real-time performance of task execution is ensured. The controller controls the peripheral equipment through the system bus, the controller configures channel configuration information, channel subscription information and tasks to the dynamic peripheral equipment interface matrix register 33 through the system bus, and the dynamic peripheral equipment interface matrix network 31 obtains the channel configuration information from the dynamic peripheral equipment interface matrix register 33 through a local connection; the dynamic peripheral interface matrix wrapper 32 obtains channel subscription information and tasks from the dynamic peripheral interface matrix registers 33 via local wiring.

Each dynamic peripheral interface matrix wrapper 32 is disposed within a corresponding peripheral; alternatively, at least two dynamic peripheral interface matrix overwraps 32 are centrally disposed within the interior of either peripheral; or at least two dynamic peripheral interface matrix overwrites 32 are centrally disposed on the outside of the peripheral. The embodiment of fig. 4 is illustrated with each dynamic peripheral interface matrix wrapper 32 disposed within a corresponding peripheral.

The dynamic peripheral interface matrix outer cladding 32 can be set according to the requirement, and the setting mode is more flexible.

Referring to fig. 4, implementation of the embodiments of the present application is further illustrated by way of a workflow.

Data stream (1): the controller configures the channel configuration information, channel subscription information, and tasks to the dynamic peripheral interface matrix register 33 via the system bus.

The tasks executed by the peripheral devices are all configured by the controller through the data stream (1).

Data stream (2): the configuration of the dynamic peripheral interface matrix register 33 is completed, and the channel configuration information is directly sent to the dynamic peripheral interface matrix network 31 through a local connection; the channel subscription information and tasks are fed directly into the dynamic peripheral interface matrix wrapper 32 through local wiring.

The data stream (1) is realized by means of a system bus, which is a protocol, signalling according to the regulations and timing, all peripherals being suspended from the bus.

The data stream (2) is realized by a local connection. The local connection is a signal line, which is intended to pass a signal from one point to another.

Data stream (3): the first peripheral 1 generates a certain communication signal which is fed into the dynamic peripheral interface matrix network 31.

Data stream (4): the dynamic peripheral interface matrix network 31 transmits the communication signal to the peripheral subscribed to the corresponding channel according to the channel configuration information.

The communication signal generated by the second peripheral 2 is transferred to the peripheral subscribed to the corresponding channel through the dynamic peripheral interface matrix network 31 to trigger the peripheral subscribed to the corresponding channel to perform tasks.

Referring specifically to fig. 5, the timer generates a timeout communication signal that is communicated via the dynamic peripheral interface matrix network 31 to a peripheral subscribed to the corresponding channel, such as an analog-to-digital converter that begins performing the task of collecting data.

Data stream (5): the first peripheral 1 receives the communication signal of the relevant channel subscribed by itself and starts to execute the task pre-configured in the data stream (1).

Tasks may be, for example, transferring data over a bus (such as DMA) or interacting with other peripherals.

In a specific implementation of the embodiment of the present application, referring to fig. 6, the dynamic peripheral interface matrix network 31 includes:

the selection logic port 311 is configured to receive communication signals generated by at least two peripheral devices, and select the received communication signals according to channel configuration information, so as to transmit the selected communication signals.

Specifically, the selection logic PORT 311 includes a plurality of PORTs (ports_0 to 31) and a selector. This application takes only 32 PORTs as an example. The SOURCE terminals SOURCE_0-N indicate that there are multiple communication signals in the system, and each communication signal is sent to any PORT (PORT) as a SOURCE terminal. The at least one PORT selects the received at least two communication signals through the selector according to the channel configuration information. At least two communication signals are generated by the same peripheral or by at least two different peripheral devices, respectively.

Illustratively, the selection logic port 311 may send a plurality of communication signals generated by one peripheral or a plurality of communication signals generated by a plurality of different peripheral to any one or more channels according to the channel configuration information, where 32 channels are shown as an example, ch 0-31 (i.e., 32 channels shown in the matrix network 313 in the figure). The signal of port_1 in fig. 6 is sent to ch1, ch3, and ch30 at the same time; the signal of port_5 is sent only to ch2; the signals of port_3 and port_5 are sent to ch2.

A communication signal synchronization pulse module (evt_sync_pulse) 312 for receiving the communication signal and converting the communication signal into a pulse signal of uniform pulse width.

A matrix network (dpim_network) 313 for receiving pulse signals of uniform pulse width and transmitting the pulse signals of uniform pulse width to channels selected by the channel configuration information.

Illustratively, the matrix network 313 is composed of 32 channels and lines corresponding to 32 PORTs port_0-31. Each channel corresponds to each vertical line in the graph; each PORT corresponds to each horizontal line in the figure. A certain black dot indicates that a signal in a certain PORT is sent to a certain channel, for example, a signal of PORT1 in fig. 6 is sent to ch1, ch3, and ch 30. A certain white point indicates that a signal in a certain PORT is not sent to a certain channel, e.g., a signal in PORT0 in fig. 6 is not sent to any one channel.

And a pulse expansion module (pulse_expansion_ch0-31) 314, configured to expand the pulse signal of the uniform pulse width received by each channel, so as to send the pulse signal after pulse expansion to the channel selected according to the channel configuration information. Taking 32 channels as an example, pulse_expansion_ch0-31 widens pulse signals and sends the pulse signals out of the dynamic peripheral interface matrix network 31 to each peripheral. The pulses are stretched to match the different sampling clock frequencies of the different peripherals.

An interrupt generation module (int_gen) 315 is configured to generate an interrupt instruction and send the interrupt instruction to the controller to notify the controller that the select logic port 311 receives the communication signal. The controller obtains the communication signal sent by the selection logic port according to the interrupt instruction, and the software in the controller can know that the related communication signal is generated.

Referring to fig. 6, the implementation of the dynamic peripheral interface matrix network 31 of the embodiments of the present application is further illustrated by way of a workflow.

The dynamic peripheral interface matrix network 31 supports a plurality of signal sources and channels, N signal sources and 32 channels in fig. 6 are only examples. The signal source end is connected with communication signals generated by each peripheral, and N paths of signal source ends are distributed to 32 PORTs PORT_0-31 through channel configuration information in a dynamic peripheral interface matrix register 33. Through synchronization, the dynamic peripheral interface matrix network 31 distributes the channels ch 0-31.

The communication signal is a message and is physically a signal line, for example, the peripherals 1 to 10 can generate 100 different communication signals in total, and then a total of 100 signal lines are connected to the signal source (n=99 in fig. 6 at this time), so the signal source is just a port of the dynamic peripheral interface matrix network 31, and the signal line can transmit an input signal with a width of 100 bits. And the communication signal is the output signal of the peripheral device, and the bit width is 100 bits.

The dynamic peripheral interface matrix network 31 of the embodiment of the present application has the following characteristics:

different signal source ends can trigger different target peripheral devices to execute corresponding tasks through the dynamic peripheral device interface matrix network 31, different peripheral devices are mutually independent, and different peripheral device execution tasks can be concurrent. For example, in fig. 6, the PORT2 corresponding signal source triggers the peripheral subscribed to ch31 to execute the corresponding task, and at the same time, the PORT3 corresponding signal source triggers the peripheral subscribed to ch2 to execute the corresponding task.

The embodiment of the application overcomes the defect that the prior art only supports that different signal source ends generated by the same peripheral are bound to one channel, and different tasks are triggered through the channel. The embodiment of the application supports that any signal source end is bound to one channel, whether or not the signal source end is generated by the same peripheral equipment. For example, peripheral 1 generates source 1-3, peripheral 2 generates source 4-8, and embodiments of the present application may select source1, 3, 5 to bind to ch0; source2, 4, 6, 7, 8 is bound to ch 1. However, the prior art only supports source1, 3 binding to ch0, source5 binding to ch1, source4, 8 binding to ch2, and source5, 6, 7 binding to ch3.

The same signal source terminal can trigger different channel connected target peripheral devices to execute corresponding tasks through the dynamic peripheral device interface matrix network, the different peripheral devices are mutually independent, and the execution tasks of the different peripheral devices can be concurrent. For example, the corresponding signal source terminal of PORT1 in fig. 6 triggers the peripheral devices subscribing to channels ch1, ch3, and ch30 to execute the corresponding tasks.

Different signal source ends can trigger a target peripheral connected with the same channel to execute a plurality of corresponding tasks through the dynamic peripheral interface matrix network, and the plurality of tasks of the target peripheral connected with the same channel cannot be concurrent, so that the plurality of tasks need to be executed in series. For example, in fig. 6, the signal source corresponding to PORT3 and the signal source corresponding to PORT5 may trigger the tasks corresponding to the peripheral subscribed to ch2, and then the tasks need to be executed in series, i.e. any of the signal source is pulled up, and the channel will send a pulse to the peripheral subscribed to the channel.

In a specific implementation of this embodiment of the present application, referring to fig. 7, the dynamic peripheral interface matrix outer cladding 32 includes:

the communication signal decoder 321 is configured to obtain, according to the channel subscription information, a communication signal sent by the dynamic peripheral interface matrix network 31 to the subscribed channel.

The task engine 322 is configured to obtain a task corresponding to the communication signal according to the communication signal obtained by the communication signal decoder 321, and make the peripheral device execute the corresponding task.

The communication signal generating module 323 is configured to enable the communication signal generated by the peripheral to be sent to the dynamic peripheral interface matrix network 31.

According to the embodiment of the application, the dynamic peripheral interface matrix outer cladding imitates the behavior of the controller, and the peripheral is enabled to execute the task corresponding to the communication signal of the subscribed channel through the task engine, so that the dynamic peripheral interface matrix outer cladding can be decoupled from the peripheral. The designer of the dynamic peripheral interface matrix wrapper does not need to know the internal structure and function of the peripheral nor does the designer of the peripheral need to alter the peripheral itself for the dynamic peripheral interface matrix wrapper. The embodiment of the application simplifies the design and can be conveniently transplanted into any system.

For example, the communication signal decoder 321 obtains, according to the channel subscription information, the communication signal sent by the dynamic peripheral interface matrix network 31 to the subscribed channel, that is, the channel subscription information is the communication signals of the three channels of the subscription channels channel [0], channel [1], channel [10], and when the communication signal of channel [0] arrives, the task engine 322 is required to make the peripheral perform task 1; when the communication signal of channel [1] arrives, the task engine 322 is required to enable the peripheral to execute task 2; the task engine 322 is required to cause the peripheral to execute task 3 when the task engine 322 of channel [10] arrives. When the communication signal decoder 321 receives the communication signal sent by the channel, it will first determine whether it belongs to the subscription channel, then determine which subscription channel is specific, and the task engine 322 makes the peripheral device execute the corresponding function. In the existing peripheral interconnection technology, only one channel is supported to correspond to one task (for example, task 1 can only be triggered by a communication signal on channel [0 ]) and the limitation is large. The embodiment of the application can support a plurality of channels to trigger the same task (for example, the task 1 can be triggered by communication signals on channels channel [0], channel [2] and channel [9 ]), and is more flexible in application.

Specifically, the communication signal decoder 321 is further configured to:

the method comprises the steps of obtaining a starting address and an ending address of a task corresponding to a communication signal in an instruction table, wherein the instruction table (cmd_table) is used for storing instructions corresponding to the tasks, and the starting address and the ending address are used for indicating instructions corresponding to the tasks and ending execution.

The task engine is specifically configured to:

obtaining instructions corresponding to the start address and the end address from an instruction table according to the start address and the end address;

and decoding the instruction, and configuring a peripheral register according to the decoded instruction so as to control the peripheral to realize the function corresponding to the task.

The task engine 322 in the embodiment of the present application takes and decodes the instruction from the instruction table, and then controls the peripheral device to implement different tasks according to different instructions. The task engine 322 will control the behavior of the peripheral by configuring its own registers as the controller controls the peripheral. Referring to the above example, after receiving the start address and the end address of task 3, task engine 322 fetches one instruction from the instruction table at a time from the start address, and fetches one instruction after execution is completed until the end address is fetched, and task 3 is completed.

The embodiment of the application realizes the self-defined task through the task engine, the instruction table and the instruction set in the instruction table, can be self-defined no matter the task content or the task quantity, and has expandability. The embodiment of the application can adapt to the demands of different clients without changing the design, and provide the platform for secondary development of the clients, so that the workload of research and development can be reduced, the maximum degree of freedom can be given to the clients, and meanwhile, the communication cost aiming at the demands of different clients can be saved. Even for the sold products, the contents of the instruction list can be modified in a firmware upgrading mode and the like, so that the products are maintained.

Specifically, task engine 322 is mounted on a universal bus interface via universal bus protocol conversion module 324.

When a task engine of a dynamic peripheral interface matrix outer cladding layer obtains the control right of a peripheral register, a universal bus protocol conversion module selects a first bus to be connected with the peripheral register; when the controller obtains the control right of the peripheral register, the universal bus protocol conversion module selects a second bus to be connected with the peripheral register, the first bus is different from the second bus, the first bus is an advanced peripheral bus, and the second bus is an advanced high-performance bus.

Illustratively, the bus protocol conversion module 324 may be an AHB/APB selector, an AHB (Advanced High Performance Bus, advanced high-performance bus), an APB (Advanced Peripheral Bus ), e.g., the first bus and the second bus are APB and AHB, respectively.

Referring to fig. 7, when the dynamic peripheral interface matrix network 31 transmits a communication signal through a channel, the task engine 322 of the dynamic peripheral interface matrix wrapper 32 obtains the control right of the peripheral register 21; otherwise, the controller obtains control of the peripheral register 21.

The dynamic peripheral interface matrix wrapper 32 shares control of the peripheral registers 21 with the controller via a multiplexer.

The dynamic peripheral interface matrix outer wrapper 32 and the controller in the embodiment of the present application may share the control rights of the peripheral registers 21, so that it is not necessary to set separate corresponding registers for both.

Specifically, when the task engine 322 of the dynamic peripheral interface matrix wrapper 32 gains control of the peripheral registers 21, the AHB/APB selector connects the peripheral registers 21 using an APB bus, which is a peripheral bus used primarily for connection between low bandwidth peripheral peripherals. When the controller obtains the control right of the peripheral register 21, the AHB/APB selector is connected to the peripheral register 21 by using an AHB bus, which is a system bus and is mainly used for connection between high-performance modules (such as a CPU, a DMA, a DSP, etc.).

Specifically, the communication signal generation module 323 receives the communication signal conditions (event_cond_0, event_cond_1, … …) generated by the peripheral core 22, and transmits the communication signals (event_0, event_1, … …) to the dynamic peripheral interface matrix network 31.

The instruction table is stored in a dynamic peripheral interface matrix control register 325 included in the dynamic peripheral interface matrix wrapper or in the static memory of the peripheral.

An instruction table is provided within the dynamic peripheral interface matrix wrapper 32 of each peripheral, which may be present within the dynamic peripheral interface matrix control registers, or in static memory if the dynamic peripheral interface matrix control registers are exceeded. The user may fill out the instruction form by configuring the dynamic peripheral interface matrix control registers.

The main purpose of the dynamic peripheral interface matrix control register 325 is to store some control information, and the communication signal decoder 321 and the task engine 322 implement different behaviors according to the control information configured by software.

Referring to fig. 8, the instruction format stored in the instruction table is described as follows:

each instruction is 32 bits, the upper 3 bits are cmd, which indicates the type of command to be executed, [28:13] is the delay (beat), [12] is the reserved bits (reserve), and the lower 12 bits are the address of the register to be operated.

The instruction table supports five instructions: a write register command, a bit segment write register command, a delay wait command, a compare decision command, and a bit segment compare decision command. The method comprises the following steps:

3' b000 denotes write register, which requires the register address to be written to be filled in the reg_addr field at the same time; and fills out the 32bit write data in the next instruction.

3' b001 represents a bit segment write register, requiring the register address to be written to be simultaneously filled in the reg_addr field; and writing data of 32 bits in the second instruction and writing mask value of 32 bits in the third instruction.

3' b010 indicates latency waiting, the number of beats to be waiting needs to be filled in the cnt_value field at the same time, and the Finite State Machine (FSM) waits for the configured number of beats and fetches a next instruction after receiving the command.

3' b011 indicates comparison and judgment, and the specific operation is to read back the register corresponding to the reg_addr field, and compare whether the value of the register is equal to cmp_data stored by the next instruction, if so, continue to execute the next instruction, otherwise repeat the read back comparison operation. And if the comparison failure exceeds the set times, reporting error information, returning to a FETCH (FETCH) state by the finite state machine, and continuing to execute the next instruction.

And 3' b100 represents bit segment comparison and judgment, wherein the specific operation is to read back a register corresponding to the reg_addr field, take inverse phase and with a mask value stored in a third instruction, then compare whether the obtained value is equal to cmp_data stored in a second instruction, if so, continue to execute the next instruction, and otherwise repeat the read back comparison operation. And if the comparison failure exceeds the set times, reporting error information, returning to the instruction fetching state by the finite state machine, and continuously executing the next instruction.

The maximum depth of the instruction table is 2-CMD_ADDR_WIDTH, wherein the CMD_ADDR_WIDTH parameter can be transmitted from outside. Illustratively, the maximum depth of the instruction table in FIG. 8 is 32 bits.

Thus, the depth of the instruction table and the bit width of the stored instructions may be set as desired.

The user can control which instruction the task engine starts execution and ends execution by configuring the start address and the end address. An instruction table may define a plurality of tasks, distinguished by different start and end addresses.

Referring to fig. 9, the following description will be made specifically by means of an instruction table.

Wherein addr 0-addr 1 is a write register instruction, writing data 0x1234 to address 0x12.

addr 2-addr 4 is a bit section write register instruction, and the lower 8 bits of data 0xabcd are written into address 0x18.

addr5 is a wait instruction, and the task engine will wait for 0x32 system clock cycles before fetching a next instruction.

addr 6-addr 7 is a comparison judgment instruction, and the task engine reads data from the 0x20 address and then compares the data with 0 xaaaa.

addr29 to addr31 are bit segment comparison judgment instructions, and the task engine reads data from the 0x12 address and then compares the high 24bit with the 0x 1234.

The instruction list can be divided into a plurality of tasks, a user sets a starting address and an ending address of each task through a configuration register, and the tasks can be discontinuous. Nor does the instruction table need to be filled. For example, addr0 to addr4 in fig. 9 may be set as task 1, a start address addr0, an end address addr4, and 2 instructions are included; addr 6-addr 7 may be set to task 2, start address addr6, end address addr7, containing 1 instruction.

Referring to fig. 10, the communication signal decoder 321 receives communication signals of subscription channels transmitted from the dynamic peripheral interface matrix network and transmits the communication signals to the task engine 322, so that the peripheral 2 performs corresponding tasks.

Referring to fig. 10, the task engine 322 takes and executes instructions from an instruction table, and is configured to receive short trigger (short) instructions sent from a peripheral device in addition to receiving communication signals from a subscription channel sent from a dynamic peripheral interface matrix network to trigger execution of tasks. That is, after the short trigger command illustrated in the figure is enabled, the communication signal decoder 321 decodes the short trigger command and sends the decoded short trigger command to the task engine 322, so that the peripheral device 2 executes the task corresponding to the short trigger command. Short triggering instructions refer to the direct connection of an internally generated interrupt or communication signal or some special indication signal of a peripheral to the communication signal decoder portal rather than the forwarding through the dynamic peripheral interface matrix network as the same triggering signal as the communication signal of the subscription channel. Therefore, the time consumption for forwarding the dynamic peripheral interface matrix network can be saved, and the function of triggering the peripheral by the peripheral can be realized. Short trigger instructions may enable faster triggers.

Referring to fig. 10, the communication signal decoder 321 is further configured to receive a task termination instruction (stop_task), that is, a special task may be defined in the instruction table, when the current task is interrupted, the task engine may automatically execute, without triggering a communication signal, and the task termination instruction may not be interrupted. The task termination instruction can ensure that the initial state can be automatically restored after some peripheral devices are accidentally interrupted during operation, and the abnormality caused by the state or configuration left before the next operation is prevented.

Referring to fig. 11, the workflow of the state machine inside the task engine. Each circle represents an operational state of the task engine.

When no communication signal comes, the task engine is in IDLE state (IDLE), when the communication signal comes, the communication signal decoder decodes the communication signal, sends the start address and the end address of the corresponding task table to the task engine, and the state machine jumps to the FETCH Finger (FETCH).

In the fetch state, the task engine reads a 32bit instruction from the task table according to the start address, decodes the instruction, and jumps to a different state according to the cmd field.

If the cmd field is 3' b000, a write register instruction, then the state opportunity jumps directly to the write register state (WR_REG), rewrites the peripheral registers specified in the instruction via the local bus, and jumps back to the fetch state.

If the cmd field is 3' b001, i.e., a bit-writing register instruction, then the state machine will fetch two more 32bit instructions (because the bit-writing register instruction consists of 3 32bit instructions), jump to the read register state (RD_REG), read the contents of the peripheral registers specified in the instruction, jump to the write register state, rewrite the contents of the specified bit segments of the register in the instruction (because only the specified bit segments need to be rewritten, the other bit segments need to remain consistent with the previous, so the original value must be read first), and jump back to the fetch state.

If the cmd field is 3' b010, i.e., a latency waiting instruction, then the state machine jumps to the WAIT state (WAIT), counts the number of beats specified in the instruction by an internal counter, and jumps back to the fetch state.

If the cmd field is 3' b011, i.e. the comparison judging instruction, then the state machine firstly reads a 32bit instruction (the comparison judging instruction is composed of 2 32bit instructions), then jumps to a read register state, designates the value in the compared register in the read instruction, jumps to a comparison state (CMP) to compare with the comparison value filled in the instruction, jumps to a fetch instruction state if the comparison state is the same, jumps to a read register state if the comparison state is different, loops the operation above until the comparison times reach the maximum value set in the dynamic peripheral interface matrix register or the comparison is successful, and jumps to the fetch instruction state.

If the cmd field is 3' b100, i.e. a bit segment comparison judging instruction, the state machine firstly reads two 32bit instructions (the comparison judging instruction is composed of 3 32bit instructions), then jumps to a register reading state, designates the value in the compared register in the read instruction, jumps to a comparison state, compares the designated bit segment of the read value with the comparison value filled in the instruction, jumps back to the instruction fetching state if the designated bit segment is the same as the comparison value filled in the instruction, jumps back to the register reading state if the designated bit segment is different from the comparison value, circulates the operation above until the comparison times reach the maximum value set in the dynamic peripheral interface matrix register or the comparison is successful, and jumps back to the instruction fetching state.

And when the instruction fetch address is larger than the end address, indicating that the task is completed, the state machine jumps back to the idle state and waits for the arrival of the next communication signal.

The main function of the communication signal decoder is to receive the corresponding command, short triggering (short) command and task ending command (stop_task) trigger signals of the communication signals from the dynamic peripheral interface matrix network, and send the start address and end address of the task corresponding to the communication signal command, short triggering (short) command and task ending command (stop_task) of the channels of different reservation to the task engine according to the mapping relation preset by the user.

Referring to fig. 12, illustratively, the communication signal decoder is configured to decode the communication signal so that the task engine can know from which address to fetch instructions, each task having a different address, so that the task engine can fetch instructions for the corresponding task and configure the peripheral registers according to the instructions. The communication signal decoder receives four instructions, wherein one instruction is an all-task termination instruction rg_stop_task_addr [11:0], the all-task termination instruction is used when an unexpected task is terminated, so that a peripheral register returns to an initial state. If the tasks are received simultaneously, the task priority corresponding to the task termination instruction is highest, the task corresponding to the instruction corresponding to the communication signal is next, and finally the task corresponding to the short triggering instruction is next.

Specifically, three instructions received by the communication signal decoder and selected by the multiplexer are respectively realized by corresponding functional modules, namely, a short trigger instruction is realized by a short trigger signal module, an instruction corresponding to a communication signal is realized by a network signal module, and a task termination instruction is realized by a task termination module.

The communication signal decoder includes:

the short trigger signal module (short_event_proc) may map 3 short trigger communication signals onto 3 tasks according to the register rg_short_evt_sel_mask, respectively, and generate a short trigger execution (short_event_act) signal, which indicates that the short trigger communication signal is valid, and simultaneously send the start and end addresses of the corresponding short trigger tasks (short_task) to the multiplexer.

The network signal module (net_event_proc) may map the 32 subscribed network channels onto the 3 tasks according to the configuration of the register rg_ch_sel_mask, and generate a network execution (net_event_act) signal and a task address (net_task_addr) signal, which indicate that the subscribed network channel communication signal is valid, and send the start and end addresses of the corresponding subscribed channel tasks to the multiplexer.

The task termination module (stop_event_proc) may generate a stop execution (stop_event_act) signal upon receipt of a stop communication signal (stop_event), indicating that the stop communication signal (stop_event) is active, and send the start and end addresses of the stop task (stop_task) to the multiplexer. Because the termination tasks support only 1, no mapping is needed.

The multiplexer obtains output signals, i.e., task execution (event_act) signals and initial recovery (task_addr [11:0 ]) signals, based on the received input signals (IN 0, IN1, IN2 and the selection signals sel [0], sel [1], sel [2 ]).

Referring to fig. 13, if the network signal module inputs communication signals of 32 reservation channels (dpim_channel [31:0 ]), after being processed by the synchronization unit (sync), each of the tasks' rg_ch_sel_mask registers (rg_ch_sel_mask [31:0 ]) after the inversion processing (inv), that is, the registers rg_ch_sel_mask in fig. 12 are processed (and) and then bit-pressed or (|) to obtain 3 output results of 1bit, after detecting a rising edge (rise_edge) or a falling edge (only in the example in the figure), the output results are divided into two groups, one group (i.e., the output results) generates a network execution signal, and the other group (i.e., the output results) is used as a selection signal of the Multiplexer (MUX) to select and send out the corresponding task start (net_task_rt_addr) and end address (net_task_end_addr_end).

Referring to fig. 14, if the input of the short trigger signal module is 3 communication signals (event_in [2:0 ]), after synchronization processing (sync), the registers rg_short_ev_sel_mask of each task after the inversion processing (inv) are respectively followed by obtaining 3 output results of 1bit or (|) after detecting a rising edge (ri_edge) or a falling edge (in the figure) for the output results, dividing the output results into two groups, namely, the output results of rg_short_ev_sel_mask_1 [2:0], rg_short_ev_sel_mask_2 [2:0], and generating a trigger signal (i.e. the output results of one group) or the output results of the other group (i.e. the output results of the other group) as the end of the multiplexing (event_end of the) and the output (end of the multiplexing) of the input (event_end of the task) are respectively.

Referring to fig. 15, the task termination module has 1 termination communication signal (stop_event) input, and receives 1bit output result after synchronization (sync) and rg_stop_task_en register (enable register of task termination function), and generates a termination execution signal (stop_event_act) after detecting a rising edge (rise_edge) or a falling edge (only shown as an example).

In another implementation of the present invention, the task engine detects a rising edge (rise_edge) or a falling edge of the output result in the network signal module; the output result in the short trigger signal module is detected by a task engine on a rising edge (rise_edge) or a falling edge of the output result; the output result in the task termination module is detected by a task engine as a rising edge (rise_edge) or a falling edge.

In this embodiment, the purpose of rising edge detection or falling edge detection is to indicate that subsequent logic can start working after detecting a pulse, and subsequent processing of an output result can be performed after detecting that an output result has a rising edge or a falling edge, so that a peripheral device can perform a task more accurately.

In this embodiment, the purpose of the rising edge detection or the falling edge detection is to indicate under what conditions the subsequent logic can continue to operate, and the task engine only fetches instructions when detecting that an output result has a rising edge or a falling edge.

For example, a communication signal may trigger a peripheral to perform a task only once, and rising edge detection may avoid a communication signal causing a peripheral to perform multiple tasks. If there is no rising edge or falling edge detection, the output result is always high, which causes the task engine to fetch instructions continuously, the peripheral will execute multiple tasks, but in fact the controller only wants the peripheral to execute a task once.

Fig. 16 is a block diagram of a processor according to another embodiment of the invention. The processor 1600 of the present embodiment includes: processor core 1601 and any of the peripheral interconnect devices 1602 described above. The processor 1601 core includes a controller, where the controller is configured to control a peripheral device, and the peripheral device interconnection device is configured to implement interconnection of the peripheral device according to preset settings of the controller.

Fig. 17 is a schematic diagram of a system-on-chip according to another embodiment of the present invention. The system on chip 1700 of the present embodiment includes a plurality of processors 1710 and at least two peripherals 1712. The processor 1701 is a processor according to the above.

In addition, the specific implementation of each step in the program may refer to the corresponding steps and corresponding descriptions in the units in the above method embodiments, which are not repeated herein. It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the apparatus and modules described above may refer to corresponding procedure descriptions in the foregoing method embodiments, which are not repeated herein.

It should be noted that, according to implementation requirements, each component/step described in the embodiments of the present invention may be split into more components/steps, or two or more components/steps or part of operations of the components/steps may be combined into new components/steps, so as to achieve the objects of the embodiments of the present invention.

The above-described methods according to embodiments of the present invention may be implemented in hardware, firmware, or as software or computer code storable in a recording medium such as a CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk, or as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium and to be stored in a local recording medium downloaded through a network, so that the methods described herein may be stored on such software processes on a recording medium using a general purpose computer, special purpose processor, or programmable or special purpose hardware such as an ASIC or FPGA. It is understood that a computer, processor, microprocessor controller, or programmable hardware includes a memory component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code that, when accessed and executed by the computer, processor, or hardware, performs the methods described herein. Furthermore, when a general purpose computer accesses code for implementing the methods illustrated herein, execution of the code converts the general purpose computer into a special purpose computer for performing the methods illustrated herein.

Those of ordinary skill in the art will appreciate that the elements and method steps of the examples described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present invention.

The above embodiments are only for illustrating the embodiments of the present invention, but not for limiting the embodiments of the present invention, and various changes and modifications may be made by one skilled in the relevant art without departing from the spirit and scope of the embodiments of the present invention, so that all equivalent technical solutions also fall within the scope of the embodiments of the present invention, and the scope of the embodiments of the present invention should be defined by the claims.

Claims

1. A peripheral interconnection apparatus for use in a system on a chip comprising at least two peripheral devices, the apparatus comprising:

the dynamic peripheral interface matrix network is used for receiving communication signals generated by the at least two peripheral devices and distributing the communication signals to different channels according to channel configuration information;

at least two dynamic peripheral interface matrix overwrites, wherein each peripheral is provided with the corresponding dynamic peripheral interface matrix overwrites, and the dynamic peripheral interface matrix overwrites are used for enabling the peripheral subscribed to the channel to execute the task corresponding to the communication signal sent by the dynamic peripheral interface matrix network according to the channel subscription information;

the channel configuration information, the channel subscription information, and the tasks are pre-configured by a controller.

2. The peripheral interconnect device of claim 1, wherein the channel configuration information, the channel subscription information, and the tasks are preconfigured by the controller through software.

3. The peripheral interconnect device of claim 1, wherein the channel configuration information is sent by the controller to the dynamic peripheral interface matrix network via a dynamic peripheral interface matrix register;

and the channel subscription information and the task are sent to the dynamic peripheral interface matrix outer cladding layer by the controller through the dynamic peripheral interface matrix register.

4. The peripheral interconnect device of claim 1 wherein the dynamic peripheral interface matrix register is coupled to the controller via a system bus;

the dynamic peripheral interface matrix register is connected with the dynamic peripheral interface matrix network and the dynamic peripheral interface matrix register is connected with the dynamic peripheral interface matrix outer cladding layer through a local connecting line.

5. The peripheral interconnect device of claim 1, wherein each of the dynamic peripheral interface matrix overwrites is disposed inside its corresponding peripheral; or,

The at least two dynamic peripheral interface matrix outer cladding layers are arranged in any peripheral in a centralized manner; or,

the at least two dynamic peripheral interface matrix overwrites are centrally disposed external to the peripheral.

6. The peripheral interconnect device of claim 1, wherein the dynamic peripheral interface matrix network comprises:

a selection logic port, configured to receive communication signals generated by the at least two peripheral devices, and select the received communication signals according to the channel configuration information, so as to transmit the selected communication signals;

the communication signal synchronous pulse module is used for receiving the communication signal and converting the communication signal into a pulse signal with uniform pulse width;

and the matrix network is used for receiving the pulse signals with the uniform pulse width and transmitting the pulse signals with the uniform pulse width to the channel selected according to the channel configuration information.

7. The peripheral interconnect device of claim 6, wherein the dynamic peripheral interface matrix network further comprises:

and the pulse expansion module is used for carrying out pulse signal broadening on the pulse signals with uniform pulse width received by each channel so as to send the pulse signals after the pulse broadening to the channel selected according to the channel configuration information.

8. The peripheral interconnect device of any of claims 6 or 7, wherein the selection logic port comprises a plurality of ports and a selector, at least one port selecting at least two of the communication signals received by the selector according to the channel configuration information; the at least two communication signals are generated by the same said peripheral or by at least two different said peripherals, respectively.

9. The peripheral interconnect device of any of claims 6 or 7, wherein the dynamic peripheral interface matrix network further comprises:

and the interrupt generation module is used for generating an interrupt instruction and sending the interrupt instruction to the controller to inform the controller that the communication signal is received by the selection logic port when the communication signal is received by the selection logic port.

10. The peripheral interconnect device of any of claims 1-7, wherein the dynamic peripheral interface matrix wrapper comprises:

the communication signal decoder is used for acquiring a communication signal sent to the subscribed channel by the dynamic peripheral interface matrix network according to the channel subscription information;

the task engine is used for obtaining a task corresponding to the communication signal according to the communication signal obtained by the communication signal decoder, so that the peripheral equipment executes the task;

And the communication signal generation module is used for enabling the communication signals generated by the peripheral to be sent to the dynamic peripheral interface matrix network.

11. The peripheral interconnection device according to claim 10, wherein the communication signal decoder is further configured to obtain a start address and an end address of a task corresponding to the communication signal in an instruction table, where the instruction table is configured to store instructions corresponding to each task, and the start address and the end address are configured to instruct the instruction corresponding to the task to start execution and the instruction to end execution;

the task engine is specifically configured to:

obtaining instructions corresponding to the starting address and the ending address from an instruction table according to the starting address and the ending address;

12. The peripheral interconnect device of claim 11, wherein the instruction table is stored in a dynamic peripheral interface matrix control register included in the dynamic peripheral interface matrix wrapper or in a static memory of a peripheral.

13. The peripheral interconnect device of claim 12, wherein the depth of the instruction table and the bit width of the stored instructions are set by the dynamic peripheral interface matrix control register or a peripheral's static memory.

14. The peripheral interconnect device of claim 11, wherein the task engine of the dynamic peripheral interface matrix wrapper obtains control of the peripheral registers when the dynamic peripheral interface matrix network transmits the communication signals over the channel; otherwise, the controller obtains the control right of the peripheral register.

15. The peripheral interconnect device of claim 14, wherein the dynamic peripheral interface matrix wrapper shares control of the peripheral registers with the controller through a multiplexer.

16. The peripheral interconnect device of claim 14, wherein the task engine is mounted on a universal bus interface via a universal bus protocol conversion module;

when the task engine of the dynamic peripheral interface matrix outer cladding obtains the control right of the peripheral register, the universal bus protocol conversion module selects a first bus to be connected with the peripheral register; when the controller obtains the control right of the peripheral register, the universal bus protocol conversion module selects a second bus to be connected with the peripheral register, the first bus is different from the second bus, the first bus is an advanced peripheral bus, and the second bus is an advanced high-performance bus.

17. The peripheral interconnect device of claim 11, wherein the instruction table supports five instructions: a write register command, a bit segment write register command, a delay wait command, a compare decision command, and a bit segment compare decision command.

18. The peripheral interconnection device of claim 10, wherein the communication signal decoder is further configured to receive a short trigger instruction sent by the peripheral, where the short trigger instruction is to enable the peripheral to implement a corresponding function according to a trigger of the peripheral, and the short trigger instruction includes one of an interrupt, a communication signal, or an indication signal generated by the peripheral, and the communication signal decoder sends a start address and an end address of the short trigger instruction to the task engine.

19. The peripheral interconnect device of claim 18 wherein the communication signal decoder is further configured to receive a task termination instruction, the task termination instruction being a task that when a currently executing task is interrupted, causes the task engine to execute a next task or continue executing the interrupted task.

20. The peripheral interconnect device of claim 19, wherein the communication signal decoder comprises:

the network signal module is used for receiving the communication signals of the reservation channel, carrying out AND processing and bit pressing or processing on the register of each task after the processing of the synchronization unit and the inverting, obtaining an output result, and generating a network execution signal for the output result after detecting the rising edge or the falling edge of the output result;

The short trigger signal module receives the communication signals, performs bit pressing or processing after synchronous processing and respectively follows the inverted registers of each task to obtain an output result, and generates a short trigger execution signal for the output result after detecting a rising edge or a falling edge of the output result;

and the task termination module receives the termination communication signal, and generates a termination execution signal after the output result detects a rising edge or a falling edge after the synchronization processing and the enabling register phase of the task termination function.

21. The peripheral interconnect device of claim 19, wherein the communication signal decoder comprises:

the network signal module is used for receiving the communication signals of the reservation channel, carrying out AND processing and bit pressing or processing on the register of each task after the processing of the synchronization unit, obtaining an output result, and if the task engine detects a rising edge or a falling edge on the output result, generating a network execution signal on the output result or the output result, and in addition, the output result is used as a selection signal of the multiplexer to select and send out corresponding task starting and ending addresses;

The short trigger signal module receives the communication signals, performs bit pressing or processing after synchronization processing and respectively follows the inverted registers of each task to obtain an output result, and generates a short trigger execution signal for the output result if the task engine detects a rising edge or a falling edge of the output result, and in addition, the output result is also used as a selection signal of a multiplexer to select corresponding task starting and ending addresses to send;

and the task termination module receives the termination communication signal, and generates a termination execution signal after synchronous processing and after the enabling register phase of the task termination function, if the task engine detects a rising edge or a falling edge on the output result.

22. A processor, comprising:

a processor core; the method comprises the steps of,

the peripheral interconnect device of any of claims 1-21;

the processor core includes a controller for controlling the peripheral device,

the peripheral interconnection device is used for realizing interconnection of the peripheral according to the preset of the controller.

23. A system on a chip, comprising:

a plurality of processors and at least two peripherals, the processors being the processor of claim 22.