CN116566388A - A Fully Differential Buffer for ADC Based on Switched Capacitor Timing Implementation - Google Patents

Abstract

The present invention provides a fully differential buffer suitable for ADC based on switched capacitor timing, which is characterized in that it includes a first capacitor array, a second capacitor array, an amplifier, a feedback capacitor Cf, a switch sw1, a switch sw1′, a switch sw2, switch sw2', switch sw3, switch sw3', switch sw4 and switch sw4'; this circuit implements a fully differential buffer circuit based on switched capacitor timing, by continuously charging the feedback capacitor Cf to maintain The output voltage Vo_ref and the amplification factor K can be adjusted by changing the connection mode of the capacitor array, which is especially suitable for driving a fully differential ADC circuit.

Description

A Fully Differential Buffer for ADC Based on Switched Capacitor Timing Implementation

technical field

The invention relates to the technical field of integrated circuits, in particular to a fully differential buffer suitable for ADC realized based on switched capacitor timing.

Background technique

In a complete ADC (analog-digital converter, analog-to-digital converter) system, including ADC circuit, reference circuit, and reference signal buffer, as shown in Figure 1, the reference signal generates a reference voltage Vin_ref, and the output of the reference voltage buffer is full Range (Full Scale) voltage Vref to ADC. Among them, Vin_p is the positive polarity input signal voltage, Vin_n is the negative polarity input voltage signal and VIN=Vin_p-Vin_n, Vrefp is the positive polarity ADC full-scale voltage, Vrefn is the negative polarity ADC full-scale voltage, Vref_adc is the ADC reference voltage , which is the full-scale voltage, and Data is the data output of the ADC.

The output voltage of a conventional reference signal buffer is generally single-ended, and the full-scale voltage of the ADC is generally connected to Vref (reference voltage) and VSS (chip ground). When the power supply noise of the chip is large, it will affect the Vref voltage, thereby affecting the full-scale voltage of the ADC. This structure requires the buffer to have high power supply noise suppression performance.

In order to improve the power supply noise suppression performance of the fully differential ADC, the buffer is required to be fully differential, as shown in Figure 2, where Vin_p is the positive input signal voltage, Vin_n is the negative input voltage signal and VIN=Vin_p- Vin_n, Vin_refp is the positive polarity input signal voltage of the buffer, Vin_refn is the negative polarity input signal voltage of the buffer, Vo_refp is the positive polarity output signal voltage of the buffer, Vo_refn is the negative polarity output signal voltage of the buffer, Vo_ref is the buffer and Vo_ref=Vo_refp-Vo_refn, Vrefp is the positive ADC full-scale voltage, Vrefn is the negative ADC full-scale voltage, Vref_adc is the ADC reference voltage, that is, the full-scale voltage, Data is the data output of the ADC.

A conventional double-terminal buffer can be implemented in the form of resistance feedback, as shown in Figure 3, where Vin_refp is the positive polarity input signal voltage, Vin_refn is the negative polarity input signal voltage, Vo_refp is the positive polarity output signal voltage, Vo_refn is the negative polarity Sexual output signal voltage.

The disadvantage of this structure is that when the phase of the ADC circuit driven by the buffer changes, the buffer will be greatly affected and conducted to the reference circuit through the resistance. This requires the reference circuit to have a certain driving capability, so that the kick-back noise (kick-back noise) can be strongly suppressed.

Contents of the invention

The purpose of the present invention is to propose a fully differential buffer suitable for ADCs based on switched capacitor timing. While realizing full differential drive, the principle of switched capacitors is adopted to cooperate with the timing of the ADC to completely isolate the buffer when the ADC is running. The impact of kickback noise on the reference circuit greatly reduces the driving capability requirements of the reference circuit to solve the problem that when the phase of the ADC circuit driven by the buffer changes, the buffer will be greatly affected and conduct to the reference circuit through resistance .

To achieve the above object, the present invention provides the following technical solutions:

A fully differential buffer suitable for ADC based on switched capacitor timing, including a first capacitor array 101, a second capacitor array 103, an amplifier 102, a feedback capacitor Cf, a switch sw1, a switch sw1', a switch sw2, and a switch sw2' , switch sw3, switch sw3', switch sw4, and switch sw4', wherein the switch sw1 is connected between the positive input signal voltage Vin_refp and the input end of the first capacitor array 101, and one end of the switch sw4 Connected to the input terminal of the first capacitor array 101, the other end is connected between the inverting output terminal of the amplifier 102 and the positive output signal voltage Vo_refp, the switch sw2 is connected to the first capacitor array 101 Between the output end of the output terminal and the common-mode voltage Vcm, the switch sw3 is connected between the positive input terminal of the first capacitor array 101 and the amplifier 102; the switch sw1' is connected to the input signal of negative polarity Between the voltage Vin_refn and the input end of the second capacitor array 103, one end of the switch sw4' is connected to the input end of the second capacitor array 103, and the other end is connected to the positive output end of the amplifier 102 and Between the output signal voltage Vo_refn of negative polarity, the switch sw2' is connected between the output end of the second capacitor array 103 and the common mode voltage Vcm, and the switch sw3' is connected to the second capacitor array 103 and Between the inverting input terminals of the amplifier 102; the feedback capacitor Cf has two, wherein the two sides of the feedback capacitor Cf are respectively connected to the positive input terminal and the inverting output terminal of the amplifier 102, and the other Both sides of the feedback capacitor Cf are respectively connected to the inverting input terminal and the forward output terminal of the amplifier 102 .

The capacitor array 101 and the second capacitor array 103 connect capacitors in parallel to collect the input voltage Vin_ref during the sampling phase of the buffer circuit;

Vin_ref=Vin_refp-Vin_refn

In the amplification stage, the capacitors are connected in series or in parallel to obtain different ratios of output voltage Vo_ref;

Vo_ref=Vo_refp-Vo_refn

Therefore, the output voltage Vo_ref of the buffer can amplify the input voltage Vin_ref in different proportions.

The amplifier 102 forms a negative feedback loop with the feedback capacitor Cf so that the differential input voltage is zero, and cooperates with the capacitor array 101 and the second capacitor array 103 to amplify the output voltage.

The switch sw1, the switch sw1', the switch sw2, the switch sw2', the switch sw3, the switch sw3', the switch sw4 and the switch sw4' realize two phases of sampling and amplification connection relationship, and cooperate with the timing of the next-level ADC circuit, collect the input voltage Vin_ref in the sampling stage, and charge the feedback capacitor Cf in the amplification stage, so that the output voltage Vo_ref can achieve a certain amplification factor K; The feedback capacitor Cf is charged to maintain the output voltage Vo_ref, and the amplification factor K can be adjusted by changing the connection mode of the capacitor array 101 and the second capacitor array 103 .

When the ADC is in the input signal sampling phase, the buffer is in the sampling phase; at this time, one end of the first capacitor array 101 and the second capacitor array 103 are respectively connected to the positive polarity through the switch sw1 and the switch sw1' The input signal voltage Vin_refp and the negative input signal voltage Vin_refn, thereby obtaining the input voltage Vin_ref, and the other end is connected to the common mode voltage Vcm through the switch sw2 and the switch sw2' to realize input voltage sampling; the switch sw4, the switch sw2' The switch sw4', the switch sw3 and the switch sw3' are turned off, and the negative feedback circuit formed by connecting the amplifier 102 and the feedback capacitor Cf keeps the output voltage Vo_ref unchanged from the voltage of the previous amplification stage;

When the ADC is in the digital-to-analog conversion stage, this buffer amplifies the stage; the switch sw1, the switch sw1', the switch sw2 and the switch sw2' are turned off, the switch sw3, the switch sw3', The switch sw4 and the switch sw4' are closed, at this moment, the first capacitor array 101 and the second capacitor array 103 are connected to the two ends of the amplifier 102 and connected in parallel with the feedback capacitor Cf; because the One end of the feedback capacitor Cf connected to the amplifier 102 is a high-impedance node. After the initial stabilization process of several cycles, the voltage at both ends of the feedback capacitor Cf remains stable and output.

Wherein, K is a proportionality factor, that is, the amplification factor of the buffer, which is related to the configuration of the first capacitor array 101 and the second capacitor array 103 .

As a preference, the first capacitor array 101 and the second capacitor array 103 include one or more capacitors connected through switches. In the sampling phase, the capacitors are connected in parallel through switches, and in the amplification phase, the capacitors are connected into Series or parallel to achieve different magnifications K.

The different connection modes of the first capacitor array 101 and the second capacitor array 103 in the sampling and amplification stages can obtain different magnification factors K, specifically including the following:

In the sampling stage, the capacitor arrays C1~Cn are connected in parallel;

In the amplification stage, if C1～Cn are connected in series, the magnification

K=n

By adjusting the number n of capacitors, different magnifications can be obtained;

In the amplification stage, if C1～Cn are still connected in parallel, the amplification factor

K=1

In this way, the output voltage of this buffer is equal to the output voltage, that is, the buffer with an amplification factor of 1.

The first capacitor array 101 and the second capacitor array 103 can be simplified as a single capacitor Cs, that is, the sampling capacitor;

In the sampling phase, the sampling capacitor Cs collects the input voltage Vin_ref;

In the amplification stage, the sampling capacitor Cs and the feedback capacitor Cf are connected in parallel, and the charge redistribution makes the voltages of the two capacitors equal. When the circuit reaches balance, the Vo_ref voltage is finally equal to Vin_ref, so the amplification factor is obtained

K=1

In this way, the output voltage of this buffer is equal to the output voltage, that is, the buffer with an amplification factor of 1.

Compared with the prior art, the beneficial effects of the present invention are as follows:

The fully differential buffer circuit provided by the present invention reduces the driving capability requirement of the upper-level reference circuit, eliminates the impact of kick back noise (kick back noise) on the reference circuit through the buffer circuit during ADC operation, and can be adjusted by adjusting Capacitor arrays achieve different magnifications.

Description of drawings

Figure 1 is a conventional reference single-ended buffer ADC system;

Figure 2 is a fully differential reference buffer ADC system;

FIG. 3 is a conventional fully differential buffer circuit;

Fig. 4 is the fully differential buffer applicable to ADC of the present invention;

Fig. 5 is the circuit structural diagram of the sampling stage in the fully differential buffer of the present invention;

Fig. 6 is the circuit structure diagram of the amplification stage in the fully differential buffer of the present invention;

Fig. 7 is the circuit diagram of the internal connection structure of the first capacitor array and the second capacitor array;

Fig. 8 is the equivalent circuit diagram of capacitor arrays connected in series or parallel in different connection modes in the sampling stage and the amplification stage;

Fig. 9 is a magnification factor K=1, and the capacitor array is a fully differential buffer of a single capacitor;

Fig. 10 is the equivalent circuit diagram of the full differential buffer sampling stage in which the capacitor array is a single capacitor;

Fig. 11 is the equivalent circuit diagram of the fully differential buffer amplification stage in which the capacitor array is a single capacitor;

In the figure: 101 - first capacitor array; 102 - amplifier; 103 - second capacitor array.

Detailed ways

In order to clarify the technical problems, technical solutions, implementation process and performance demonstration, the present invention will be further described in detail below in conjunction with the examples. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in the figures indicate functionally identical or similar elements.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or better than other embodiments.

In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific implementation manners. It will be understood by those skilled in the art that the present disclosure may be practiced without some of the specific details. In some instances, methods, means, components and circuits that are well known to those skilled in the art have not been described in detail so as to obscure the gist of the present disclosure.

Example 1

As shown in FIG. 4, the present invention relates to a fully differential buffer circuit suitable for ADC based on switched capacitor timing, including a first capacitor array 101, a second capacitor array 103, an amplifier 102, a feedback capacitor Cf, a switch sw1, switch sw1', switch sw2, switch sw2', switch sw3, switch sw3', switch sw4 and switch sw4', wherein the switch sw1 is connected to the input signal voltage Vin_refp of positive polarity and the input of the first capacitor array 101 Between terminals, one terminal of the switch sw4 is connected to the input terminal of the first capacitor array 101, and the other terminal is connected between the inverting output terminal of the amplifier 102 and the positive output signal voltage Vo_refp, the switch sw2 is connected between the output terminal of the first capacitor array 101 and the common mode voltage Vcm, and the switch sw3 is connected between the first capacitor array 101 and the positive input terminal of the amplifier 102; the switch sw1' is connected between the negative input signal voltage Vin_refn and the input end of the second capacitor array 103, one end of the switch sw4' is connected to the input end of the second capacitor array 103, and the other end is connected to Between the positive output terminal of the amplifier 102 and the negative output signal voltage Vo_refn, the switch sw2' is connected between the output terminal of the second capacitor array 103 and the common-mode voltage Vcm, and the switch sw3' Connected between the second capacitor array 103 and the inverting input of the amplifier 102; there are two feedback capacitors Cf, one of which is connected to the positive side of the amplifier 102 on both sides of the feedback capacitor Cf The input terminal and the inverting output terminal, and the two sides of the other feedback capacitor Cf are respectively connected to the inverting input terminal and the forward output terminal of the amplifier 102 .

The capacitor array 101 and the second capacitor array 103 connect capacitors in parallel to collect the input voltage Vin_ref during the sampling phase of the buffer circuit;

Vin_ref=Vin_refp-Vin_refn

In the amplification stage, the capacitors are connected in series or in parallel to obtain different ratios of output voltage Vo_ref;

Vo_ref=Vo_refp-Vo_refn

Therefore, the output voltage Vo_ref of the buffer can amplify the input voltage Vin_ref in different proportions.

The amplifier 102 forms a negative feedback loop with the feedback capacitor Cf so that the differential input voltage is zero, and cooperates with the capacitor array 101 and the second capacitor array 103 to amplify the output voltage.

To match the timing of the ADC, this fully differential buffer circuit has two repeating phases, a sampling phase and an amplification phase; the switch sw1, the switch sw1', the switch sw2, the switch sw2', the The switch sw3, the switch sw3', the switch sw4, and the switch sw4' realize the connection relationship between the two phases of sampling and amplification, and cooperate with the timing sequence of the next-stage ADC circuit to collect the input voltage Vin_ref in the sampling phase. In the amplification stage, the feedback capacitor Cf is charged, so that the output voltage Vo_ref achieves a certain amplification factor K; the output voltage Vo_ref is maintained by continuously charging the feedback capacitor Cf, and the amplification factor K can be changed by changing the capacitor array 101 The connection mode with the second capacitor array 103 is adjusted.

As shown in Figure 5, when the ADC is in the input signal sampling phase, this buffer is in the sampling phase in Figure 5. At this time, one end of the first capacitor array 101 and the second capacitor array 103 are respectively connected to the positive input signal voltage Vin_refp and the negative input signal voltage Vin_refn through the switch sw1 and the switch sw1', using formula

Vin_ref=Vin_refp-Vin_refn

Thus, the input voltage Vin_ref is obtained, and the other end is connected to the common mode voltage Vcm through the switch sw2 and the switch sw2' to realize input voltage sampling; at this time, the switch sw4, the switch sw4', the switch sw3 and the The switch sw3' is turned off;

The negative feedback circuit formed by the amplifier 102 and the feedback capacitor Cf keeps the output voltage Vo_ref unchanged from the voltage of the previous amplification stage.

As shown in Figure 6, this buffer is in the amplification phase in Figure 5 while the ADC is in the digital-to-analog conversion phase. The switch sw1, the switch sw1', the switch sw2, and the switch sw2' are turned off, and the switch sw3, the switch sw3', the switch sw4, and the switch sw4' are turned off. The first capacitor array 101 and the second capacitor array 103 are connected to both ends of the amplifier 102 and connected in parallel with the feedback capacitor Cf. Since the end of the feedback capacitor Cf connected to the amplifier 102 is a high-impedance node, after the initial stabilization process of several cycles, the voltage at both ends of the feedback capacitor Cf remains stable and output.

Vo_ref=K*Vin_ref

Wherein, K is a proportionality factor, that is, the amplification factor of the buffer, which is related to the configuration of the first capacitor array 101 and the second capacitor array 103 .

After the circuit reaches equilibrium, the voltages of the first capacitor array 101 and the second capacitor array 103 and the feedback capacitor Cf remain stable, and the first capacitor array 101 and the second capacitor array 101 and the second capacitor array in the sampling stage and the amplification stage The charge of the capacitor array 103 remains basically unchanged, so the requirement for the driving capability of the front-end reference circuit is extremely low.

In addition, when the ADC is driven during the amplification stage, since the switch sw1, the switch sw1', the switch sw2 and the switch sw2' are turned off, the reference circuit will not be affected at all, thus avoiding backlash. The effect of kick backnoise on the reference circuit.

As shown in Figures 7 and 8, as a possible implementation, the first capacitor array 101 and the second capacitor array 103 include one or more capacitors connected through switches, and there are various forms of implementation . Through different connection modes of the first capacitor array 101 and the second capacitor array 103 in the sampling and amplifying stages, different magnification factors K can be obtained.

In the sampling stage, the capacitor arrays C1~Cn are connected in parallel;

In the amplification stage, if C1～Cn are connected in series, the magnification

K=n

By adjusting the number n of capacitors, different amplification factors can be obtained.

In the amplification stage, if C1～Cn are still connected in parallel, the amplification factor

K=1

In this way, the output voltage of this buffer is equal to the output voltage, that is, the buffer with an amplification factor of 1.

Example 2

As a possible implementation manner, when n=1, the first capacitor array 101 and the second capacitor array 103 become a single capacitor. This situation is described in detail below;

As shown in Figures 9-11, it is a magnification factor K=1, and the first capacitor array 101 and the second capacitor array 103 are specific examples of a single capacitor; in the figure, VDD is a power supply terminal, and VB is a bias Voltage.

The input voltage Vin_ref is the voltage drop generated by the mirror current on the resistor, and the capacitor array 101 is simplified into a single capacitor Cs, which is the sampling capacitor.

In the sampling phase, one end of Cs is connected to the input voltage, and the other end is connected to the common-mode voltage Vcm, so that Cs collects the input voltage Vin_ref.

In the amplification stage, one end of Cs (the sampling stage is connected to the input voltage) is connected to the output of the amplifier 102, and the other end (the sampling stage is connected to the common mode voltage) is connected to the input of the amplifier 102, realizing Cs and Parallel connection of Cf. Since one end of Cf is a high-impedance node, Cs shares its own charge with Cf, and the voltages of the two are the same. After several initial cycles, the voltage on Cf and the sampling voltage of Cs reach a balance, that is, both are Vin_ref, so Vo_ref=Vin_ref.

In summary, based on the timing of switched capacitors, a fully differential buffer circuit suitable for ADC is realized. This fully differential buffer circuit can fully match the timing of the ADC, and is especially suitable for ADC systems. And through different composition methods of the first capacitor array 101 and the second capacitor array 103 , different ratios of magnification can be realized.

The basic principles, main features and advantages of the present invention have been shown and described above. Those skilled in the art should understand that the present invention is not limited by the above-mentioned embodiments, and those described in the above-mentioned embodiments and description are only preferred examples of the present invention, and are not intended to limit the present invention, without departing from the spirit and scope of the present invention. Under the premise, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the claimed invention. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (8)

1. A fully differential buffer suitable for ADC based on switched capacitor timing implementation, comprising a first capacitor array (101), a second capacitor array (103), an amplifier (102), a feedback capacitor Cf, a switch sw1', a switch sw2', a switch sw3', a switch sw4 and a switch sw4', wherein the switch sw1 is connected between an input signal voltage vin_refp of positive polarity and an input of the first capacitor array (101), one end of the switch sw4 is connected to an input of the first capacitor array (101), the other end is connected between an inverted output of the amplifier (102) and an output signal voltage vo_refp of positive polarity, the switch sw2 is connected between an output of the first capacitor array (101) and a common mode voltage Vcm, and the switch sw3 is connected between the first capacitor array (101) and a positive input of the amplifier (102); the switch sw1 'is connected between the input signal voltage vin_refn with the negative polarity and the input end of the second capacitor array (103), one end of the switch sw4' is connected to the input end of the second capacitor array (103), the other end is connected between the positive output end of the amplifier (102) and the output signal voltage vo_refn with the negative polarity, the switch sw2 'is connected between the output end of the second capacitor array (103) and the common-mode voltage Vcm, and the switch sw3' is connected between the second capacitor array (103) and the inverting input end of the amplifier (102); the feedback capacitor Cf has two sides, wherein one side of the feedback capacitor Cf is respectively connected to the forward input end and the reverse output end of the amplifier (102), and the other side of the feedback capacitor Cf is respectively connected to the reverse input end and the forward output end of the amplifier (102).

2. A fully differential buffer for ADC based on switched capacitor timing according to claim 1, characterized in that the capacitor array (101) and the second capacitor array (103) connect capacitors in parallel to collect the input voltage vin_ref during the sampling phase of the buffer circuit;

Vin_ref＝Vin_refp-Vin_refn

the capacitors are connected in series or in parallel in the amplifying stage to obtain output voltages vo_ref with different proportions;

Vo_ref＝Vo_refp-Vo_refn

so that the output voltage Vo _ ref of the buffer can amplify the input voltage Vin _ ref in different proportions.

3. A fully differential buffer for ADC based on switched capacitor timing according to claim 1, wherein the amplifier (102) is configured to amplify the output voltage by forming a negative feedback loop with the feedback capacitor Cf, so that the differential input voltage is zero, and cooperating with the capacitor array (101) and the second capacitor array (103).

4. The fully differential buffer for ADC based on the switch capacitor timing according to claim 1, wherein the switch sw1, the switch sw1', the switch sw2', the switch sw3', the switch sw4 and the switch sw4' implement a connection relationship between sampling and amplifying phases, and cooperate with the timing of the ADC circuit of the next stage to collect the input voltage vin_ref in the sampling stage and charge the feedback capacitor Cf in the amplifying stage, so that the output voltage vo_ref implements a certain amplification factor K; the feedback capacitor Cf is continuously charged to maintain the output voltage vo_ref, and the amplification factor K can be adjusted by changing the connection mode of the capacitor array (101) and the second capacitor array (103).

5. The fully differential buffer for an ADC of claim 4, wherein the buffer is in a sampling phase when the ADC is in an input signal sampling phase; at this time, one end of the first capacitor array (101) and one end of the second capacitor array (103) are respectively connected with an input signal voltage vin_refp with positive polarity and an input signal voltage vin_refn with negative polarity through the switch sw1 and the switch sw1', so as to obtain an input voltage vin_ref, and the other end is connected with a common-mode voltage Vcm through the switch sw2 and the switch sw2', so that input voltage sampling is realized; the switch sw4, the switch sw4', the switch sw3 and the switch sw3' are turned off, and the negative feedback circuit formed by connecting the amplifier (102) and the feedback capacitor Cf maintains the output voltage vo_ref unchanged in the last amplifying stage;

the buffer amplifying stage when the ADC is in the digital-to-analog conversion stage; the switch sw1, the switch sw1', the switch sw2 and the switch sw2' are turned off, the switch sw3', the switch sw4 and the switch sw4' are turned on, and at this time, the first capacitor array (101) and the second capacitor array (103) are connected to two ends of the amplifier (102) and are connected in parallel with the feedback capacitor Cf; because one end of the feedback capacitor Cf connected to the amplifier (102) is a high-resistance node, after the initial stabilization process for a plurality of periods, the voltage at two ends of the feedback capacitor Cf is kept to be output stably,

Vo_ref＝K*Vin_refn

wherein K is a scaling factor, i.e. the amplification factor of the buffer, which is related to the way the first capacitor array (101) and the second capacitor array (103) are configured.

6. A fully differential buffer for ADCs based on switched capacitor timing implementation according to claim 1, characterized in that the first capacitor array (101) and the second capacitor array (103) comprise one or more capacitors connected by switches, which are connected in parallel during the sampling phase and in series or in parallel during the amplifying phase to achieve different amplification factors K.

7. The fully differential buffer for ADC based on switched capacitor timing according to claim 6, wherein the different connection modes of the first capacitor array (101) and the second capacitor array (103) in the sampling and amplifying stages can obtain different amplification factors K, which specifically includes the following contents:

in the sampling stage, the capacitor arrays C1-Cn are in parallel connection;

in the amplifying stage, if C1-Cn are connected in series, the amplification factor is increased

K＝n

Different amplification factors can be obtained by adjusting the number n of the capacitors;

in the amplifying stage, if C1-Cn are still connected in parallel, the amplification factor is increased

K＝1

The output voltage of this buffer is thus equal to the output voltage, i.e. the buffer with a magnification of 1.

8. A fully differential buffer for ADC based on switched capacitor timing according to claim 6, wherein the first capacitor array (101) and the second capacitor array (103) can be reduced to a single capacitor Cs, i.e. the sampling capacitor;

in a sampling stage, a sampling capacitor Cs collects an input voltage vin_ref;

in the amplifying stage, the sampling capacitor Cs and the feedback capacitor Cf are connected in parallel, the charge is redistributed to make the two capacitor voltages equal, and when the circuit reaches balance, the vo_ref voltage is finally equal to vin_ref, thus obtaining the amplifying power

K＝1

The output voltage of this buffer is thus equal to the output voltage, i.e. the buffer with a magnification of 1.