CN116594279A - High-speed Time-to-Digital Converter Based on Nested Time Amplification and Automatic Calibration Technology - Google Patents

Abstract

The invention relates to a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology, comprising: the N-stage TDC module, the pulse generator and the digital decoding module; adjacent two stages of TDC modules are connected through a pulse generator to form an N-stage pipeline architecture, and the quantization of each stage of TDC module generates a temperature code and is input to a digital decoding module; the digital decoding module obtains and outputs a digital code Dout after decoding the temperature code. The front N-1 stage TDC modules have the same structure and comprise two cascaded low-level sub-TDC modules; the N-th stage TDC module comprises two cascaded high-order sub-TDC modules. The invention uses an N-stage pipeline architecture, each stage comprises two stages of sub-TDC modules, the use of a time allowance amplifier is avoided, the two stages of sub-TDC modules automatically calibrate the aperture error, higher linearity is realized, and the noise performance is maintained unchanged.

Description

High-speed Time-to-Digital Converter Based on Nested Time Amplification and Automatic Calibration Technology

technical field

The invention belongs to the field of time-to-digital converters, in particular to a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology.

Background technique

As a bridge connecting the analog world and the digital domain, the performance of the analog-to-digital converter limits the performance of the entire system; among them, the time-domain analog-to-digital converter has excellent process adaptability, low power consumption and small area characteristics. With the continuous advancement of technology, the resolution and quantization range of time-to-digital converters (TDC) have been continuously improved, making it successfully used in many fields, and also put forward higher requirements for the quantization speed, precision and linearity of TDC. On-chip mismatch and in-band noise have become key factors limiting TDC performance that cannot be ignored.

Due to the feature that the pipelined time-to-digital converter can be quantized in parallel, it can do multi-stage sub-TDC pipeline work and achieve a higher quantization speed. However, time margin amplifiers are generally used to transfer margin between stages. With the evolution of integrated circuit process nodes to the nanometer level, many problems such as the degradation of MOS tube intrinsic gain lead to relatively large changes in the gain of time margin amplifiers with process, voltage and temperature parameters. Sensitive, the introduction of the margin amplifier leads to high circuit complexity and increased power consumption; in addition, the on-chip mismatch is specifically manifested as the aperture error of the gated delay chain formed by the delay unit, which has not been effectively limited.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the present invention provides a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology. The technical problem to be solved in the present invention is realized through the following technical solutions:

The invention provides a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology, which is characterized in that it includes: an N-level TDC module, a pulse generator and a digital decoding module;

The TDC modules of two adjacent stages are connected through the pulse generator to form an N-stage pipeline architecture, and the quantized output terminals of the TDC modules of each stage are connected to the digital decoding module;

The previous N-1 level TDC modules have the same structure, including two cascaded low-position sub-TDC modules; the N-th level TDC module includes two cascaded high-position sub-TDC modules; the low-position sub-TDC module and the high-position The quantization bits of the TDC module are different;

Each stage of TDC module quantizes the input time signal to generate corresponding temperature code and FULL signal, and the pulse generator connected to it generates a time margin signal according to the difference between the FULL signal and the external Trigger signal, wherein the first The input terminal of the first-stage TDC module inputs the external time signal TIN and the external Trigger signal; the time margin signal generated by the previous stage pulse generator is used as the time signal input by the subsequent stage TDC module; the temperature code generated by each stage TDC module is input To the digital decoding module, the digital decoding module decodes the temperature code to obtain a digital code Dout and outputs it.

In an embodiment of the present invention, the structure of the upper sub-TDC module and the lower sub-TDC module is the same, and the number of quantization bits of the upper sub-TDC module is 1 LSB higher than that of the lower sub-TDC module.

In one embodiment of the present invention, the low-position sub-TDC module includes: OR gate R1, switch S1, switch S2, switch S3, D flip-flop DFF1, D flip-flop DFF2, delay unit t _Q1 , delay unit t _Q2 , Delay unit t _Q3 , delay unit t _Q4 , delay unit t _Q5 , delay unit t _Q6 , delay unit t _Q7 and delay unit t _Q8 ;

Wherein, the first input terminal of the OR gate R1 inputs the external Trigger signal, the second input terminal inputs the time signal, and the output terminal of the OR gate R1 outputs an enable signal EN;

The delay unit t _Q1 , the delay unit t _Q2 , the delay unit t _Q3 , the delay unit t _Q4 , the delay unit t Q5 , the delay unit t _Q6 , the delay unit t _Q7 and the delay unit t _Q7 The delay unit t _Q8 is sequentially connected in series to form a delay chain, and its control terminals are all connected to the output terminals of the OR gate R1;

The input terminal of the delay unit _tQ1 inputs a reset SET signal;

The first end of the switch S1 is connected between the output end of the delay unit _tQ4 and the input end of the delay unit _tQ5 , and the first end of the switch S2 is connected to the output of the delay unit _tQ6 Between the terminal and the input end of the delay unit t _Q7 , the first end of the switch S3 is connected to the output end of the delay unit t _Q8 ;

The second end of the switch S1, the second end of the switch S2, and the second end of the switch S3 are connected and used as the output end of the FULL signal;

The first input end of the D flip-flop DFF1 is connected between the output end of the delay unit t _Q3 and the input end of the delay unit t _Q4 , and the first input end of the D flip-flop DFF2 is connected to the Between the output end of the delay unit _tQ5 and the input end of the delay unit _tQ6 ; the second input end of the D flip-flop DFF1 and the second input end of the D flip-flop DFF2 both input the clock signal CLK;

The output terminal of the D flip-flop DFF1 outputs the first temperature code D0, and the output terminal of the D flip-flop DFF2 outputs the second temperature code D1.

In an embodiment of the present invention, the time signal includes: a primary time signal T ₁ and a secondary time signal T ₂ , and satisfies:

T ₂ =T ₁ +ΔT;

in, t _Q is the delay time of one delay unit.

In one embodiment of the present invention, in the TDC modules of the first N-1 stages,

The first low-level sub-TDC module quantizes the input primary time signal _T1 and the external Trigger signal to generate a primary FULL signal;

The second low-level sub-TDC module quantizes the input secondary time signal _T2 and the primary FULL signal to generate a secondary FULL signal, and inputs the secondary FULL signal as the FULL signal generated by the TDC module to the the pulse generator.

In an embodiment of the present invention, the time margin signal includes: margin information of the first lower sub-TDC module and margin information of the second lower sub-TDC module;

Wherein, the margin information of the first low-position sub-TDC module includes a first aperture error, and the margin information of the second low-position sub-TDC module includes a second aperture error;

The values of the first aperture error and the second aperture error are positive and negative.

Compared with prior art, the beneficial effect of the present invention is:

The high-speed time-to-digital converter based on nested time amplification and automatic calibration technology of the present invention uses an N-stage pipeline architecture, each stage includes two-stage sub-TDC modules, and the output time margin signal carries the margin information of the two-stage sub-TDC , avoiding the use of the time margin amplifier, effectively reducing the complexity and power consumption of the circuit. At the same time, using split calibration technology, the two-stage sub-TDC module automatically calibrates the aperture error, achieving higher linearity while maintaining the same noise performance.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

Fig. 1 is a circuit structure block diagram of a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology provided by an embodiment of the present invention;

FIG. 2 is a circuit structure diagram of a 1.5bit sub-TDC provided by an embodiment of the present invention;

Fig. 3 is the equivalent schematic diagram of the delay unit in the holding phase of the embodiment of the present invention;

FIG. 4 is a schematic diagram of potentials of positive and negative charge transitions of the delay unit in the holding phase of the embodiment of the present invention;

Fig. 5 is a schematic diagram of an aperture error of an embodiment of the present invention;

Fig. 6 is a schematic structural diagram of a TDC module according to an embodiment of the present invention.

Detailed ways

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology proposed according to the present invention will be described below in conjunction with the accompanying drawings and specific implementation methods Describe in detail.

The aforementioned and other technical contents, features and effects of the present invention can be clearly presented in the following detailed description of specific implementations with accompanying drawings. Through the description of specific embodiments, the technical means and effects of the present invention to achieve the intended purpose can be understood more deeply and specifically, but the accompanying drawings are only for reference and description, and are not used to explain the technical aspects of the present invention. program is limited.

Embodiment one

Please refer to FIG. 1 . FIG. 1 is a block diagram of a circuit structure of a high-speed time-to-digital converter based on nested time amplification and automatic calibration technology provided by an embodiment of the present invention.

As shown in the figure, the high-speed time-to-digital converter based on nested time amplification and automatic calibration technology of the present invention is characterized in that it includes: N-level TDC modules, pulse generators and digital decoding modules; adjacent two-level TDC The modules are connected through pulse generators to form an N-level pipeline architecture, and the quantized output terminals of each TDC module are connected to the digital decoding module.

In this embodiment, the first N-1 level TDC modules have the same structure, including two cascaded low-position sub-TDC modules; the N-th level TDC module includes two cascaded high-position sub-TDC modules; The quantization bits of the high-bit sub-TDC modules are different.

In this embodiment, each stage of TDC module quantizes the input time signal to generate corresponding temperature code and FULL signal, and the pulse generator connected to it generates a time margin signal according to the difference between the FULL signal and the external Trigger signal, wherein, The input terminal of the first-stage TDC module inputs the external time signal TIN and the external Trigger signal; the time margin signal generated by the previous stage pulse generator is used as the time signal input by the subsequent stage TDC module; the temperature code generated by each stage TDC module They are all input to the digital decoding module, and the digital decoding module decodes the temperature code to obtain the digital code Dout and output it.

In an optional implementation manner, the upper sub-TDC module and the lower sub-TDC module have the same structure, and the number of quantization bits of the upper sub-TDC module is 1 LSB higher than that of the lower sub-TDC module.

In an optional implementation, in order to achieve redundancy and avoid over-range output digital codes, the first N-1 stages adopt a 1.5-bit cascaded TDC structure, and the Nth-stage TDC module adopts a 2-bit cascaded TDC structure.

Please refer to FIG. 2 . FIG. 2 is a circuit structure diagram of a 1.5-bit sub-TDC provided by an embodiment of the present invention.

As shown in the figure, take the first-stage 1.5bit sub-TDC module as an example, which includes: OR gate R1, switch S1, switch S2, switch S3, D flip-flop DFF1, D flip-flop DFF2, delay unit t _Q1 , delay unit t _Q2 , delay unit t _Q3 , delay unit t _Q4 , delay unit t _Q5 , delay unit t _Q6 , delay unit t _Q7 and delay unit t _Q8 .

In an optional implementation manner, the first input terminal of the OR gate R1 inputs an external Trigger signal, the second input terminal inputs a time signal, and the output terminal of the OR gate R1 outputs an enable signal EN.

In an optional implementation manner, the delay unit t _Q1 , the delay unit t _Q2 , the delay unit t _Q3 , the delay unit t _Q4 , the delay unit t _Q5 , the delay unit t _Q6 , the delay unit t _Q7 and the delay unit t _Q8 are sequentially connected in series A delay chain is formed, and its control terminals are all connected to the output terminal of the OR gate R1; the input terminal of the delay unit t _Q1 inputs a reset SET signal.

In an optional implementation manner, the first end of the switch S1 is connected between the output end of the delay unit _tQ4 and the input end of the delay unit _tQ5 , and the first end of the switch S2 is connected to the output end of the delay unit _tQ6 and the input end of the delay unit t _Q7 , the first end of the switch S3 is connected to the output end of the delay unit t _Q8 ; the second end of the switch S1, the second end of the switch S2 and the second end of the switch S3 are connected and used as The output terminal of the FULL signal.

In an optional implementation, the first input terminal of the D flip-flop DFF1 is connected between the output terminal of the delay unit t _Q3 and the input terminal of the delay unit t _Q4 , and the first input terminal of the D flip-flop DFF2 is connected between the delay Between the output terminal of the unit t _Q5 and the input terminal of the delay unit t _Q6 ; the second input terminal of the D flip-flop DFF1 and the second input terminal of the D flip-flop DFF2 both input the clock signal CLK; the output terminal of the D flip-flop DFF1 outputs The first temperature code D0, the output terminal of the D flip-flop DFF2 outputs the second temperature code D1, and the digital decoding module decodes the temperature code to obtain a digital code Dout and outputs it.

In an optional embodiment, the corresponding output relationship between the temperature code and the digital code of this level is shown in Table 1, wherein, according to the first temperature code D0 and the second temperature code D1, the highest output in the digital decoding module is The digital code of 10 meets the quantitative range requirements.

Table 1 Correspondence between temperature codes and digital codes of this level

D1 D0 Dout L L 00 L h 01 h h 10

Please refer to FIG. 3 and FIG. 4 in conjunction. FIG. 3 is an equivalent schematic diagram of the delay unit in the holding phase of the embodiment of the present invention; FIG. 4 is a schematic diagram of the positive and negative charge transitions of the delay unit in the holding phase of the embodiment of the present invention.

As shown in the figure, when the enable signal EN is at low level, the delay chain is in the hold phase, that is, the delay unit keeps the current information unchanged; the switch S0 is equivalent to a resistor, and the current on the resistor R _inv is zero, that is, the resistor The potential difference across R _inv is zero; this means that the charges of capacitors C _p and C _d are redistributed through resistor R _inv to ensure that the potentials across resistor R _inv are equal. Depending on the direction of the charge transition, the levels on the capacitor C _p and the capacitor C _d will increase or decrease accordingly, that is, the charge positive transition and negative transition.

Furthermore, since the delay chain is affected by the feedthrough of the clock signal CLK during the hold phase, the clock signal CLK is fed through to the output terminal through the parasitic capacitance, resulting in unstable potential held, and a charge transition occurs at the output terminal of the delay unit, resulting in the output The voltage changes and the charge transition varies with the maintained potential. This error is called aperture error.

Please refer to FIG. 5 . FIG. 5 is a schematic diagram of an aperture error of an embodiment of the present invention.

As shown in the figure, the solid line represents the output of the delay unit (Original FULL) under ideal conditions, and the dotted line represents the output of the delay unit (Actual FULL) due to the existence of charge transitions under actual conditions. After the enable signal EN becomes high, the switch is turned on, but the charge that has already transitioned will not return to the position before the transition, which causes the phase information to change, which will cause an error in the time required for the potential to drop to GND . And this error is non-linear. The voltage change caused by the transition is related to the phase during the hold, that is, it is related to the input. It is not a fixed value and cannot be calibrated as a static offset. The direction and quantity of the charge transition in the hold phase are related to the phase of the hold phase. If the influence of noise is not considered, each phase corresponds to an aperture error, so this is a nonlinear error related to the input, which is difficult to pass through simply The first-order calibration to trim. Aperture error causes a positive or negative time error T _skew between Actual FULL and Original FULL. After the error is introduced, the output time margin can be given by the following formula:

T _{IDEA res} = (T _{Actual FULL} - T _Trigger ) - T _skew ; (1)

Among them, T _{IDEA res} is the time margin signal under ideal conditions; T _{Actual FULL} is the FULL signal under actual conditions; T _Trigger is the external Trigger signal under actual conditions; (T _{Actual FULL} -T _Trigger ) is the actual condition The time margin signal is T _{Actual res} ; T _skew is the time error.

Please refer to FIG. 6 , which is a schematic structural diagram of a TDC module according to an embodiment of the present invention.

Since T _skew is related to the input and is not a fixed value, it is a nonlinear error that has a complex impact on T _{IDEA res} , so it needs to be calibrated through the split TDC of this embodiment, that is, two sub-TDCs cascaded module.

In this embodiment, the time signal input to the TDC module includes: a primary time signal T ₁ and a secondary time signal T ₂ , and satisfies:

T ₂ =T ₁ +ΔT; (2)

in, t _Q is the delay time of one delay unit.

As shown in the figure, take the previous N-1 level TDC module as an example. The first low-level sub-TDC module quantizes the input level-1 time signal T ₁ and external Trigger signal to generate a level-1 FULL signal; the second low-level sub-TDC The module quantizes the input secondary time signal T ₂ and the primary FULL signal to generate a secondary FULL signal, and inputs the secondary FULL signal to the pulse generator as the FULL signal generated by the TDC module.

In an optional embodiment, the time margin signal includes: margin information of the first low-order sub-TDC module and margin information of the second low-order sub-TDC module; wherein, the margin information of the first low-order sub-TDC module The amount information includes the first aperture error, and the margin information of the second low-position sub-TDC module includes the second aperture error. After the quantization of the delay chains in the two low-level sub-TDC modules, the maintained phase states are evenly distributed within the range of a delay unit, the values of the first aperture error and the second aperture error are opposite in positive and negative, and the magnitude of the absolute value It is similar, that is, the influence caused by the control error will be partially offset, the influence of the aperture error is weakened, a higher linearity is achieved, and the noise performance remains unchanged.

It is worth noting that since the time margin signal Tout already includes the margin information of the first low-level sub-TDC module and the margin information of the second low-level sub-TDC module, there is no need to use a time margin amplifier to transmit between stages margin, reducing circuit complexity and power consumption.

The high-speed time-to-digital converter based on nested time amplification and automatic calibration technology in the embodiment of the present invention uses an N-stage pipeline architecture, each stage includes two-stage sub-TDC modules, and the output time margin signal carries the remainder of the two-stage sub-TDC Quantitative information avoids the use of time margin amplifiers and effectively reduces circuit complexity and power consumption. At the same time, using split calibration technology, the two-stage sub-TDC module automatically calibrates the aperture error, achieving higher linearity while maintaining the same noise performance.

It should be noted that in this document, relational terms such as first and second etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the terms "comprises", "comprises" or any other variation are intended to cover a non-exclusive inclusion such that an article or device comprising a set of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the article or device comprising said element. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying References to devices or elements must have a particular orientation, be constructed, and operate in a particular orientation and therefore should not be construed as limiting the invention.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (6)

1. A high-speed time-to-digital converter based on nested time-amplification and auto-calibration techniques, comprising: the N-stage TDC module, the pulse generator and the digital decoding module;

adjacent two stages of TDC modules are connected through the pulse generator to form an N-stage pipeline architecture, and the quantization output end of each stage of TDC module is connected with the digital decoding module;

the front N-1 stage TDC modules have the same structure and comprise two cascaded low-level sub-TDC modules; the N-th stage TDC module comprises two cascaded high-level sub-TDC modules; the low-order sub-TDC module is different from the Gao Weizi TDC module in quantization bit number;

each stage of TDC module quantizes an input time signal to generate a corresponding temperature code and a FULL signal, and the pulse generator connected with the temperature code and the FULL signal generates a time allowance signal according to the difference value of the FULL signal and an external Trigger signal, wherein the input end of the first stage of TDC module inputs an external time signal TIN and the external Trigger signal; the time allowance signal generated by the pulse generator of the previous stage is used as the time signal input by the TDC module of the next stage; the temperature code generated by each stage of TDC module is input to the digital decoding module, and the digital decoding module decodes the temperature code to obtain a digital code Dout and outputs the digital code Dout.

2. The high-speed time-to-digital converter based on the nested time-amplification and auto-calibration technique of claim 1, wherein the Gao Weizi TDC module and the low-order sub-TDC module are identical in structure, and the Gao Weizi TDC module has a quantization bit number 1LSB higher than the low-order sub-TDC module.

3. The nested time-amplified and auto-calibration technique-based high-speed time-to-digital converter of claim 1, wherein said low-order sub-TDC module comprises: OR gate R1, switch S2, switch S3, D flip-flop DFF1, D flip-flop DFF2, delay unit t _Q1 Delay unit t _Q2 Delay unit t _Q3 Delay unit t _Q4 Delay (delay)Delay unit t _Q5 Delay unit t _Q6 Delay unit t _Q7 And delay unit t _Q8 ；

The first input end of the or gate R1 inputs the external Trigger signal, the second input end inputs the time signal, and the output end of the or gate R1 outputs an enable signal EN;

the delay unit t _Q1 Said delay unit t _Q2 Said delay unit t _Q3 Said delay unit t _Q4 Said delay unit t _Q5 Said delay unit t _Q6 Said delay unit t _Q7 And the delay unit t _Q8 Sequentially connecting the delay chains in series to form delay chains, wherein the control ends of the delay chains are connected with the output end of the OR gate R1;

the delay unit t _Q1 The input end of the (a) inputs a reset SET signal;

a first end of the switch S1 is connected to the delay unit t _Q4 And the delay unit t _Q5 A first end of the switch S2 is connected to the delay unit t _Q6 And the delay unit t _Q7 A first end of the switch S3 is connected to the delay unit t _Q8 An output terminal of (a);

the second end of the switch S1, the second end of the switch S2 and the second end of the switch S3 are connected and serve as output ends of the FULL signal;

a first input terminal of the D flip-flop DFF1 is connected to the delay unit t _Q3 And the delay unit t _Q4 A first input terminal of the D flip-flop DFF2 is connected to the delay unit t _Q5 And the delay unit t _Q6 Is connected between the input ends of the first and second switches; a second input end of the D trigger DFF1 and a second input end of the D trigger DFF2 are respectively input with a clock signal CLK;

the output end of the D trigger DFF1 outputs a first temperature code D0, and the output end of the D trigger DFF2 outputs a second temperature code D1.

4. A high-speed time-to-digital converter based on nested time-scale up and auto-calibration techniques as claimed in claim 3,

the time signal includes: first-order time signal T ₁ And a secondary time signal T ₂ And satisfies:

T ₂ ＝T ₁ +ΔT；

wherein ,t _Q is the delay time of one delay cell.

5. The high-speed time-to-digital converter based on nested time-amplification and auto-calibration techniques of claim 4, wherein in a top N-1 stage TDC module,

the first low-order sub-TDC module inputs the first-order time signal T ₁ The external Trigger signal is quantized to generate a first-level FULL signal;

the second low-order sub-TDC module inputs the second-order time signal T ₂ And the first-stage FULL signal is quantized to generate a second-stage FULL signal, and the second-stage FULL signal is used as the FULL signal generated by the TDC module and is input to the pulse generator.

6. The nested time-scale and auto-calibration technique-based high-speed time-to-digital converter of claim 5,

the time margin signal includes: the residual information of the first low-order sub-TDC module and the residual information of the second low-order sub-TDC module;

wherein the residual information of the first low-order sub-TDC module includes a first aperture error, and the residual information of the second low-order sub-TDC module includes a second aperture error;

the first aperture error and the second aperture error are opposite in value and positive and negative.