CN116598359B - Trench MOSFET device with integrated junction barrier Schottky diode and manufacturing method - Google Patents

Abstract

The present application discloses a trench MOSFET device with an integrated junction barrier Schottky diode and a manufacturing method. The device includes: an epitaxial layer and a MOSFET structure located on the top of the epitaxial layer; the MOSFET structure includes: a number of cells, a first highly doped P-type region, and a trench; the cell includes a well region, a source region, a second highly doped P-type region, a junction barrier Schottky region including a preset number of third highly doped P-type regions, and a JFET region; the well region and the epitaxial layer form a first PN junction; the source region and the well region form a second PN junction; the well region and the second highly doped P-type region surround the junction barrier Schottky region; the trench is located between each cell, and the first highly doped P-type region wraps the bottom of the trench; the first highly doped P-type region and the epitaxial layer form a third PN junction; the well region and the adjacent first highly doped P-type region form a JFET region. The present application solves the problem that the conduction characteristics of the junction barrier Schottky structure and the MOSFET structure cannot be taken into account when they jointly occupy the active area of the device through the above-mentioned device.

Description

Trench MOSFET device with integrated junction barrier Schottky diode and manufacturing method

Technical Field

The present application relates to the technical field of power semiconductor manufacturing, and in particular to a trench MOSFET device with an integrated junction barrier Schottky diode and a manufacturing method thereof.

Background technique

Basal plane dislocations (BPDs) exist in silicon carbide crystals. Under certain conditions, basal plane dislocations (BPDs) can be converted into stacking faults (SFs). When the body diode in a silicon carbide power MOSFET device is turned on, under bipolar operation, the recombination of electrons and holes will cause the stacking faults (SFs) to continue to expand, resulting in bipolar degradation. This phenomenon increases the on-resistance of the silicon carbide power MOSFET, increases the leakage current in the blocking mode, and increases the on-voltage drop of the body diode, thereby reducing the reliability of the device.

In actual circuit applications, in order to avoid bipolar degradation, designers generally use external reverse parallel Schottky diodes to suppress the body diode in power MOSFET devices. However, for cost considerations, we can embed the junction barrier Schottky diode into each cell unit in the power MOSFET device, and the entire device shares the same terminal structure, which can reduce the total chip size.

For silicon carbide trench power MOSFET devices with integrated junction barrier Schottky diodes inside the cell, the junction barrier Schottky structure and the MOSFET structure jointly occupy the active area of the device, so there is a contradictory relationship of compromise and trade-off between the two. If the two are unbalanced, it will lead to greater MOSFET conduction losses, or make the current conduction capability of the junction barrier Schottky diode weaker, reducing the overall electrical performance of the device.

Summary of the invention

The embodiments of the present application provide a trench MOSFET device with an integrated junction barrier Schottky diode and a manufacturing method, which are used to solve the following technical problems: the junction barrier Schottky structure and the MOSFET structure jointly occupy the active area of the device. If the two are unbalanced, it will cause greater MOSFET conduction losses, or make the current conduction capability of the junction barrier Schottky diode weaker, thereby reducing the practicality of the device.

On the one hand, an embodiment of the present application provides a trench MOSFET device with an integrated junction barrier Schottky diode, characterized in that the device includes: an epitaxial layer and a MOSFET structure located on top of the epitaxial layer; wherein the epitaxial layer is an N-type region; the MOSFET structure includes: a number of cells with the same shape and structure, a first highly doped P-type region, and a trench; each cell includes a well region, a source region, a second highly doped P-type region, a junction barrier Schottky region including a preset number of third highly doped P-type regions, and a JFET region; wherein: the well region is a P-type region, and the source region is an N-type region; the third highly doped P-type region includes a ring-shaped third highly doped P-type region and an island-shaped third highly doped P-type region; the well region is located on the top surface of the epitaxial layer and is adjacent to the epitaxial region. The first PN junction is formed in the layer; the source region and the second highly doped P-type region are both located in the well region on the side surface away from the epitaxial layer, the well region and the source region form a second PN junction, and the source region surrounds the second highly doped P-type region; the junction barrier Schottky region is located in the inner surrounding region of the well region and the source region, and a preset number of third highly doped P-type regions are arranged at equal intervals in the junction barrier Schottky region; the groove is located between each unit cell, the groove cross section between the units is U-shaped, and the bottom corner of the groove is rounded; the first highly doped P-type region wraps the bottom of the groove; the first highly doped P-type region forms a third PN junction with the epitaxial layer; a junction field effect transistor JFET region is formed between the well region and the adjacent first highly doped P-type region.

In one implementation of the present application, the value range of the width of the JFET region and the value range of the spacing of the third highly doped P-type region in the junction barrier Schottky region are both within the same preset range; wherein the preset range is [0.8μm～5μm], and the preset number ranges from 1 to 10.

In one implementation of the present application, the MOSFET structure also includes: an ohmic contact metal and a Schottky contact metal; the ohmic contact metal covers the top of the second highly doped P-type region and a portion of the source region, and simultaneously forms an ohmic contact with the second highly doped P-type region and a portion of the source region at the contact position to suppress the parasitic bipolar transistor effect inside the MOSFET device; the Schottky contact metal covers the top of the junction barrier Schottky region, and forms a Schottky contact at the contact position.

In one implementation of the present application, the MOSFET structure further includes: an insulating gate oxide layer and gate conductive polysilicon; the insulating gate oxide layer covers the inner wall of the trench; and the gate conductive polysilicon fills the trench.

In one implementation of the present application, the MOSFET structure further includes: an insulating dielectric layer; the insulating dielectric layer covers the top of the filled trench and the top of a portion of the source region of each cell.

In one implementation of the present application, the MOSFET structure further includes: a source electrode; the source electrode covers the ohmic contact metal and the Schottky contact metal; and the insulating dielectric layer separates the gate conductive polysilicon from the source metal.

In one implementation of the present application, the device further includes: a silicon carbide substrate, a drain electrode; the top of the silicon carbide substrate contacts the bottom of the epitaxial layer; wherein the silicon carbide substrate is an N-type region; and the drain electrode covers the bottom of the silicon carbide substrate.

In one implementation of the present application, the ion doping concentration in the silicon carbide substrate is greater than the ion doping concentration in the epitaxial layer; the ion doping concentration in the JFET region and the junction barrier Schottky region is greater than or equal to the ion doping concentration of the epitaxial layer.

In one implementation of the present application, the shape of the cell is circular or polygonal.

On the other hand, the embodiment of the present application also provides a method for manufacturing a trench MOSFET device with an integrated junction barrier Schottky diode, characterized in that the manufacturing method includes the following steps: S1. forming a silicon carbide substrate and forming an epitaxial layer on one side of the silicon carbide substrate; S2. forming an enhanced first conductivity type Schottky region on the surface of the epitaxial layer; S3. forming a plurality of second conductivity type well regions on the surface of the epitaxial layer; wherein the first conductivity type is N type and the second conductivity type is P type; S4. forming a plurality of highly doped first conductivity type source regions inside the well region containing the second conductivity type; S5. forming a plurality of trench structures on the surface of the epitaxial layer; S6. forming an enhanced first conductivity type JFET region on the sidewalls of the trench; S7. A plurality of first highly doped P-type regions are formed at the bottom of the trench, and a plurality of second highly doped P-type regions and a third highly doped P-type region of the second conductivity type are formed on the surface of the platform; S8. An insulating gate oxide layer is formed at the bottom and sidewalls of the trench; S9. Gate conductive polysilicon is formed inside the trench to fill the trench, and its height is close to the level with the epitaxial layer platform; S10. A plurality of insulating dielectric layers are formed on the surface of the device; S11. Ohmic contact metal is formed above the highly doped first conductivity type source region and the second highly doped P-type region on the surface of the device; S12. Schottky contact metal is formed above the enhanced Schottky region on the surface of the device; S13. A source electrode is formed on the top of the device; S14. A drain electrode is formed on the other side of the silicon carbide substrate.

The embodiments of the present application provide a trench MOSFET device with an integrated junction barrier Schottky diode and a manufacturing method, which integrates the junction barrier Schottky diode into the cell structure of the trench power MOSFET. Through the layout of circular or polygonal cells, a compromise and trade-off between the performance of the junction barrier Schottky diode and the trench power MOSFET is achieved, thereby improving the comprehensive electrical performance of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

FIG1 is a cross-sectional view of an active region of a trench MOSFET device with an integrated junction barrier Schottky diode provided in an embodiment of the present application;

FIG2 is a schematic diagram of a regular hexagonal cell structure provided in an embodiment of the present application;

FIG3 is a cross-sectional view of an active region of another trench MOSFET device with an integrated junction barrier Schottky diode provided in an embodiment of the present application;

FIG4 is a schematic diagram of a circular cell structure provided in an embodiment of the present application;

FIG5 is a schematic diagram of a regular quadrilateral cell structure provided in an embodiment of the present application;

FIG6 is a schematic diagram of another regular quadrilateral cell structure provided in an embodiment of the present application;

FIG. 7 is a schematic diagram of step 1 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG8 is a schematic diagram of step 2 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG9 is a schematic diagram of step 3 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG10 is a schematic diagram of step 4 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG11 is a schematic diagram of step 5 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG12 is a schematic diagram of step 6 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG13 is a schematic diagram of step 7 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG14 is a schematic diagram of step 8 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG15 is a schematic diagram of step 9 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG16 is a schematic diagram of step 10 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG17 is a schematic diagram of step 11 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG18 is a schematic diagram of step 12 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG19 is a schematic diagram of step 13 of a method for manufacturing a MOSFET device provided in an embodiment of the present application;

FIG20 is a schematic diagram of step 2 of another MOSFET device manufacturing method provided in an embodiment of the present application;

FIG21 is a schematic diagram of a regular hexagonal cell structure of an island-shaped third highly doped P-type region provided in an embodiment of the present application;

FIG22 is a cross-sectional view of an active region of a trench MOSFET device of an island-shaped third highly doped P-type region with an integrated junction barrier Schottky diode provided by an embodiment of the present application;

23 is a cross-sectional view of an active region of a trench MOSFET device of another island-shaped third highly doped P-type region with an integrated junction barrier Schottky diode provided by an embodiment of the present application;

Description of reference numerals:

Cell 10; silicon carbide substrate 101; epitaxial layer 102; well region 103; source region 104; second highly doped P-type region 105; insulating gate oxide layer 106; gate conductive polysilicon 107; insulating dielectric layer 108; ohmic contact metal 109; Schottky contact metal 110; source electrode 111; drain electrode 112; JFET region 113; junction barrier Schottky region 114; first PN junction 115; second PN junction 116; trench 118 first highly doped P-type region 118; third PN junction 119; ring-shaped third highly doped P-type region 120; island-shaped third highly doped P-type region 121.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

The embodiments of the present application provide a trench MOSFET device with an integrated junction barrier Schottky diode and a manufacturing method, which are used to solve the following technical problems: the junction barrier Schottky structure and the MOSFET structure jointly occupy the active area of the device. If the two are unbalanced, it will cause greater MOSFET conduction losses, or make the current conduction capability of the junction barrier Schottky diode weak, thereby reducing the availability of the device.

The technical solution proposed in the embodiments of the present application is described in detail below with reference to the accompanying drawings.

FIG1 is a cross-sectional view of an active region of a trench MOSFET device with an integrated junction barrier Schottky diode provided in an embodiment of the present application. As shown in FIG1 , the trench MOSFET device with an integrated junction barrier Schottky diode includes an epitaxial layer 102; wherein the epitaxial layer is an N-type region. In addition, as shown in FIG1 , a MOSFET structure is disposed on top of the epitaxial layer 102.

It should be noted that, under the same device area, due to the circular and polygonal cell design of the MOSFET device, a higher channel width and total area of the junction field effect transistor JFET region can be achieved, thereby having a lower specific on-resistance. Therefore, the cell shape in the embodiment of the present application is designed to be polygonal or circular.

FIG2 is a schematic diagram of a regular hexagonal cell structure provided by an embodiment of the present application. Taking the regular hexagonal cell structure shown in FIG2 as an example, the cross-sectional view corresponding to the dotted line AA' in FIG2 is a cross-sectional view of the active area of a trench MOSFET device with an integrated junction barrier Schottky diode shown in FIG1. Combining FIG1 and FIG2, it can be seen that the MOSFET structure located at the top of the epitaxial layer includes: a plurality of cells 10 with the same shape and structure, a first highly doped P-type region 118, and a groove 117; each cell 10 includes: a well region 103, a source region 104, a second highly doped P-type region 105, a junction barrier Schottky region 114 including a preset number of annular third highly doped P-type regions 120, and a JFET region 113; the groove 117 is located between each cell 10, and the first highly doped P-type region 118 is located at the bottom of the groove 117.

It should also be noted that, since there is a first highly doped P-type region 118 at the bottom of the trench 117, the two overlap in the top view of FIG. 2. The solid line in FIG. 2 represents the trench boundary, and the double-dash line represents the boundary projection of the first highly doped P-type region 118 at the bottom of the trench on the platform portion of the epitaxial layer. At the same time, the well region 103 is blocked by the source region 104 and the second highly doped P-type region 105, and thus cannot be shown in FIG. 2.

As shown in Fig. 2, the shape of the boundary of the groove 117, the source region 104, the second highly doped P-type region 105, the annular third highly doped P-type region 120 and the junction barrier Schottky region 114 are all regular hexagons, and the center points coincide. In conjunction with Fig. 1, it can be seen that the shape of the well region 103 of the cell 10 is also a regular hexagon, and the center points are the same as those of other structures of the cell 10.

Furthermore, as shown in FIG1 , the structure of each cell 10 is as follows: the well region 103 is located on the top surface of the epitaxial layer 102, and forms a first PN junction 115 with the epitaxial layer 102; the source region 104 and the second highly doped P-type region 105 are both located on the surface of the well region 103 on the side facing away from the epitaxial layer 102, the well region 103 and the source region 104 form a second PN junction 116, and the source region 104 surrounds the second highly doped P-type region 105; the junction barrier Schottky region 114 is located in the inner surrounding region of the well region 103 and the source region 104, and a preset number of annular third highly doped P-type regions 120 are arranged at equal intervals in the junction barrier Schottky region 114.

Furthermore, the trench 117 is located between each cell 10, the cross section of the trench between the cells 10 is U-shaped, and the bottom corner of the trench 117 is rounded; the first highly doped P-type region 118 wraps the bottom of the trench 117; the first highly doped P-type region 118 contacts the epitaxial layer 102, and forms a third PN junction 119 at the contact position;

Furthermore, a junction field effect transistor (JFET) region 113 is formed between the well region 103 of the cell 10 and the adjacent first highly doped P-type region 118 .

Further, as shown in Fig. 2, the cross-sectional view corresponding to the dotted line BB' in Fig. 2 is a cross-sectional view of the active region of another trench MOSFET device with an integrated junction barrier Schottky diode shown in Fig. 3. As can be seen from Figs. 1 and 3, the ion implantation depth of the source region 104 in the cell 10 is less than the ion implantation depth of the well region 103, and the ion implantation depth of the second highly doped P-type region 105 can be less than, equal to, or greater than the ion implantation depth of the well region 103.

It should be noted that the well region 103 , the second highly doped P-type region 105 , the first highly doped P-type region 118 , and the annular third highly doped P-type region 120 are all P-type regions, and the source region 104 is an N-type region.

In one embodiment of the present application, the ion doping concentration range of the well region 103 is: 5E15cm ^-3 ~ 1E19cm ^-3 ; the ion doping concentration range of the source region 104 is: 1E18cm ^-3 ~ 1E22cm ^-3 ; the ion doping concentration range of the second highly doped P-type region 105, the first highly doped P-type region 118, and the annular third highly doped P-type region 120 is: 1E18cm ^-3 ~ 1E22 cm ^-3 .

It should be noted that, due to the design of the width n and ion doping concentration of the JFET region 113, it is necessary to ensure that the MOSFET has a small on-resistance, and in the blocking mode, the well region 103 and the adjacent first highly doped P-type region 118 can play an effective electric field shielding effect to ensure the reliability of the device. Similarly, the ion doping concentration in the junction barrier Schottky region 114 and the width s of the Schottky sub-region separated by a preset number of annular third highly doped P-type regions 120 in the junction barrier Schottky region 114 need to ensure that the junction barrier Schottky diode has sufficient current conduction capability, and in the blocking mode, the second highly doped P-type region 105 and the adjacent annular third highly doped P-type region 120, or the annular third highly doped P-type region 120 can play an effective electric field shielding effect to ensure the reliability of the device. Therefore, in the embodiment of the present application, the value range of the width n of the JFET region 113 and the value range of the width s of the Schottky sub-region are both within the preset range; the ion doping concentration in the JFET region 113 and the ion doping concentration in the junction barrier Schottky region 114 are both greater than or equal to the ion doping concentration of the epitaxial layer 102. It can be understood that the ion doping concentration in the junction barrier Schottky region 114 described here is the ion doping concentration in the Schottky sub-region separated by a preset number of annular third highly doped P-type regions 120, and does not include the annular third highly doped P-type region 120.

In one embodiment of the present application, the preset interval is 0.8 um to 5 um; the ion doping concentration range in the JFET region 113 and the Schottky region 114 is 1E15 cm ⁻³ to 5E17 cm ⁻³ .

In one embodiment of the present application, the trench MOSFET device with integrated junction barrier Schottky diode further includes: a silicon carbide substrate 101 and a drain electrode 112 .

As shown in FIG. 1 , the top of the silicon carbide substrate 101 contacts the bottom of the epitaxial layer 102 ; wherein the silicon carbide substrate 101 is an N-type region; the drain electrode 112 covers the bottom of the silicon carbide substrate 101 ; and the ion doping concentration in the silicon carbide substrate 101 is greater than the ion doping concentration in the epitaxial layer 102 .

In one embodiment of the present application, the ion doping concentration of the silicon carbide substrate 101 is in the range of 1E18 cm ⁻³ to 1E20 cm ⁻³ , and the ion doping concentration of the epitaxial layer 102 is in the range of 1E14 cm ⁻³ to 1E17 cm ⁻³ .

In one embodiment of the present application, the MOSFET structure located on the top of the epitaxial layer further includes: an ohmic contact metal 109 and a Schottky contact metal 110 .

As shown in Fig. 1, the ohmic contact metal 109 covers the top of the second highly doped P-type region 105 and a portion of the source region 104, and forms an ohmic contact with the second highly doped P-type region 105 and a portion of the source region 104 at the contact position to suppress the parasitic bipolar transistor effect inside the MOSFET device. The Schottky contact metal 110 covers the top of the junction barrier Schottky region 114, and forms a Schottky contact at the contact position.

In one embodiment of the present application, the MOSFET structure located on the top of the epitaxial layer further includes: an insulating gate oxide layer 106 and a gate conductive polysilicon 107 .

As shown in FIG1 , the insulating gate oxide layer 106 covers the inner wall of the trench 117; the gate conductive polysilicon 107 fills the trench 117. It can be understood that the gate conductive polysilicon 107 is filled in the trench 117 that has been covered with the gate insulating oxide layer 106, and the top of the trench is flush with the platform height of the epitaxial layer 102 after being filled.

In one embodiment of the present application, the MOSFET structure located on the top of the epitaxial layer further includes: an insulating dielectric layer 108 .

As shown in FIG. 1 , the insulating dielectric layer 108 covers the top of the filled trench 117 and a portion of the source region 104 of each cell 10 .

In one embodiment of the present application, the trench MOSFET device with integrated junction barrier Schottky diode further includes: a source electrode 111 .

As shown in FIG. 1 , the source electrode 111 covers the ohmic contact metal 109 and the Schottky contact metal 110 ; the insulating dielectric layer 108 separates the gate conductive polysilicon 107 from the source metal 104 .

FIG4 is a schematic diagram of a circular cell structure provided in an embodiment of the present application. As shown in FIG4, the preset number is one, and the shape of the boundary of the groove 117, the source region 104, the second highly doped P-type region 105, the annular third highly doped P-type region 120 and the Schottky region 114 are all concentric ring structures. The cross-sectional view corresponding to the dotted line AA' in FIG4 is a cross-sectional view of the active area of a trench MOSFET device with an integrated junction barrier Schottky diode shown in FIG1; the cross-sectional view corresponding to the dotted line BB' in FIG4 is another cross-sectional view of the active area of a trench MOSFET device with an integrated junction barrier Schottky diode shown in FIG3.

FIG5 is a schematic diagram of a regular quadrilateral cell structure provided in an embodiment of the present application. As shown in FIG5, the preset number is one, and the shape of the boundary of the groove 117, the source region 104, the second highly doped P-type region 105, the annular third highly doped P-type region 120 and the Schottky region 114 are all concentric regular quadrilateral structures. In addition, the regular quadrilateral cell arrangement shown in FIG5 is an alternating arrangement of regular quadrilateral cells in two adjacent rows or two adjacent columns. The cross-sectional view corresponding to the dotted line AA' in FIG5 is a cross-sectional view of the active area of a trench MOSFET device of an integrated junction barrier Schottky diode shown in FIG1; the cross-sectional view corresponding to the dotted line BB' in FIG5 is a cross-sectional view of the active area of another trench MOSFET device of an integrated junction barrier Schottky diode shown in FIG3.

FIG6 is a schematic diagram of a regular quadrilateral cell structure provided in an embodiment of the present application. As shown in FIG6, the preset number is one, and the shape of the boundary of the groove 117, the source region 104, the second highly doped P-type region 105, the annular third highly doped P-type region 120 and the Schottky region 114 are all concentric regular quadrilateral structures. In addition, the regular quadrilateral cell arrangement shown in FIG6 is that the regular quadrilateral cells in each row and column are aligned. The cross-sectional view corresponding to the dotted line AA' in FIG6 is a cross-sectional view of the active area of a trench MOSFET device of an integrated junction barrier Schottky diode shown in FIG1; the cross-sectional view corresponding to the dotted line BB' in FIG6 is another cross-sectional view of the active area of a trench MOSFET device of an integrated junction barrier Schottky diode shown in FIG3.

It should be noted that there is only one annular third highly doped P-type region in Figures 2, 4, 5 and 6 of the embodiments of the present application, but since the cross-sectional structure will cut into both sides of the annular third highly doped P-type region, the cross-sections of Figures 1 and 3 show that there are two third highly doped P-type regions in the junction barrier Schottky region 114.

It should also be noted that when the preset number is 1, the third highly doped P-type region can also be an island-shaped third highly doped P-type region. Figure 21 is a schematic diagram of a regular hexagonal cell structure of an island-shaped third highly doped P-type region provided in an embodiment of the present application. As shown in Figure 21, the third highly doped P-type region is an island-shaped third highly doped P-type region 121. It can be understood that the cross-sectional view corresponding to the dotted line AA' in Figure 21 is a cross-sectional view of the active area of a trench MOSFET device of an integrated junction barrier Schottky diode in an island-shaped third highly doped P-type region shown in Figure 22; the cross-sectional view corresponding to the dotted line BB' in Figure 21 is another cross-sectional view of the active area of a trench power MOSFET device of an integrated junction barrier Schottky diode in an island-shaped third highly doped P-type region shown in Figure 23.

As a feasible implementation method, the manufacturing method of the trench power MOSFET device with integrated Schottky diode of the present application is shown in FIGS. 7 to 20 , and the manufacturing method mainly includes the following steps:

1. As shown in FIG. 7 , a substrate 101 and an epitaxial layer 102 are formed;

2. As shown in FIG. 8 or FIG. 20 , a reinforced first conductivity type Schottky region 114 is formed on the surface of the epitaxial layer 102 ;

3. As shown in FIG. 9 , a plurality of well regions 103 of the second conductivity type are formed on the surface of the epitaxial layer 102 ; wherein the first conductivity type is N type and the second conductivity type is P type;

4. As shown in FIG. 10 , a plurality of highly doped source regions 104 of the first conductivity type are formed inside the well region 103 containing the second conductivity type;

5. As shown in FIG. 11 , a plurality of trench structures 117 are formed on the surface of the epitaxial layer 102;

6. As shown in FIG. 12 , a reinforced first conductivity type JFET region 113 is formed on the sidewall of the trench 117 ;

7. As shown in FIG. 13 , a plurality of first highly doped P-type regions 118 are formed at the bottom of the trench 117 , and a plurality of second highly doped P-type regions 105 and a third highly doped P-type region 120 of the second conductivity type are formed on the surface of the platform;

8. As shown in FIG. 14 , an insulating gate oxide layer 106 is formed on the bottom and sidewalls of the trench 117;

9. As shown in FIG. 15 , a gate conductive polysilicon 107 is formed inside the trench 117 to fill the trench, and its height is close to the level with the platform of the epitaxial layer 102;

10. As shown in FIG. 16 , a plurality of insulating dielectric layers 108 are formed on the surface of the device;

11. As shown in FIG. 17 , an ohmic contact metal 109 is formed on the highly doped first conductivity type source region 104 and the second highly doped P type region 105 on the surface of the device;

12. As shown in FIG. 17 , a Schottky contact metal 110 is formed above the enhanced Schottky region 114 on the surface of the device;

13. As shown in FIG18 , the source electrode 111 is formed on the top of the device;

14. As shown in FIG. 19 , a drain electrode 112 is formed on the back side of the substrate 101 , and the drain electrode is also an ohmic contact metal.

Among them, the step of forming the substrate 101 includes using N+ type SiC as the substrate. The step of forming the epitaxial layer 102 includes forming an epitaxial layer made of N-type silicon carbide on the surface of the substrate. In the embodiment of the present application, as shown in FIG8, the first step of forming the first type of strengthening the 114 region includes forming an epitaxial layer made of silicon carbide with a higher N-type doping on the chip surface. As shown in FIG20, the second step of forming the first type of strengthening the 114 region includes depositing a mask layer 200, photolithography and etching the mask layer to form a pattern transfer. The step of forming the first type of strengthening the 114 region includes performing ion implantation on the chip surface, thereby realizing N-type impurity doping at a specific surface portion of the epitaxial layer (the region where the mask layer opens a window), and the doping impurity type can be nitrogen or phosphorus. The step of forming the second conductivity type well region 103 includes depositing a mask layer 201, photolithography and etching the mask layer to form a pattern transfer. The step of forming the second conductivity type well region 103 includes performing ion implantation on the chip surface, thereby realizing P-type impurity doping at a specific surface portion of the epitaxial layer (the region where the mask layer opens a window), and the doping impurity type can be aluminum or boron. The step of forming a highly doped first conductivity type source region 104 includes depositing a mask layer 202, and photolithographing and etching the mask layer to form a pattern transfer. The step of forming a highly doped first conductivity type source region 104 includes performing ion implantation on the chip surface, thereby achieving N-type impurity doping at a specific surface portion of the epitaxial layer (the region where the mask layer has a window), and the doping impurity type may be nitrogen or phosphorus. The step of forming a groove structure 117 includes depositing a mask layer 203, and photolithographing and etching the mask layer to form a pattern transfer. The step of forming a groove structure 117 includes etching on the chip surface, thereby forming a groove structure at a specific surface portion of the epitaxial layer (the region where the mask layer has a window). The step of forming a strengthened first type 113 region includes using the mask layer 203, thereby achieving strengthened N-type impurity doping at a specific surface portion of the epitaxial layer (the sidewall of the groove), and the doping impurity type may be nitrogen or phosphorus. The step of forming a plurality of highly doped second conductivity type regions 105, regions 118, and regions 120 includes photolithographing and etching the mask layer 203 again to form a pattern transfer. The step of forming a plurality of highly doped second conductive type regions 105, region 118 and region 120 includes etching on the surface of the chip, thereby achieving P-type impurity doping at a specific portion of the surface of the epitaxial layer (the region where the mask layer opens a window), and the doping impurity type can be aluminum or boron. The step of forming a gate oxide layer 106 includes forming an oxide at the bottom and sidewalls of the trench. The step of forming a gate conductive polysilicon 107 includes depositing polysilicon on the top of the device. The step of forming a gate conductive polysilicon 107 includes photolithography and etching, and the height of the polysilicon in the final trench is similar to or slightly lower than the silicon carbide platform. The step of forming an insulating dielectric layer 108 includes dielectric layer growth, photolithography, and etching the dielectric layer to form a source contact window. The step of forming an ohmic contact metal 109 and a Schottky contact metal 110 includes depositing metal on the top of the epitaxial layer containing the dielectric layer. The step of forming an ohmic contact metal 109 and a Schottky contact metal 110 includes annealing the metal, and simultaneously forming an ohmic contact and a Schottky metal at the interface where the metal is in direct contact with the surface of the epitaxial layer. The step of forming the ohmic contact metal 112 includes depositing metal on the back side of the substrate. The step of forming the ohmic contact metal 112 includes annealing the metal on the back side of the substrate to form an ohmic contact between the metal and the surface of the substrate.

In one embodiment, when the doping concentration of the enhanced first conductivity type JFET region 113 and the enhanced first conductivity type Schottky region 114 is the same as that of the epitaxial layer, no additional process steps are required for ion implantation or double-layer epitaxy. In this case, the manufacturing method steps are as follows:

1. forming a substrate 101;

2. Forming an epitaxial layer 102;

3. Forming a plurality of well regions 103 of the second conductivity type on the surface of the epitaxial layer 102;

4. forming a plurality of highly doped regions 104 of the first conductivity type inside the well region 103 containing the second conductivity type;

5. Forming a plurality of trench structures 117 on the surface of the epitaxial layer 102;

6. Form a plurality of highly doped second conductivity type regions 118 at the bottom of the trench, and form a plurality of highly doped second conductivity type regions 105 and a third highly doped P-type region 120 of the second conductivity type on the surface of the platform;

7. Forming an oxide layer 106 at the bottom and sidewalls of the trench;

8. Form gate polysilicon 107 inside the trench, fill the trench, and its height is close to the same level as the platform;

9. Forming a plurality of insulating dielectric layers 108 on the surface of the device;

10. Form an ohmic contact metal 109 on the highly doped first conductive type region 104 and the highly doped second conductive type region 105 on the surface of the device;

11. Forming a Schottky contact 110 above the enhanced region 114 on the device surface;

12. The source electrode 111 is formed on the top of the device;

13. An ohmic contact metal 112 is formed on the back side of the substrate;

Among them, the formation of the highly doped first conductivity type source region 104 can also be carried out through a self-alignment process, using the existing mask layer 201 to form a mask layer 202, and etching the mask layer to form a pattern transfer. The enhanced first conductivity type region 113 and the enhanced first conductivity type region 114 can be formed simultaneously through the same process step, or they can be formed in steps. The highly doped second conductivity type region 105 and the highly doped second conductivity type region 118 can be formed simultaneously through the same process step, or they can be formed in steps. The formation of the ohmic contact metal 109 and the Schottky contact metal 110 can be formed simultaneously through the same process step, or they can be formed in steps.

In addition, in the manufacturing method of the MOSFET device, the formation order of the well region 103, the source region 104, the first highly doped P-type region 105, the second highly doped P-type region 118, the third highly doped P-type region 120 of the second conductivity type, the JFET region 113, the Schottky region 114, and the trench structure 117 can be adjusted according to process requirements.

In one embodiment, the manufacturing method sequence may be as follows:

1. forming a substrate 101;

2. Forming an epitaxial layer 102;

3. Forming a reinforced first conductive type region 114 on the surface of the epitaxial layer 102;

4. Forming a plurality of highly doped second conductivity type regions 105 and second conductivity type regions 120 on the platform surface;

5. Forming a plurality of well regions 103 of the second conductivity type on the surface of the epitaxial layer 102;

6. Forming a plurality of highly doped regions 104 of the first conductivity type inside the well region 103 containing the second conductivity type;

7. Forming a plurality of trench structures 117 on the surface of the epitaxial layer;

8. Forming a reinforced first conductive type region 113 on the sidewall of the trench structure 117;

9. Forming a plurality of highly doped second conductivity type regions 118 at the bottom of the trench;

10. Forming an oxide layer 106 at the bottom and sidewalls of the trench;

11. Form gate polysilicon 107 inside the trench, fill the trench, and its height is close to the same level as the platform;

12. Forming a plurality of insulating dielectric layers 108 on the surface of the device;

13. An ohmic contact metal 109 is formed on the highly doped first conductive type region 104 and the highly doped second conductive type region 105 on the surface of the device;

14. Forming a Schottky contact 110 above the enhanced region 114 on the device surface;

15. The source electrode 111 is formed on the top of the device;

16. An ohmic contact metal 112 is formed on the back side of the substrate.

In another embodiment, the manufacturing method sequence may also be as follows:

1. forming a substrate 101;

2. Forming an epitaxial layer 102;

3. Forming a plurality of highly doped second conductivity type regions 105 and second conductivity type regions 120 on the surface of the platform;

4. Forming a plurality of well regions 103 of the second conductivity type on the surface of the epitaxial layer 102;

5. Form a plurality of highly doped regions 104 of the first conductivity type in the well region 103 containing the second conductivity type;

6. Forming a reinforced first conductive type region 114 on the surface of the epitaxial layer 102;

7. Forming a plurality of trench structures 117 on the surface of the epitaxial layer 102;

8. Forming a reinforced first conductive type region 113 on the sidewall of the trench structure 117;

9. Forming a plurality of highly doped second conductivity type regions 118 at the bottom of the trench;

10. Forming an oxide layer 106 at the bottom and sidewalls of the trench;

11. Form gate polysilicon 107 inside the trench, fill the trench, and its height is close to the same level as the platform;

12. Forming a plurality of insulating dielectric layers 108 on the surface of the device;

13. An ohmic contact metal 109 is formed on the highly doped first conductive type region 104 and the highly doped second conductive type region 105 on the surface of the device;

14. Forming a Schottky contact 110 above the enhanced region 114 on the device surface;

15. The source electrode 111 is formed on the top of the device;

16. An ohmic contact metal 112 is formed on the back side of the substrate.

In another embodiment, the manufacturing method sequence may also be as follows:

1. forming a substrate 101;

2. Forming an epitaxial layer 102;

3. Forming a plurality of trench structures 117 on the surface of the epitaxial layer 102;

4. Forming a reinforced first conductive type region 113 on the sidewall of the trench structure 117;

5. Forming a plurality of highly doped second conductivity type regions 118 at the bottom of the trench;

6. Forming a reinforced first conductive type region 114 on the surface of the epitaxial layer 102;

7. Form a plurality of highly doped second conductivity type regions 105 and second conductivity type regions 120 on the surface of the platform;

8. Forming a plurality of well regions 103 of the second conductivity type on the surface of the epitaxial layer 102;

9. Form a plurality of highly doped regions 104 of the first conductivity type in the well region 103 containing the second conductivity type;

10. Forming an oxide layer 106 at the bottom and sidewalls of the trench;

11. Form gate polysilicon 107 inside the trench, fill the trench, and its height is close to the same level as the platform;

12. Forming a plurality of insulating dielectric layers 108 on the surface of the device;

13. An ohmic contact metal 109 is formed on the highly doped first conductive type region 104 and the highly doped second conductive type region 105 on the surface of the device;

14. Forming a Schottky contact 110 above the enhanced region 114 on the device surface;

15. The source electrode 111 is formed on the top of the device;

16. An ohmic contact metal 112 is formed on the back side of the substrate.

The trench MOSFET device with an integrated junction barrier Schottky diode provided in the embodiment of the present application has a polygonal or circular cell design and introduces a trench design, which can balance the proportion of the junction barrier Schottky structure and the MOSFET structure occupied by the device active area, achieve a higher channel width, total JFET area and total Schottky conduction area, thereby making the MOSFET structure and the Schottky structure have lower conduction losses and improving the comprehensive electrical performance of the device.

Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (8)

1. A trench MOSFET device incorporating a junction barrier schottky diode, said device comprising:

the epitaxial layer and the MOSFET structure are positioned on the top of the epitaxial layer; the epitaxial layer is an N-type region;

the MOSFET structure comprises: a plurality of cells with the same shape and structure, a first highly doped P-type region and a groove;

Each cell comprises a well region, a source region, a second highly doped P-type region, a junction barrier Schottky region comprising a preset number of third highly doped P-type regions and a JFET region; wherein: the well region is a P-type region, and the source region is an N-type region; the third highly doped P-type region comprises an annular third highly doped P-type region and an island-shaped third highly doped P-type region;

the well region is positioned on the top surface of the epitaxial layer and forms a first PN junction with the epitaxial layer;

The source electrode region and the second highly doped P-type region are both positioned on one side surface, away from the epitaxial layer, of the well region, a second PN junction is formed between the well region and the source electrode region, and the source electrode region surrounds the second highly doped P-type region;

The junction barrier Schottky region is positioned in the surrounding area on the inner sides of the well region and the source region, and a preset number of third highly doped P-type regions are arranged in the junction barrier Schottky region at equal intervals;

the grooves are positioned among cells, the cross sections of the grooves among the cells are U-shaped, and the corners at the bottom of the grooves are fillets; the first highly doped P-type region wraps the bottom of the groove;

The first highly doped P-type region and the epitaxial layer form a third PN junction;

forming a Junction Field Effect Transistor (JFET) region between the well region and the adjacent first highly doped P-type region;

Wherein the device further comprises: a silicon carbide substrate and a drain electrode;

the top of the silicon carbide substrate is contacted with the bottom of the epitaxial layer; wherein the silicon carbide substrate is an N-type region;

the drain electrode covers the bottom of the silicon carbide substrate;

Wherein the ion doping concentration in the silicon carbide substrate is greater than the ion doping concentration in the epitaxial layer;

and the ion doping concentration in the JFET region and the junction barrier Schottky region is greater than or equal to that of the epitaxial layer.

2. The trench MOSFET device integrated with a junction barrier schottky diode of claim 1, wherein,

The value range of the width of the JFET region and the value range of the interval of the third high-doped P-type region in the junction barrier Schottky region are both in the same preset interval; wherein the preset interval is [ 0.8-5 mu m ], and the preset number is 1-10.

3. The trench MOSFET device of claim 1, wherein said MOSFET structure further comprises: ohmic contact metal, schottky contact metal;

the ohmic contact metal covers the top of the second highly doped P-type region and part of the source electrode region, and forms ohmic contact with the second highly doped P-type region and part of the source electrode region at the contact position at the same time so as to inhibit parasitic bipolar transistor effect in the MOSFET device;

The schottky contact metal covers the top of the junction barrier schottky region and forms a schottky contact at the contact location.

4. The trench MOSFET device of claim 1, wherein said MOSFET structure further comprises: insulating the gate oxide layer from the gate conductive polysilicon;

The insulating gate oxide layer covers the inner wall of the groove;

the gate conductive polysilicon fills the trench.

5. The trench MOSFET device of claim 4, wherein said MOSFET structure further comprises: an insulating dielectric layer;

And the insulating medium layer covers the top of the filled groove and the top of part of the source electrode area of each cell.

6. The trench MOSFET device of claim 5, wherein said MOSFET structure further comprises: a source electrode;

the source electrode is covered on the ohmic contact metal and the Schottky contact metal;

the insulating dielectric layer separates the gate conductive polysilicon from the source metal.

7. The trench MOSFET device of claim 1, wherein said cell is circular or polygonal in shape.

8. A method for manufacturing a trench MOSFET device incorporating a junction barrier schottky diode, characterized in that it is used for manufacturing a trench MOSFET device incorporating a junction barrier schottky diode according to any of claims 1-7, comprising the steps of:

S1, forming a silicon carbide substrate, and forming an epitaxial layer on one surface of the silicon carbide substrate;

s2, forming a reinforced Schottky region of the first conductivity type on the surface of the epitaxial layer;

S3, forming a plurality of well regions of the second conductivity type on the surface of the epitaxial layer; wherein the first conductivity type is N type, and the second conductivity type is P type;

S4, forming a plurality of highly doped source regions of the first conductivity type inside the well region containing the second conductivity type;

s5, forming a plurality of groove structures on the surface of the epitaxial layer;

S6, forming a reinforced JFET region of a first conductivity type on the side wall of the groove;

S7, forming a plurality of first high-doped P-type regions at the bottom of the groove, and forming a plurality of second high-doped P-type regions and third high-doped P-type regions of the second conductivity type on the surface of the platform;

s8, forming an insulating gate oxide layer at the bottom and the side wall of the groove;

s9, forming grid conductive polysilicon in the groove, filling the groove, and enabling the height of the grid conductive polysilicon to be close to the position flush with the epitaxial layer platform;

s10, forming a plurality of insulating medium layers on the surface of the device;

s11, forming ohmic contact metal above a source region of the high doping first conductivity type and a second high doping P-type region on the surface of the device;

s12, forming a Schottky contact metal above the reinforced Schottky region of the surface of the device;

s13, forming a source electrode at the top of the device;

S14, forming a drain electrode on the other surface of the silicon carbide substrate.