CN116598892A - Semiconductor element with thyristor inhibition layer - Google Patents

Abstract

The invention provides a semiconductor element with a thyristor suppression layer, which relates to the technical field of semiconductor optoelectronic devices, including a substrate, a first n-type semiconductor layer, a second n-type semiconductor layer, and a thyristor suppression layer arranged in sequence from bottom to top , a quantum well layer and a p-type semiconductor layer; the thyristor suppression layer is composed of a first thyristor suppression layer, a second thyristor suppression layer and a third thyristor suppression layer from bottom to top; by inserting a thyristor suppression layer, In the thyristor suppression layer, three layers with different C content concentrations, C content showing a double-step downward trend, and a semiconductor structure combination of Si doping concentration, H content concentration and O content concentration are designed to suppress deep energy level defect centers and PN interlacing Interjunction capacitance is generated to reduce the generation probability of the thyristor from 1 to 5% to 0, and solve the problem of inconsistency in lighting during the use of the semiconductor light-emitting element.

Description

A kind of semiconductor element with thyristor suppression layer

technical field

The invention relates to the technical field of semiconductor optoelectronic devices, in particular to a semiconductor element with a thyristor suppression layer.

Background technique

Semiconductor elements, especially semiconductor light-emitting elements, have a wide range of adjustable wavelengths, high luminous efficiency, energy saving and environmental protection, and can be used for more than 100,000 hours. Long life, small size, multiple application scenarios, and strong designability have gradually replaced Incandescent lamps and fluorescent lamps have grown into light sources for ordinary household lighting and are widely used in new scenarios, such as indoor high-resolution displays, outdoor displays, Mini-LEDs, Micro-LEDs, mobile phone TV backlights, backlighting, street lights, automobiles Headlights, daytime running lights, interior ambient lights, flashlights and other application fields.

Traditional nitride semiconductors are grown on sapphire substrates, and the lattice mismatch and thermal mismatch are large, resulting in high defect density and polarization effects, resulting in non-radiative recombination centers, and reducing the luminous efficiency of semiconductor light-emitting elements; at the same time, traditional nitride The hole ionization efficiency of the semiconductor is much lower than the electron ionization efficiency, resulting in the hole concentration being more than 2 orders of magnitude lower than the electron concentration. The low ionization efficiency will make it difficult for the holes of the second conductivity type semiconductor to be effectively injected into the multiple quantum wells, and the efficiency of hole injection into the multiple quantum wells is low, resulting in low luminous efficiency of the multiple quantum wells; the nitride semiconductor structure has non-centrosymmetry , strong spontaneous polarization will be generated along the c-axis direction, and the piezoelectric polarization effect of lattice mismatch will be superimposed to form an intrinsic polarization field; the intrinsic polarization field is along the (001) direction, making the multi-quantum well layer It produces a strong quantum confinement Stark effect, which causes the energy band tilt and the space separation of the electron-hole wave function, reduces the radiative recombination efficiency of the electron-hole, and then affects the luminous efficiency of the semiconductor light-emitting element. The defect of the traditional nitride semiconductor light-emitting element extends to the quantum well, resulting in a deep-level defect center, and the PN interlaces to generate interjunction capacitance to form a thyristor, which causes the conduction voltage of the light-emitting diode to rise during use, and the diode is lit. Afterwards, the voltage dropped again, resulting in inconsistencies in the conduction voltages of normal and abnormal chips, and the problem of inconsistency in lighting during use.

Contents of the invention

The object of the present invention is to provide a semiconductor element with a thyristor suppression layer, which solves the problems in the prior art.

A semiconductor element with a thyristor suppression layer comprises a substrate, a first n-type semiconductor layer, a second n-type semiconductor layer, a thyristor suppression layer, a quantum well layer and a p-type semiconductor layer arranged sequentially from bottom to top.

As a preferred technical solution of the present invention, the thyristor suppression layer is composed of a first thyristor suppression layer, a second thyristor suppression layer and a third thyristor suppression layer from bottom to top.

As a preferred technical solution of the present invention, the C content from the second thyristor suppression layer to the first thyristor suppression layer has a double-step downward trend, including a first C content drop step and a second C content drop step; the first step The angle of the first C content descending step is α: 60°≥α≥15°, and the second C content descending step angle is β: 90°≥β≥30°.

As a preferred technical solution of the present invention, the C content from the second thyristor suppression layer to the third thyristor suppression layer presents a double-step downward trend, including a third C content descending step and a fourth C content descending step; the first The third C content descending step angle is γ: 80°≥γ≥20°, and the fourth C content descending step angle is θ: 90°≥θ≥30°.

As a preferred technical solution of the present invention, the second C content decreasing step angle β≥the fourth C content decreasing step angle θ≥the third C content decreasing step angle γ≥the first C content decreasing step angle α.

As a preferred technical solution of the present invention, the C content concentration of the second thyristor suppression layer is kept constant, and the C content concentration is 1E17-5E18 cm ^-3 ; the Si doping concentration of the second thyristor suppression layer is kept constant at 5E17 ~5E18cm ^-3 , the Si doping concentration of the first thyristor suppression layer is peak-shaped, the peak Si doping concentration is 1E18-2E19cm ^-3 , the Si doping concentration of the third thyristor suppression layer is peak-shaped, The peak Si doping concentration is 8E17˜5E18 cm ⁻³ ; the Si doping concentration of the first thyristor suppression layer, the second thyristor suppression layer and the third thyristor suppression layer is greater than the C content concentration.

Further, the C content from the second thyristor suppression layer to the first thyristor suppression layer shows a double-step downward trend, including the first C content drop step and the second C content drop step, and the C content of the first C content drop step The content concentration drops from 5E17 to 5E18cm ^-3 by 1E17 to 5E17cm ^-3 , and the C content concentration of the second C content descending step decreases from 1E17 to 5E17cm ^-3 to 1E16 to 1E17cm ^-3 ; the second thyristor suppression layer goes to the third The C content of the thyristor suppression layer shows a double-step downward trend, including the third C content descending step and the fourth C content descending step, and the C content concentration of the third C content descending step decreases from 5E17～5E18cm ^-3 by 1E17～5E17cm ^-3 , the C content concentration of the fourth C content descending step decreases from 1E17 to 5E17 cm ^-3 to 1E16 to 1E17 cm ^-3 .

As a preferred technical solution of the present invention, the H content of the first thyristor suppression layer, the second thyristor suppression layer and the third thyristor suppression layer is kept constant, and the H content concentration is 1E17-1E18 cm ^-3 , and the first The O content of the thyristor suppression layer 103 a , the second thyristor suppression layer and the third thyristor suppression layer 103 c is kept constant, and the O content concentration is 1E16˜17E17 cm ⁻³ .

As a preferred technical solution of the present invention, the first n-type semiconductor layer, the second n-type semiconductor layer, the thyristor suppression layer, the quantum well layer, and the p-type semiconductor layer are GaN, AlGaN, InGaN, AlInGaN, AlN, InN, AlInN any one or any combination of .

As a preferred technical solution of the present invention, the quantum well layer is a periodic structure composed of well layers and barrier layers, the period number of the quantum well layer is x: 5≤x≤20, and the well layer of the quantum well layer Thickness a: 20 Å≤a≤60 Å, and thickness b of the barrier layer of the quantum well layer 104: 20 Å≤b≤150 Å.

Compared with prior art, the beneficial effect of the present invention:

In the scheme of the present invention:

Compared with the prior art, the present invention designs three layers of different C content concentrations in the thyristor suppression layer, the C content shows a double-step downward trend, and the Si doping concentration, H content concentration, and O content concentration are designed in the thyristor suppression layer. Combining with advanced semiconductor structure, suppressing deep level defect centers, suppressing PN interlacing to generate interjunction capacitance, reducing the generation probability of thyristor from 1 to 5% to 0, and solving the problem of inconsistency in lighting during the use of semiconductor light-emitting elements.

Description of drawings

Fig. 1 is a schematic structural view of a semiconductor element with a thyristor suppression layer in the present invention;

Fig. 2 is the SIMS secondary ion mass spectrogram of the semiconductor element with thyristor suppression layer in the present invention;

FIG. 3 is a partially enlarged view of FIG. 2 .

Reference signs:

100. Substrate, 101, first n-type semiconductor layer, 102, second n-type semiconductor layer, 103, thyristor suppression layer, 103a: first thyristor suppression layer, 103b: second thyristor suppression layer, 103c: The third thyristor suppression layer, 104, the quantum well layer, 105, the p-type semiconductor layer.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are some, not all, embodiments of the present invention.

Therefore, the following detailed description of the embodiments of the present invention is not intended to limit the scope of the claimed invention, but merely represents some embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

It should be noted that, in the case of no conflict, the embodiments of the present invention and the features and technical solutions in the embodiments can be combined with each other.

Please refer to FIG. 1, this embodiment provides a technical solution: a semiconductor element with a thyristor suppression layer, including a substrate 100, a first n-type semiconductor layer 101, a second n-type semiconductor layer arranged in sequence from bottom to top 102 , a thyristor suppression layer 103 , a quantum well layer 104 and a p-type semiconductor layer 105 .

Further, the thyristor suppression layer 103 is composed of a first thyristor suppression layer 103a, a second thyristor suppression layer 103b and a third thyristor suppression layer 103c from bottom to top.

Further, the C content from the second thyristor suppression layer 103b to the first thyristor suppression layer 103a presents a double-step downward trend, including a first C content drop step and a second C content drop step; the first C content The descending step angle is α: 60°≥α≥15°, and the descending step angle of the second C content is β: 90°≥β≥30°.

Further, the C content from the second thyristor suppression layer 103b to the third thyristor suppression layer 103c presents a double-step downward trend, including a third C content descending step and a fourth C content descending step; the third C content The descending step angle is γ: 80°≥γ≥20°, and the fourth C content descending step angle is θ: 90°≥θ≥30°.

Further, the second C content decreasing step angle β≥the fourth C content decreasing step angle θ≥the third C content decreasing step angle γ≥the first C content decreasing step angle α.

Further, as shown in FIGS. 2-3 , the C content concentration of the second thyristor suppression layer 103b is kept constant, and the C content concentration is 1E17-5E18cm ^-3 ; the Si-doped The dopant concentration is kept constant at 5E17~5E18cm ^-3 , the Si doping concentration of the first thyristor suppression layer 103a is peak-shaped, and the peak Si doping concentration is 1E18~2E19cm ^-3 , the Si doping concentration of the third thyristor suppression layer 103c The Si doping concentration is peak-shaped, and the peak Si doping concentration is 8E17-5E18cm ^-3 ; the Si doping concentration of the first thyristor suppression layer 103a, the second thyristor suppression layer 103b and the third thyristor suppression layer 103c is greater than C content concentration.

Further, the C content from the second thyristor suppression layer 103b to the first thyristor suppression layer 103a shows a double-step downward trend, including a first C content drop step and a second C content drop step, and the first C content drop step The C content concentration of the C content drops from 5E17 to 5E18 cm ^-3 by 1E17 to 5E17 cm ^-3 , and the C content concentration of the second C content descending step drops from 1E17 to 5E17 cm ^-3 to 1E16 to 1E17 cm ^-3 ; the second thyristor suppression layer 103b The C content to the third thyristor suppression layer 103c shows a double-step downward trend, including the third C content descending step and the fourth C content descending step, and the C content concentration of the third C content descending step drops from 5E17 to 5E18cm ^-3 by 1E17 ～5E17cm ^-3 , the C content concentration of the fourth C content descending step decreases from 1E17～5E17cm ^-3 to 1E16～1E17cm ^-3 .

Further, the H content of the first thyristor suppression layer 103a, the second thyristor suppression layer 103b and the third thyristor suppression layer 103c is kept constant, and the concentration of H content is 1E17-1E18cm ^-3 , the first thyristor The O content of the suppression layer 103a, the second thyristor suppression layer 103b and the third thyristor suppression layer 103c is kept constant, and the O content concentration is 1E16˜17E17 cm ⁻³ .

In the thyristor suppression layer, three layers with different C content concentrations, C content showing a double-step downward trend, and a semiconductor structure combination of Si doping concentration, H content concentration and O content concentration are designed to suppress deep energy level defect centers and PN interlacing Interjunction capacitance is generated to reduce the generation probability of the thyristor from 1 to 5% to 0, and solve the problem of inconsistency in lighting during the use of the semiconductor light-emitting element.

Further, the first n-type semiconductor layer 101, the second n-type semiconductor layer 102, the thyristor suppression layer 103, the quantum well layer 104, and the p-type semiconductor layer 105 are GaN, AlGaN, InGaN, AlInGaN, AlN, InN, AlInN any one or any combination of .

Further, the quantum well layer 104 is a periodic structure composed of well layers and barrier layers, the number of periods of the quantum well layer 104 is x: 5≤x≤20, and the well layer thickness of the quantum well layer 104 is a: 20 angstroms≤a≤60 angstroms, and the barrier layer thickness b of the quantum well layer 104: 20 angstroms≤b≤150 angstroms.

The technical scheme in the embodiment is adopted to carry out the green laser experiment, and the experimental results are compared as follows with respect to the data of traditional semiconductor components : ;

semiconductor element Traditional Semiconductor Components Semiconductor element of the present invention Range of change Thyramid production rate 4.8 0% -100% White light photoelectric conversion efficiency (lm/W) 180 260 44%

Compared with the prior art, the present invention designs three layers of different C content concentrations in the thyristor suppression layer, the C content shows a double-step downward trend, and the Si doping concentration, H content concentration, and O content concentration are designed in the thyristor suppression layer. Combining with advanced semiconductor structure, suppressing deep level defect centers, suppressing PN interlacing to generate interjunction capacitance, reducing the generation probability of thyristor from 1 to 5% to 0, and solving the problem of inconsistency in lighting during the use of semiconductor light-emitting elements.

The above embodiments are only used to illustrate the present invention and are not intended to limit the technical solutions described in the present invention. Although the specification has described the present invention in detail with reference to the above-mentioned embodiments, the present invention is not limited to the above-mentioned specific implementation methods, so Any modifications or equivalent replacements to the present invention; and all technical solutions and improvements that do not depart from the spirit and scope of the invention are covered by the scope of the claims of the present invention.

Claims (10)

1. A semiconductor device having a thyristor suppression layer is characterized by comprising a substrate (100), a first n-type semiconductor layer (101), a second n-type semiconductor layer (102), a thyristor suppression layer (103), a quantum well layer (104) and a p-type semiconductor layer (105) which are arranged in this order from bottom to top.

2. The semiconductor element with a thyristor inhibiting layer according to claim 1, wherein the thyristor inhibiting layer (103) is composed of a first thyristor inhibiting layer (103 a), a second thyristor inhibiting layer (103 b) and a third thyristor inhibiting layer (103 c) from bottom to top.

3. The semiconductor element with a thyristor inhibiting layer according to claim 2, wherein the second thyristor inhibiting layer (103 b) has a double-step decreasing trend of C content toward the first thyristor inhibiting layer (103 a), comprising a first C content decreasing step and a second C content decreasing step; the first C content decreasing step angle is alpha: the angle of the second C content decreasing step is more than or equal to 60 degrees and more than or equal to 15 degrees, and the angle of the second C content decreasing step is beta: the angle beta is more than or equal to 90 degrees and more than or equal to 30 degrees.

4. The semiconductor element with a thyristor inhibiting layer according to claim 2, wherein the second thyristor inhibiting layer (103 b) has a double-step downward trend of C content toward the third thyristor inhibiting layer (103C), including a third C content downward step and a fourth C content downward step; the third C content decreasing step angle is gamma: the angle of the fourth C content descending step is more than or equal to 80 degrees, the gamma is more than or equal to 20 degrees, and the angle of the fourth C content descending step is theta: the angle theta is more than or equal to 90 degrees and more than or equal to 30 degrees.

5. The semiconductor element with a thyristor inhibiting layer according to claim 4, wherein the second C-content step angle β is greater than or equal to the fourth C-content step angle θ is greater than or equal to the third C-content step angle γ is greater than or equal to the first C-content step angle α.

6. The semiconductor device with a thyristor inhibiting layer according to claim 5, wherein the second thyristor inhibiting layer (103 b) has a constant C content concentration of 1E 17-5E 18cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The Si doping concentration of the second thyristor suppression layer (103 b) is kept constant at 5E 17-5E 18cm ^-3 The Si doping concentration of the first thyristor suppression layer (103 a) is in a mountain shape, and the peak Si doping concentration is 1E 18-2E 19cm ^-3 The third thyristor inhibiting layer (103 c) has a peak Si doping concentration of 8E 17-5E 18cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The first thyristor suppression layer (103 a), the second thyristor suppression layer (103 b), and the third thyristor suppression layer (103C) have Si doping concentrations greater than the C content concentration.

7. The semiconductor device with a thyristor inhibiting layer according to claim 6, wherein the second thyristor inhibiting layer (103 b) has a two-step decreasing trend of the C content toward the first thyristor inhibiting layer (103 a), comprising a first C contentA step of decreasing the C content and a step of decreasing the second C content, wherein the C content concentration of the step of decreasing the first C content is from 5E17 to 5E18cm ^-3 Drop by 1E 17-5E 17cm ^-3 The concentration of C content of the second C content reduction step is from 1E17cm to 5E17cm ^-3 Lowering to 1E 16-1E 17cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The C content of the second thyristor inhibiting layer (103 b) towards the third thyristor inhibiting layer (103C) is in a double-step descending trend, and comprises a third C content descending step and a fourth C content descending step, wherein the C content concentration of the third C content descending step is from 5E17cm to 5E18cm ^-3 Drop by 1E 17-5E 17cm ^-3 C content concentration of the fourth C content reduction step is from 1E17cm to 5E17cm ^-3 Lowering to 1E 16-1E 17cm ^-3 。

8. The semiconductor element with a thyristor inhibiting layer according to claim 2, wherein the first thyristor inhibiting layer (103 a), the second thyristor inhibiting layer (103 b) and the third thyristor inhibiting layer (103 c) have a constant H content and a H content concentration of 1E17 to 1E18cm ^-3 The first thyristor suppression layer (103 a), the second thyristor suppression layer (103 b) and the third thyristor suppression layer (103 c) have a constant O content of 1E 16-17E 17cm ^-3 。

9. The semiconductor element with a thyristor inhibiting layer according to claim 1, wherein the first n-type semiconductor layer (101), the second n-type semiconductor layer (102), the thyristor inhibiting layer (103), the quantum well layer (104), and the p-type semiconductor layer (105) are any one or any combination of GaN, alGaN, inGaN, alInGaN, alN, inN, alInN.

10. The semiconductor element with a thyristor inhibiting layer according to claim 1, wherein the quantum well layer (104) is a periodic structure composed of a well layer and a barrier layer, and the number of cycles of the quantum well layer (104) is x: x is more than or equal to 5 and less than or equal to 20, and the thickness of the well layer of the quantum well layer (104) is a:20 a.ltoreq.60 a.ltoreq.m, the barrier layer thickness b of the quantum well layer (104): b is more than or equal to 20 and less than or equal to 150.