CN116661731A - Full adder, chip and computing device - Google Patents

Abstract

The present invention relates to the field of integrated circuits, and provides a full adder, a chip and a computing device, wherein the full adder includes: an inverter, which is used to generate an inverted signal for the first addend signal input at the first addend end and provide For the first node; the exclusive OR circuit is used to perform exclusive OR calculation on the first addend signal and the second addend signal input from the second addend end based on the inverted signal to obtain a carry propagation signal and provide it to the second node; The OR circuit is used to use the power supply under the control of the NOR signal and the carry input signal if the carry input signal is low when the first addend signal is at high level and the second addend signal is at low level. The signal will pull up the sum bit output signal, if the carry input signal is high level, the same OR signal will be used as the sum bit output signal. It can avoid the problem of the output performance reduction of the sum bit output signal caused by the pull-up delay at the second node when the first addend signal is high level and the second addend signal is low level, and improve the performance of the full adder .

Description

Full adder, chip and computing device

technical field

The invention relates to the technical field of integrated circuits, in particular to a full adder, a chip and a computing device.

Background technique

The full adder is a basic calculation unit of digital circuits, mainly used to realize addition and multiplication calculations, and is an important part of the calculation circuit. Reducing power consumption and improving performance are important tasks in the design of full adders. Therefore, how to improve the performance of the full adder is an important issue to be solved urgently in the industry.

Contents of the invention

The invention provides a full adder, a chip and a computing device, which are used to solve the problem of how to improve the performance of the full adder in the prior art and realize the improvement of the performance of the full adder.

The present invention provides a full adder, comprising:

an inverter, respectively connected to the first addend terminal and the first node, and used to generate an inverted signal for the first addend signal input to the first addend terminal and provide it to the first node;

An exclusive OR circuit, connected to the first addend end, the second addend end, the first node, and the second node, and used to compare the first addend signal and the second addend signal based on the inverted signal performing XOR calculation on the second addend signal input from the second addend end to obtain a carry propagation signal and providing it to the second node;

A NOR circuit, respectively connected to the first addend terminal, the second addend terminal, the first node, and the third node, and used to convert the first addend signal based on the inverted signal performing an exclusive OR calculation with the second addend signal to obtain an exclusive OR signal and providing it to the third node;

a summation circuit, connected to the second node, the third node, the carry input terminal, the power supply terminal and the sum output terminal respectively, and is used to provide the carry input signal based on the carry propagation signal and the carry input terminal , the NOR signal and the power signal provided by the power supply end generate the sum bit output signal of the sum bit output port; wherein, when the first addend signal is high level and the second addend signal is In the case of low level, if the carry input signal is low level, the power supply signal is used to pull up the sum output signal under the control of the NOR signal and the carry input signal. The carry input signal is at a high level, and the NOR signal is used as the sum bit output signal.

According to a full adder provided by the present invention, the XOR circuit includes: a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor and a fifth switch transistor; the first switch transistor and The second switch transistor is a P-type switch transistor; the third switch transistor, the fourth switch transistor, and the fifth switch transistor are N-type switch transistors;

The gate of the first switch transistor, the first source/drain of the second switch transistor, and the gate of the fifth switch transistor are respectively connected to the first adder terminal;

The gate of the second switching transistor, the first source/drain of the first switching transistor, the first source/drain of the third switching transistor, and the gate of the fourth switching transistor are respectively connected to the second addend;

the second source/drain of the first switch transistor, the second source/drain of the second switch transistor, the second source/drain of the third switch transistor, and the fourth switch The first source/drain of the transistor is respectively connected to the second node;

The second source/drain of the fourth switch transistor is connected to the first source/drain of the fifth switch transistor;

The second source/drain of the fifth switch transistor is connected to the ground terminal;

The gate of the third switching transistor is connected to the first node.

According to a full adder provided by the present invention, the summation circuit includes: a first transmission gate, a sixth switch transistor, a seventh switch transistor, and an eighth switch transistor; wherein, the sixth switch transistor and the seventh switch transistor The transistor is a P-type switching transistor; the eighth switching transistor is an N-type switching transistor;

The gate of the sixth switch transistor, the input terminal of the first transmission gate, and the gate of the eighth switch transistor are respectively connected to the carry input terminal;

The first source/drain of the sixth switch transistor is connected to the power supply terminal, the second source/drain of the sixth switch transistor is connected to the first source/drain of the seventh switch transistor connected;

The second source/drain of the seventh switch transistor, the output terminal of the first transmission gate, and the first source/drain of the eighth switch transistor are respectively connected to the sum bit output terminal;

The first control terminal of the first transmission gate is connected to the second node;

The second control terminal of the first transmission gate, the gate of the seventh switch transistor, and the second source/drain of the eighth switch transistor are respectively connected to the third node;

When the first addend signal is at high level and the second addend signal is at low level, if the carry input signal is at low level, the NOR signal and the carry input Under the control of the signal, the sixth switch transistor and the seventh switch transistor conduct the power supply terminal and the sum bit output terminal, so as to use the power supply signal to pull up the sum bit output signal;

When the first addend signal is at high level and the second addend signal is at low level, if the carry-in signal is at high-level, under the control of the carry-in signal, the The eighth switch transistor is turned on to use the exclusive OR signal as the sum bit output signal.

According to a full adder provided by the present invention, the NOR circuit includes: a ninth switch transistor, a tenth switch transistor, an eleventh switch transistor, a twelfth switch transistor, and a thirteenth switch transistor; wherein, the The ninth switch transistor, the tenth switch transistor and the eleventh switch transistor are P-type switch transistors; the twelfth switch transistor and the thirteenth switch transistor are N-type switch transistors;

The first source/drain of the ninth switch transistor, the gate of the tenth switch transistor, the first source/drain of the twelfth switch transistor, and the gate of the thirteenth switch transistor The poles are respectively connected to the second addend;

The gate of the eleventh switch transistor, the gate of the twelfth switch transistor, and the first source/drain of the thirteenth switch transistor are respectively connected to the first addend terminal;

The second source/drain of the ninth switch transistor, the first source/drain of the tenth switch transistor, the second source/drain of the twelfth switch transistor, and the tenth switch transistor the second source/drain of the three switching transistors are respectively connected to the third node;

The gate of the ninth switch transistor is connected to the first node;

The second source/drain of the tenth switch transistor is connected to the first source/drain of the eleventh switch transistor;

The second source/drain of the eleventh switch transistor is connected to the power supply terminal.

According to a full adder provided by the present invention, the inverter includes: a fourteenth switch transistor and a fifteenth switch transistor; wherein, the fourteenth switch transistor is a P-type switch transistor; the fifteenth switch transistor The switch transistor is an N-type switch transistor;

The gate of the fourteenth switch transistor and the gate of the fifteenth switch transistor are respectively connected to the first adder terminal;

The first source/drain of the fourteenth switch transistor is connected to the power supply terminal;

The second source/drain of the fourteenth switch transistor and the first source/drain of the fifteenth switch transistor are respectively connected to the first node;

The second source/drain of the fifteenth switch transistor is connected to the ground terminal.

A full adder provided according to the present invention also includes: a carry circuit;

The carry circuit is respectively connected to the second node, the third node, the carry input terminal, the second addend terminal and the carry output terminal, and is used for propagating the signal based on the carry, the same OR signal, the second addend signal and the carry-in signal to generate a carry-out signal at the carry-out terminal.

According to a full adder provided by the present invention, the carry circuit includes: a second transmission gate and a third transmission gate;

The first control terminal of the second transmission gate and the second control terminal of the third transmission gate are respectively connected to the second node;

The second control terminal of the second transmission gate and the first control terminal of the third transmission gate are respectively connected to the third node;

The input terminal of the second transmission gate is connected to the second addend terminal;

The input terminal of the third transmission gate is connected to the carry input terminal;

The output end of the second transmission gate and the output end of the third transmission gate are respectively connected to the carry output end.

According to a full adder provided by the present invention, the P-type switch transistor is PMOS; the N-type switch transistor is NMOS.

The present invention also provides a chip, including the full adder as described above.

The present invention also provides a computing device, including any one of the chips described above.

The full adder provided by the present invention uses an inverter to generate an inverted signal for the first addend signal and provides it to the first node, and the exclusive OR circuit performs exclusive operation on the first addend signal and the second addend signal based on the inverted signal The OR is calculated to obtain the carry propagation signal and provided to the second node, and the OR circuit performs the OR to the first addend signal and the second addend signal based on the inverted signal to obtain the OR signal and provides it to the third node. When the addend signal is at high level and the second addend signal is at low level, if the carry input signal is at low level, the summation circuit can use the power supply signal to combine the summation under the control of the NOR signal and the carry input signal The bit output signal is pulled up. If the carry input signal is high level, the summation circuit will use the OR signal as the sum bit output signal, so as to avoid the situation that the first addend signal is high level and the second addend signal is low level. In the case of flatness, the output performance of the sum bit output signal is reduced due to the pull-up delay at the second node, thereby greatly improving the performance of the full adder.

Description of drawings

In order to more clearly illustrate the present invention or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings in the following description are the For some embodiments of the present invention, those of ordinary skill in the art can also obtain other drawings based on these drawings on the premise of not paying creative efforts.

Fig. 1 is one of structural representations of full adder provided by the present invention;

Fig. 2 is the second structural diagram of the full adder provided by the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention , but not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

The logical expression of the full adder is as follows:

p'=p=A⊙B (2)

Cout＝ p'·B+ p·Cin (4)

in, Indicates XOR calculation, ⊙ indicates XOR calculation, A and B indicate two input addend signals, Cin indicates carry input signal, p indicates XOR calculation result, p' indicates XOR calculation result, Sum indicates sum bit Output signal, Cout represents the carry output signal.

The full adder based on the transmission tube logic can bring advantages in terms of area and power consumption, so it occupies a dominant position in the low power full adder, however, there are still internal node non-full swings in many full adder designs Amplitude output, low noise margin, poor stability, excessive delay under the condition of minimum power consumption, etc. Usually, a static inverter is added to the design of the full adder to optimize the non-full swing of the internal node. However, the introduction of the inverter causes the delay of the internal node to be too large. Among many low-energy full adders, 16 transistors (Transistor, T) and 20T full adders have lower power consumption. However, in the 16T full adder design, the output node of the XOR calculation result and the same Or the output node of the calculated result has a threshold loss in some states, causing the performance of the full adder to be significantly reduced, and it cannot work normally under low voltage. In the 20T full adder design, A is compensated by the NMOS/PMOS controlled by the inverter to solve the problem of threshold loss, but there is a competition problem when A=1, B=0, and Cin=0, which also leads to the 20T full adder Adder delay is high. Therefore, the performance of the full adder needs to be improved.

A full adder of the present invention will be described below with reference to FIG. 1 to FIG. 2 .

This embodiment provides a full adder, as shown in Figure 1, including:

The inverter 110 is respectively connected to the first addend terminal and the first node, and is used to generate an inverted signal for the first addend signal input to the first addend terminal and provide it to the first node;

Exclusive OR circuit 120, connected to the first addend end, the second addend end, the first node and the second node respectively, and used to compare the first addend signal and the first addend signal based on the inverted signal Exclusive OR calculation is performed on the second addend signal input from the second addend end to obtain a carry propagation signal and provided to the second node;

NOR circuit 130, connected to the first addend end, the second addend end, the first node and the third node respectively, and used to, based on the inverted signal, performing an exclusive OR calculation on the signal and the second addend signal to obtain an exclusive OR signal and providing it to the third node;

A summation circuit 140 is connected to the second node, the third node, the carry input terminal, the power supply terminal and the sum output terminal respectively, and is used for carrying in based on the carry propagation signal and the carry input provided by the carry input terminal. signal, the NOR signal, and the power supply signal provided by the power supply end generate the sum bit output signal of the sum bit output port; wherein, when the first addend signal is high level and the second addend signal In the case of low level, if the carry input signal is low level, the power supply signal is used to pull up the sum output signal under the control of the NOR signal and the carry input signal, if The carry input signal is at a high level, and the NOR signal is used as the sum bit output signal.

The two addend signals that the full adder needs to input include a first addend signal A and a second addend signal B. Wherein, the first addend terminal is used for inputting the first addend signal A, and the second addend terminal is used for inputting the second addend signal B.

The inverter 110 may generate an inverted signal F of the first add signal A and provide it to the first node. The XOR circuit 120 can perform XOR calculation on the first addend signal A and the second addend signal B based on the inverted signal F to obtain the result p of the XOR calculation as the carry propagation signal, so p also represents the carry propagation signal, The carry propagate signal p is provided to the second node. The exclusive OR circuit 130 can perform the exclusive OR calculation on the first addend signal A and the second addend signal B based on the inverted signal F, and obtain the exclusive OR calculation result p' as the exclusive OR signal, therefore, p' also represents exclusive OR signal, and provide the exclusive OR signal p' to the third node. The summation circuit 140 can generate a sum output signal Sun at the sum output terminal based on the carry propagation signal p, the carry input signal Cin provided by the carry input terminal, the exclusive-OR signal p′ and the power signal Vdd provided by the power supply terminal.

The first addend signal can be high level, also can be low level, here, high level is 1, low level is 0, namely A=0 or promptly A=1, the second addend signal can be high The level, that is, B=1, can also be a low level, that is, B=0. Based on this, the first addend signal and the second addend signal input to the full adder can include the following situations:

A=1, B=1;

A=1, B=0;

A=0, B=1;

A=0, B=0.

Correspondingly, the carry propagation signal p of the XOR circuit 120 includes:

When A=1, B=1, p=0;

When A=1, B=0, p=1;

When A=0, B=1, p=1;

When A=0, B=0, p=0.

The same-or signal of the same-or circuit 130 includes:

When A=1, B=1, p'=1;

When A=1, B=0, p'=0;

When A=0, B=1, p'=0;

When A=0, B=0, p'=1.

When the first addend signal is at high level and the second addend signal is at low level, that is, in the case of A=1 and B=0, there is a delay in the pull-up of the second node, resulting in summation The output performance of the sum bit output signal of circuit 140 is degraded. In order to solve this problem, in the present embodiment, when A=1, B=0, Cin=0, instead of utilizing the carry propagation signal p at the second node to realize the output of the sum bit output signal of the full adder, but Utilize the NOR signal p' and the carry input signal Cin to realize the output of the sum output signal of the full adder, under the control of the NOR signal p' and the carry input signal Cin, use the The power signal Vdd pulls up the sum bit output signal Sum, so that the sum bit output signal Sum is at a high level, ie Sum=1. When A=1, B=0, and Cin=1, the carry propagation signal p at the second node is not used to realize the output of the sum bit output signal Sum of the full adder, but the same OR signal p' is utilized To realize the output of the sum bit output signal Sum of the full adder, the exclusive OR signal p' is used as the sum bit output signal Sum. In this way, the problem of degraded output performance of the sum bit output signal due to the pull-up delay at the second node can be avoided.

Based on this, the sum bit output signal Sum of the summation circuit 140 includes:

When p=1 (p'=0), Cin=1, Sum=0;

When p=1 (p'=0), Cin=0, Sum=1;

When p=0 (p'=1), Cin=1, Sum=1;

When p=0 (p'=1), Cin=0, Sum=0.

In this embodiment, the inverter 110 is used to generate an inverted signal for the first addend signal and provide it to the first node, and the XOR circuit 120 performs an inversion of the first addend signal and the second addend signal based on the inverted signal. The signals are XOR-calculated to obtain a carry propagation signal and provided to the second node, and the NOR circuit 130 performs XOR calculation on the first addend signal and the second addend signal based on the inverted signal to obtain the same OR signal and provide it to the third node, when the first addend signal is high level and the second addend signal is low level, if the carry input signal is low level, The summation circuit 140 can use the power supply signal to pull up the sum bit output signal under the control of the NOR signal and the carry input signal. If the carry input signal is high level, the summation circuit 140 The NOR signal is used as the sum bit output signal, so that when the first addend signal is high level and the second addend signal is low level, due to the The problem that the output performance of the sum-bit output signal is reduced due to the pull-up delay caused by the pull-up delay, thus greatly improving the performance of the full adder.

Further, as shown in FIG. 1, the full adder may further include: a carry circuit 150;

The carry circuit 150 is respectively connected to the second node, the third node, the carry input terminal, the second addend terminal and the carry output terminal, and is used for propagating the signal based on the carry, the The NOR signal, the second addend signal and the carry-in signal are used to generate a carry-out signal at the carry-out terminal.

The carry output signal Cout of the carry circuit 150 includes:

When p=1 (p'=0), Cin=1, Cout=1;

When p=1 (p'=0), Cin=0, Cout=0;

When p=0 (p'=1), B=1, Cout=1;

When p=0 (p'=1), B=0, Cout=0.

In this embodiment, the carry circuit 150 is not affected by the delay problem, and can directly use the carry propagation signal p, the exclusive OR signal p', the second addend signal B, and the carry input signal Cin to obtain a carry output Signal.

In an exemplary embodiment, as shown in FIG. 2 , the carry circuit 150 includes: a second transmission gate T2 and a third transmission gate T3;

The first control terminal of the second transmission gate T2 and the second control terminal of the third transmission gate T3 are respectively connected to the second node;

The second control terminal of the second transmission gate T2 and the first control terminal of the third transmission gate T3 are respectively connected to the third node;

The input end of the second transmission gate T2 is connected to the second addend end;

The input terminal of the third transmission gate T3 is connected to the carry input terminal;

The output terminal of the second transmission gate T2 and the output terminal of the third transmission gate T3 are respectively connected to the carry output terminal.

In this embodiment, the second transmission gate T2 and the third transmission gate T3 are used to form a selector controlled by the carry propagation signal p or the exclusive OR signal p', so as to select whether to output the second addend signal B or the carry input signal Cin, thus The output of the carry output signal Cout is realized.

in:

When p=1 (p'=0), when Cin=1, the third transmission gate T3 is turned on and connected to the carry input terminal, thereby selecting and outputting the carry input signal Cin, Cout=1;

When p=1 (p'=0), Cin=0, the third transmission gate T3 is turned on and connected to the carry input terminal, thereby selecting and outputting the carry input signal Cin, Cout=0;

When p=0 (p'=1), when B=1, the second transmission gate T2 is turned on and connected to the second addend end, thereby selecting and outputting the second addend signal B, Cout=1;

When p=0 (p′=1) and B=0, the second transmission gate T2 is turned on and connected to the second addend terminal, so as to select and output the second addend signal B, and Cout=0.

In an exemplary embodiment, as shown in FIG. 2 , the XOR circuit 120 includes: a first switch transistor M1, a second switch transistor M2, a third switch transistor M3, a fourth switch transistor M4, and a fifth switch transistor M5 The first switch transistor M1 and the second switch transistor M2 are P-type switch transistors; the third switch transistor M3, the fourth switch transistor M4 and the fifth switch transistor M5 are N-type switch transistors ;

The gate of the first switching transistor M1, the first source/drain of the second switching transistor M2, and the gate of the fifth switching transistor M5 are respectively connected to the first adder terminal;

The gate of the second switching transistor M2, the first source/drain of the first switching transistor M1, the first source/drain of the third switching transistor M3, and the fourth switching transistor M4 The gates of are respectively connected to the second addend end;

The second source/drain of the first switching transistor M1, the second source/drain of the second switching transistor M2, the second source/drain of the third switching transistor M3 and the The first source/drain of the fourth switching transistor M4 are respectively connected to the second node;

The second source/drain of the fourth switch transistor M4 is connected to the first source/drain of the fifth switch transistor M5;

The second source/drain of the fifth switching transistor M5 is connected to the ground terminal GND;

The gate of the third switching transistor M3 is connected to the first node.

The P-type switch transistor in the present invention may be PMOS; the N-type switch transistor may be NMOS. The switching transistor includes a gate, a first source/drain, a second source/drain and a substrate. The substrate of the PMOS is connected to the power terminal, and the substrate of the NMOS is connected to the ground terminal. One of the first source/drain and the second source/drain is the source, the other is the drain, the higher voltage end of the PMOS is the source, and the lower voltage end of the NMOS is the source pole.

In this embodiment, the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, the fourth switching transistor M4 and the fifth switching transistor M5 form an exclusive-or (XOR) logic gate with full-swing output to realize the first The XOR of an addend signal A and the second addend signal B generates a carry propagation signal p, and the working process is as follows:

The first addend signal A generates an inverted signal F under the action of the inverter 110, based on this:

When A=1, B=1, the fourth switch transistor M4 and the fifth switch transistor M5 are turned on and connected to GND, p=0;

When A=1, B=0, the second switching transistor M2 is turned on and connected to the first addend terminal, p=1;

When A=0, B=1, the third switch transistor M3 is turned on and connected to the second addend end, the first switch transistor M1 is turned on and connected to the second addend end, p=1;

When A=0, B=0, the third switch transistor M3 is turned on and connected to the second addend, the first switch transistor M1 is turned on and connected to the second addend, and the second switch transistor M2 is turned on and connected to the first addend end, p=0.

In the full adder shown in Figure 2, when A=1, B=0, there is a delay in turning off the third switching transistor M3, which prevents the second switching transistor M2 from pulling up the second node and thus delays. This solution is improved The output logic of the sum bit output signal Sum in the key state, when A=1, B=0, Cin=0, the sum bit output signal Sum is pulled up by the same OR signal p' and the carry input signal Cin, when A=1, When B=0, Cin=1, the carry input signal Cin will output the same-OR signal p', and the full adder and bit output logic are realized without the carry propagation signal p, avoiding the impact of delay on the performance of the full adder.

In an exemplary embodiment, as shown in FIG. 2 , the summation circuit 140 includes: a first transmission gate T1, a sixth switch transistor M6, a seventh switch transistor M7, and an eighth switch transistor M8; wherein, the first The six switch transistors M6 and the seventh switch transistor M7 are P-type switch transistors; the eighth switch transistor M8 is an N-type switch transistor;

The gate of the sixth switch transistor M6, the input terminal of the first transfer gate T1, and the gate of the eighth switch transistor M8 are respectively connected to the carry input terminal;

The first source/drain of the sixth switch transistor M6 is connected to the power supply terminal, the second source/drain of the sixth switch transistor M6 is connected to the first source of the seventh switch transistor M7 / drain connected;

The second source/drain of the seventh switch transistor M7, the output terminal of the first transfer gate T1, and the first source/drain of the eighth switch transistor M8 are respectively connected to the sum bit output terminal connected;

The first control terminal of the first transmission gate T1 is connected to the second node;

The second control terminal of the first transmission gate T1, the gate of the seventh switch transistor M7, and the second source/drain of the eighth switch transistor M8 are respectively connected to the third node;

When the first addend signal is at high level and the second addend signal is at low level, if the carry input signal is at low level, the NOR signal and the carry input Under the control of the signal, the sixth switch transistor M6 and the seventh switch transistor M7 conduct the power supply terminal and the sum bit output terminal, so as to use the power supply signal to pull up the sum bit output signal;

When the first addend signal is at high level and the second addend signal is at low level, if the carry-in signal is at high-level, under the control of the carry-in signal, the The eighth switch transistor M8 is turned on to use the NOR signal p' as the sum bit output signal.

Among them, the first transmission gate T1, the sixth switching transistor M6, the seventh switching transistor M7 and the eighth switching transistor M8 form the NOR gate (XNOR) of the carry input signal Cin and the carry propagation signal p to obtain the final sum output signal Sum, where:

When p=1 (p'=0), Cin=1, the eighth switch transistor M8 is turned on and connected to the third node, Sum=0;

When p=1 (p'=0) and Cin=0, the sixth switching transistor M6 and the seventh switching transistor M7 are turned on and connected to the power supply terminal, Sum=1;

When p=0 (p'=1), Cin=1, the first transmission gate T1 is turned on and connected to the carry input terminal, Sum=1;

When p=0 (p′=1) and Cin=0, the first transmission gate T1 is turned on and connected to the carry input terminal, and Sum=0.

When A=1, B=0, there is a delay in turning off the third switching transistor M3, which prevents the second switching transistor M2 from pulling up the XOR signal p at the second node, resulting in slower turning off of the first transmission gate T1 Or in other full adders, the node directly pulled up by the XOR signal p at the second node has a relatively high delay, which further reduces the output performance of the sum bit output signal Sum of the full adder. In this embodiment, the sum output signal Sum output logic in this key state is improved. When A=1, B=0, and Cin=0, the NOR signal p' and the carry input signal Cin pass through the sixth The switch transistor M6 and the seventh switch transistor M7 pull up the sum output signal Sum; when A=1, B=0, and Cin=1, the carry input signal Cin will output the same-OR signal p', so that the carry can not be propagated Under the condition of the signal p, the output logic of the full adder and the bit output signal Sum is realized, and the critical path is optimized.

In an exemplary embodiment, as shown in FIG. 2, the inverter 110 includes: a fourteenth switch transistor M14 and a fifteenth switch transistor M15; wherein the fourteenth switch transistor M14 is a P-type switch transistor ; The fifteenth switching transistor M15 is an N-type switching transistor;

The gate of the fourteenth switch transistor M14 and the gate of the fifteenth switch transistor M15 are respectively connected to the first adder terminal;

The first source/drain of the fourteenth switching transistor M14 is connected to the power supply terminal;

The second source/drain of the fourteenth switch transistor M14 and the first source/drain of the fifteenth switch transistor M15 are respectively connected to the first node;

The second source/drain of the fifteenth switch transistor M15 is connected to the ground terminal GND.

As mentioned above, the P-type switching transistor may be PMOS; the N-type switching transistor may be NMOS.

In this embodiment, the problem of non-full swing of internal nodes is optimized by adding a static inverter 110 into the design of the full adder. The full-swing output of the internal nodes is suitable for operation at low voltage, making the full adder suitable for low-voltage scenarios.

In an exemplary embodiment, as shown in FIG. 2 , the NOR circuit 130 includes: a ninth switching transistor M9, a tenth switching transistor M10, an eleventh switching transistor M11, a twelfth switching transistor M12, and a thirteenth switching transistor. Switching transistor M13; wherein, the ninth switching transistor M9, the tenth switching transistor M10 and the eleventh switching transistor M11 are P-type switching transistors; the twelfth switching transistor M12 and the thirteenth switching transistor M13 are N-type switching transistor;

The first source/drain of the ninth switch transistor M9, the gate of the tenth switch transistor M10, the first source/drain of the twelfth switch transistor M12, and the thirteenth switch The gate of the transistor M13 is respectively connected to the second addend end;

The gate of the eleventh switch transistor M11, the gate of the twelfth switch transistor M12, and the first source/drain of the thirteenth switch transistor M13 are respectively connected to the first addend terminal ;

The second source/drain of the ninth switch transistor M9, the first source/drain of the tenth switch transistor M10, the second source/drain of the twelfth switch transistor M12 and all The second source/drain of the thirteenth switching transistor M13 is respectively connected to the third node;

The gate of the ninth switching transistor M9 is connected to the first node;

The second source/drain of the tenth switch transistor M10 is connected to the first source/drain of the eleventh switch transistor M11;

The second source/drain of the eleventh switching transistor M11 is connected to the power supply terminal.

Among them, the ninth switching transistor M9, the tenth switching transistor M10, the eleventh switching transistor M11, the twelfth switching transistor M12 and the thirteenth switching transistor M13 form a full-swing output NOR logic gate to realize the first addend The exclusive OR of the signal A and the second addend signal B produces an exclusive OR signal p', wherein:

The first addend signal A generates an inverted signal F under the action of the inverter 110, based on this:

When A=1, B=1, the ninth switch transistor M9 is turned on and connected to the second addend end, the twelfth switch transistor M12 is turned on and connected to the second addend end, and the thirteenth switch transistor M13 is turned on and connected to the first addend end. Addend end, p'=1;

When A=1, B=0, the ninth switch transistor M9 is turned on and connected to the second addend end, the twelfth switch transistor M12 is turned on and connected to the second addend end, p'=0;

When A=0, B=1, the thirteenth switching transistor M13 is turned on and connected to the first addend terminal, p'=0;

When A=0 and B=0, the tenth switching transistor M10 and the eleventh switching transistor M11 are turned on and connected to the power supply terminal, and p′=1.

The exclusive OR circuit 130 in this embodiment can realize the exclusive OR calculation of the full swing output.

Each of the first transmission gate T1 , the second transmission gate T2 and the third transmission gate T3 is composed of a PMOS and an NMOS connected in parallel. Therefore, the structure of the full adder shown in FIG. 2 includes 21 switch transistors, that is, a 21T full adder. The full adder provided in this embodiment can work stably and quickly at low pressure. Although the power consumption has slightly deteriorated, the delay has been greatly improved, and the overall power-delay product (Power-Delay Product, PDP) is better than other full adders. Compared with the typical low-power full adder CMOS 28T and the advanced low-power full adder 16T, 20T, a kind of 22T, and another kind of 22T, the present invention has a single full adder under 200MHZ, 1.2V, normal temperature, and TT process Power consumption deteriorated by 8.7%, 2.1%, 10.8%, -3%, -1.3%; Latency optimized by 39.7%, 46.6%, 47%, 11.7%, 11.2% respectively; Overall PDP optimized by 34.4%, 45.5%, 40% %, 14.4%, 12.4%. At 0.8v voltage, at normal temperature, compared with CMOS 28T, 20T, and a kind of 22T (16T can not work normally under 0.8v) under TT process, the power consumption of the single full adder of the present invention deteriorates respectively by 10.9%, 1.8%, - 2.3%, the delay is optimized by 34.3%, 37.1%, and 17.2%, and the overall PDP is optimized by 27.2%, 36%, and 16.2%. TT is the abbreviation of Typical-Typical, indicating that both NMOS and PMOS are typical processes.

The present invention also provides a chip, including the full adder provided in any one of the above embodiments. For the specific implementation of the chip, reference may be made to the above embodiments of the full adder, which will not be repeated here.

This embodiment also provides a computing device, including the chip provided by any one of the foregoing embodiments. For the specific implementation manner of the computing device, reference may be made to the above chip embodiments, which will not be repeated here.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

1. a full adder, is characterized in that, comprises: an inverter, respectively connected to the first addend terminal and the first node, and used to generate an inverted signal for the first addend signal input to the first addend terminal and provide it to the first node; An exclusive OR circuit, connected to the first addend end, the second addend end, the first node, and the second node, and used to compare the first addend signal and the second addend signal based on the inverted signal performing XOR calculation on the second addend signal input from the second addend end to obtain a carry propagation signal and providing it to the second node; A NOR circuit, respectively connected to the first addend terminal, the second addend terminal, the first node, and the third node, and used to convert the first addend signal based on the inverted signal performing an exclusive OR calculation with the second addend signal to obtain an exclusive OR signal and providing it to the third node; a summation circuit, connected to the second node, the third node, the carry input terminal, the power supply terminal and the sum output terminal respectively, and is used to provide the carry input signal based on the carry propagation signal and the carry input terminal , the NOR signal and the power signal provided by the power supply end generate the sum bit output signal of the sum bit output port; wherein, when the first addend signal is high level and the second addend signal is In the case of low level, if the carry input signal is low level, the power supply signal is used to pull up the sum output signal under the control of the NOR signal and the carry input signal. The carry input signal is at a high level, and the NOR signal is used as the sum bit output signal. 2. The full adder according to claim 1, wherein the XOR circuit comprises: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor and a fifth switching transistor; The first switch transistor and the second switch transistor are P-type switch transistors; the third switch transistor, the fourth switch transistor and the fifth switch transistor are N-type switch transistors; The gate of the first switch transistor, the first source/drain of the second switch transistor, and the gate of the fifth switch transistor are respectively connected to the first adder terminal; The gate of the second switching transistor, the first source/drain of the first switching transistor, the first source/drain of the third switching transistor, and the gate of the fourth switching transistor are respectively connected to the second addend; the second source/drain of the first switch transistor, the second source/drain of the second switch transistor, the second source/drain of the third switch transistor, and the fourth switch The first source/drain of the transistor is respectively connected to the second node; The second source/drain of the fourth switch transistor is connected to the first source/drain of the fifth switch transistor; The second source/drain of the fifth switch transistor is connected to the ground terminal; The gate of the third switching transistor is connected to the first node. 3. The full adder according to claim 2, wherein the summing circuit comprises: a first transmission gate, a sixth switching transistor, a seventh switching transistor and an eighth switching transistor; wherein the sixth The switch transistor and the seventh switch transistor are P-type switch transistors; the eighth switch transistor is an N-type switch transistor; The gate of the sixth switch transistor, the input terminal of the first transmission gate, and the gate of the eighth switch transistor are respectively connected to the carry input terminal; The first source/drain of the sixth switch transistor is connected to the power supply terminal, the second source/drain of the sixth switch transistor is connected to the first source/drain of the seventh switch transistor connected; The second source/drain of the seventh switch transistor, the output terminal of the first transmission gate, and the first source/drain of the eighth switch transistor are respectively connected to the sum bit output terminal; The first control terminal of the first transmission gate is connected to the second node; The second control terminal of the first transmission gate, the gate of the seventh switch transistor, and the second source/drain of the eighth switch transistor are respectively connected to the third node; When the first addend signal is at high level and the second addend signal is at low level, if the carry input signal is at low level, the NOR signal and the carry input Under the control of the signal, the sixth switch transistor and the seventh switch transistor conduct the power supply terminal and the sum bit output terminal, so as to use the power supply signal to pull up the sum bit output signal; When the first addend signal is at high level and the second addend signal is at low level, if the carry-in signal is at high-level, under the control of the carry-in signal, the The eighth switch transistor is turned on to use the exclusive OR signal as the sum bit output signal. 4. The full adder according to claim 1, wherein the NOR circuit comprises: the ninth switching transistor, the tenth switching transistor, the eleventh switching transistor, the twelfth switching transistor and the thirteenth switching transistor A transistor; wherein, the ninth switch transistor, the tenth switch transistor, and the eleventh switch transistor are P-type switch transistors; the twelfth switch transistor and the thirteenth switch transistor are N-type switch transistors; The first source/drain of the ninth switch transistor, the gate of the tenth switch transistor, the first source/drain of the twelfth switch transistor, and the gate of the thirteenth switch transistor The poles are respectively connected to the second addend; The gate of the eleventh switch transistor, the gate of the twelfth switch transistor, and the first source/drain of the thirteenth switch transistor are respectively connected to the first addend terminal; The second source/drain of the ninth switch transistor, the first source/drain of the tenth switch transistor, the second source/drain of the twelfth switch transistor, and the tenth switch transistor the second source/drain of the three switching transistors are respectively connected to the third node; The gate of the ninth switch transistor is connected to the first node; The second source/drain of the tenth switch transistor is connected to the first source/drain of the eleventh switch transistor; The second source/drain of the eleventh switch transistor is connected to the power supply terminal. 5. The full adder according to claim 1, wherein the inverter comprises: a fourteenth switching transistor and a fifteenth switching transistor; wherein the fourteenth switching transistor is a P-type switching transistor ; The fifteenth switching transistor is an N-type switching transistor; The gate of the fourteenth switch transistor and the gate of the fifteenth switch transistor are respectively connected to the first adder terminal; The first source/drain of the fourteenth switch transistor is connected to the power supply terminal; The second source/drain of the fourteenth switch transistor and the first source/drain of the fifteenth switch transistor are respectively connected to the first node; The second source/drain of the fifteenth switch transistor is connected to the ground terminal. 6. The full adder according to any one of claims 1 to 5, further comprising: a carry circuit; The carry circuit is respectively connected to the second node, the third node, the carry input terminal, the second addend terminal and the carry output terminal, and is used for propagating the signal based on the carry, the same OR signal, the second addend signal and the carry-in signal to generate a carry-out signal at the carry-out terminal. 7. The full adder according to claim 6, wherein the carry circuit comprises: a second transmission gate and a third transmission gate; The first control terminal of the second transmission gate and the second control terminal of the third transmission gate are respectively connected to the second node; The second control terminal of the second transmission gate and the first control terminal of the third transmission gate are respectively connected to the third node; The input terminal of the second transmission gate is connected to the second addend terminal; The input end of the third transmission gate is connected to the carry input end; The output end of the second transmission gate and the output end of the third transmission gate are respectively connected to the carry output end. 8. The full adder according to claim 2, wherein the P-type switch transistor is PMOS; the N-type switch transistor is NMOS. 9. A chip, comprising the full adder according to any one of claims 1 to 8. 10. A computing device comprising the chip according to claim 9.