CN116682860B - Surround gate channel silicon carbide field effect transistor and manufacturing method thereof - Google Patents

Abstract

The invention discloses a silicon carbide field effect transistor surrounding a gate channel and a manufacturing method thereof, wherein the transistor comprises second conductive type channel layer etching windows which penetrate through the second conductive type channel layer and contact a groove, a first gate dielectric layer positioned on the inner surface of the groove, a second gate dielectric layer positioned on the upper surface of the second conductive type channel layer and a third gate dielectric layer positioned on the inner wall of the second conductive type channel layer etching windows, wherein the second conductive type channel layer etching windows are periodically distributed on the second conductive type channel layer along the grid direction; filling a first gate electrode in the trench, a second gate electrode covering part of the upper surface of the second gate dielectric layer and a third gate electrode filling an etching window of the second conductive type channel layer; the invention adopts the design of surrounding gate channel, and utilizes the upper and lower double-layer gate electrodes to realize the gate control conduction of the ultrathin channel, thereby obtaining the ultra-high channel mobility and greatly reducing the on-resistance of the device.

Description

Surround gate channel silicon carbide field effect transistor and manufacturing method thereof

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a surround gate channel silicon carbide field effect transistor and a manufacturing method thereof.

Background technique

The development of power electronic systems has put forward higher requirements for the performance of semiconductor devices, especially in terms of high temperature, high frequency, radiation resistance, and high voltage. The manufacturing process of traditional silicon material devices is mature, but the performance of the material itself limits the application of silicon devices in extreme working environments. Compared with silicon (Si) material, silicon carbide (SiC) material has a larger band gap, higher electron saturation drift velocity, stronger radiation resistance, higher breakdown electric field and thermal conductivity. It has broad application prospects in the fields of power electronic equipment, aerospace systems, high-speed rail traction equipment, military electronic communication systems and other fields.

However, unlike Si materials, the oxidation process of SiC materials will produce the precipitation of free carbon (C). Although most of the C will be converted into gaseous carbon oxides in an oxygen atmosphere, a considerable part still exists as C clusters. Gate oxide layer interface. On the other hand, the epitaxial quality of SiC material itself is far different from that of Si material, and there are many crystal defects, dislocations, etc. These combined factors cause the interface state density in the channel region of conventional SiC MOSFET devices to be much higher than that of Si MOSFETs. The direct impact is that the channel mobility is very low. Even if nitrogen oxide high-temperature annealing is used, the mobility can only be increased to 20cm ² /V·s~30cm ² /V·s. The proportion of channel resistance in SiC low-voltage MOSFET devices is particularly prominent. The trench structure of the vertical gate is a solution that can increase the channel mobility to more than 40 cm ² /V·s, but the trench gate structure requires effective shielding of the strong electric field at the bottom of the gate dielectric, which will directly affect Device reliability.

At present, the channel mobility of SiC MOSFETs with conventional structures is much lower than the body mobility, causing channel on-resistance to account for a prominent proportion in low-voltage devices and affecting conduction performance. Although the literature reports the use of trench structures, when the SiC between trenches, that is, the lateral spacing between SiC trenches is less than 100nm, especially when it is close to 50nm, the channel mobility of the trench device decreases due to the influence of the double-sided gating effect. It can reach 200 cm ² /V·s, achieving a significant improvement. However, it is very difficult to control the etching process of 50nm line width for power devices, especially SiC, a material that is much more difficult to etch than Si, so this structure is not mass-produced.

Contents of the invention

Technical purpose: In view of the problems in the prior art, the present invention discloses a surround gate channel silicon carbide field effect transistor and a manufacturing method thereof. It adopts a surround gate channel design and uses upper and lower double-layer gate electrodes to realize gate control of the channel. It can achieve ultra-high channel mobility and greatly reduce the on-resistance of the device.

Technical solution: In order to achieve the above technical purpose, the present invention adopts the following technical solution.

First conductivity type SiC epitaxial layer;

a second conductivity type well region in the first conductivity type SiC epitaxial layer;

In the first conductivity type SiC epitaxial layer, the trench adjacent to the second conductivity type well region defines the x direction as the device length direction, the y direction as the device width direction, which is also the gate bar direction, and the z direction as the device height direction; x The first conductivity type SiC epitaxial layer between adjacent trenches in the direction is defined as the device neck region;

A first conductivity type SiC epitaxial layer, a second conductivity type well region and a second conductivity type channel layer on the trench;

a first conductivity type source region that penetrates the second conductivity type channel layer and extends into the second conductivity type well region, and is adjacent to the trench;

Etch windows of the second conductive type channel layer are periodically distributed along the direction of the gate strips on the second conductive type channel layer, penetrate the second conductive type channel layer and contact the trench;

The gate dielectric layer includes a first gate dielectric layer located on the inner surface of the trench, a second gate dielectric layer located on the upper surface of the second conductive type channel layer, and located on the inner wall of the etching window of the second conductive type channel layer. The third gate dielectric layer;

The gate electrode includes a first gate electrode that fills the trench and is wrapped by the first gate dielectric layer, a second gate electrode that covers part of the upper surface of the second gate dielectric layer, and an etched window that fills the second conductivity type channel layer and is a third gate electrode wrapped by a third gate dielectric layer;

an isolation dielectric layer covering the second gate electrode and the second gate dielectric layer and covering part of the first conductive type source region;

The source ohm is connected to part of the second conductivity type channel layer and part of the first conductivity type source region.

Preferably, the trench is continuous along the direction of the gate bar, or is a periodically distributed rectangular shape; the projection of the trench in the z direction completely covers the etching window of the second conductive type channel layer; the trench The depth is greater than 0.5um, and the width of the trench in the The border spacing is greater than 0.2um.

Preferably, the second conductive type well region does not completely cover the trench, and the lateral boundary difference between the trench and the adjacent second conductive type well region on the side close to the device neck region is less than 0.8um.

Preferably, the thickness of the second conductive type channel layer does not exceed 120 nm.

Preferably, the length of the etching window of the second conductive type channel layer in the x direction is not less than 1.0um; the width of the etching window of the second conductive type channel layer in the y direction is not less than 0.8um; the second conductive type channel layer The spacing between the etching windows ranges from 1.5um to 2.0um; the boundary distance between the etching windows of the second conductivity type channel layer and the trench ranges from 0.1um to 1.0um.

Preferably, the method further includes: a second conductive type heavily doped region penetrating the second conductive type channel layer, extending into the second conductive type well region and away from the trench; penetrating the second conductive type channel layer and extending to the second conductive type well region; In a conductive type SiC epitaxial layer, the first conductive type current expansion area is located in the middle of the device neck area.

A method for manufacturing a surround gate channel silicon carbide field effect transistor, including the following steps:

S1. Form a first conductive type SiC epitaxial layer on the first conductive type SiC substrate;

S2. Selectively dope the first conductive type epitaxial layer to form a second conductive type well region;

S3. Etch the first conductive type SiC epitaxial layer to form a trench;

S4. Form a sacrificial layer in the trench;

S5. Form a second conductivity type channel layer on the first conductivity type SiC epitaxial layer 1, the second conductivity type well region 2 and the trench 3;

S6. Perform selective doping to form a first conductivity type source region. The first conductivity type source region penetrates the second conductivity type channel layer and extends into the second conductivity type well region, and is adjacent to the trench;

S7. Etch the second conductive type channel layer to form an etching window for the second conductive type channel layer. The etching window for the second conductive type channel layer is periodically formed on the second conductive type channel layer along the direction of the gate bar. Distribution, the etching window of the second conductivity type channel layer penetrates the second conductivity type channel layer and stops on the sacrificial layer;

S8. Remove the sacrificial layer;

S9. Grow a gate dielectric layer, including a first gate dielectric layer located on the inner surface of the trench, a second gate dielectric layer located on the upper surface of the second conductive type channel layer, and an inner wall of the etching window of the second conductive type channel layer. the third gate dielectric layer on;

S10. Grow the gate electrode material and etch it to form a gate electrode, including a first gate electrode filling the trench, a second gate electrode covering part of the upper surface of the second gate dielectric layer, and etching the channel layer filling the second conductivity type. a third gate electrode that has a window and is wrapped by a third gate dielectric layer;

S11. Grow an isolation dielectric layer to form source ohms, drain ohms, source thickened metal and drain thickened metal.

Preferably, the sacrificial layer uses a carbon film or medium. When using a carbon film, the filling method includes photoresist coating, carbonization and surface planarization processes. When removed, high-temperature thermal oxidation is used, and the oxidation temperature does not exceed 1150 degrees Celsius; the sacrificial layer Remove by wet etching when using dielectric.

Preferably, the deposited thickness of the second conductive type channel layer ranges from 10 nm to 250 nm. When the gate dielectric layer is formed by thermal oxidation, the deposited thickness of the second conductive type channel layer ranges from 80 nm to 250 nm. When the gate dielectric layer is formed by thermal oxidation, When the layer is formed by deposition, the deposition thickness of the second conductivity type channel layer is 10nm~120nm.

Preferably, the process of forming the etching window in step S7 includes: defining the location of the trench as a trench etching area, and mapping the projection of the trench etching area onto the second conductive type channel layer to form several second The etching window of the conductive type channel layer, the length of the etching window of the second conductive type channel layer in the x direction is not less than 1.0um; the width of the etching window of the second conductive type channel layer in the y direction is not less than 0.8um; The spacing between the etching windows of the two conductivity type channel layers ranges from 1.5um to 2.0um; the boundary distance between the etching windows of the second conductivity type channel layer and the trench etching area ranges from 0.1um to 1.0um.

Beneficial effects:

(1) The present invention adopts a surrounding gate channel design and uses upper and lower double-layer gate electrodes to realize gate-controlled conduction of the channel, which can obtain ultra-high channel mobility and greatly reduce the on-resistance of the device.

(2) The present invention uses the atomic layer deposition (ALD) process to realize the production of ultra-thin channel layers, which facilitates precise process control and has the ability to control mass production processes;

(3) The present invention deposits the sacrificial layer in the etching trench and removes the sacrificial layer before making the gate dielectric to realize the production of upper and lower double-layer gate electrodes, which provides the design structure of the present invention with a method that is compatible with the existing process. The production method has high practical value.

Description of the drawings

Figure 1 is a schematic cross-sectional view of a surround-gate channel silicon carbide field effect transistor of the present invention along the direction perpendicular to the gate bar, that is, the xz plane;

Figure 2 is a three-dimensional schematic diagram of a surround-gate channel silicon carbide field effect transistor according to Embodiment 1;

Figure 3 is a schematic cross-sectional view along the xz plane in the direction perpendicular to the grid bars in Embodiment 1;

Figure 4 is a schematic cross-sectional structural diagram of Embodiment 1 corresponding to the position A-A’ in Figure 2;

Figures 5 to 13 are flow charts for manufacturing a surround-gate channel silicon carbide field effect transistor according to Embodiment 1 of the present invention, in which (A) and (B) are corresponding to the same step and are perpendicular to the direction of the gate bar, that is, the xz plane. The cross-sectional schematic diagram and the cross-sectional structural diagram corresponding to the position A-A' in Figure 2;

Figure 14 is a schematic diagram comparing the etching patterns of the second conductivity type well region, the second conductivity type channel layer and the gate electrode on the xy plane in Embodiment 1;

Figure 15 is a three-dimensional schematic diagram of the etching pattern of the second conductivity type channel layer in Embodiment 1;

Figure 16 is a schematic diagram comparing the etching patterns of the second conductivity type well region, the second conductivity type channel layer and the gate electrode on the xy plane in Embodiment 2;

Figure 17 is a three-dimensional schematic diagram of the etching pattern of the second conductivity type channel layer in Embodiment 2;

Figure 18 is a schematic cross-sectional structural diagram of Embodiment 2 corresponding to the position A-A’ in Figure 2;

Among them, 1. First conductivity type SiC epitaxial layer; 2. Second conductivity type well region; 3. Trench; 3-1. Sacrificial layer; 4. Second conductivity type channel layer; 5. First conductivity type source area; 6. The second conductivity type heavily doped area; 7. The first conductivity type current expansion area; 8. Gate dielectric layer; 8-1. The first gate dielectric layer; 8-2. The second gate dielectric layer; 8 -3. Third gate dielectric layer; 9. Gate electrode; 9-1. First gate electrode; 9-2. Second gate electrode; 9-3. Third gate electrode; 10. Isolation dielectric layer; 11. Source Extreme ohmic; 12. Gate electrode etching area; 13. Trench etching area; 14. Second conductivity type channel layer etching window.

Implementation

A wrap-around gate channel silicon carbide field effect transistor and a manufacturing method thereof according to the present invention will be further explained and described below with reference to the accompanying drawings.

Example 1

As shown in Figures 2, 3 and 4, a surround gate channel silicon carbide field effect transistor includes:

First conductivity type SiC epitaxial layer 1;

The second conductivity type well region 2 is located in the first conductivity type SiC epitaxial layer 1; the second conductivity type well region 2 is doped with Al, and the junction depth from the upper surface of the epitaxial layer is 1.5um.

In the first conductivity type SiC epitaxial layer 1, the trench 3 adjacent to the second conductivity type well region 2; define the x direction as the device length direction, which is also the horizontal direction in Figure 1, and the y direction as the device width direction, which is also the gate strip The direction is also the vertical direction of the paper in Figure 1. The z direction is the device height direction, which is also the vertical direction of Figure 1. The first conductive type SiC epitaxial layer 1 between adjacent trenches 3 in the x direction is defined as the device neck area; As shown in Figure 2, the direction AA' is the direction of the gate bars of the device, and the trench 3 is continuous along the direction of the gate bars.

The depth of trench 3 is greater than 0.5um, and the width of trench 3 along the x direction is greater than 0.3um and less than 1.5um; the preferred width is greater than 0.5um and less than 1.2um; the bottom depth of trench 3 is shallower than the second conductive type well region 2, The difference should be greater than 0.2um, preferably greater than 0.5um; the second conductive type well region 2 does not completely cover the trench 3, and the trench 3 is in close proximity to the adjacent second conductive type well region 2 The lateral boundary difference on one side of the device neck area should be less than 0.8um, recommended to be less than 0.5um, preferably less than 0.2um;

In some embodiments of the present invention, the width of the trench 3 ranges from 1.2um to 1.5um, and the depth of the trench 3 ranges from 0.8um to 1.0um. The boundary distance between the trench 3 and the second conductivity type well region 2 on the side close to the neck region in the x direction ranges from 0.3um to 0.5um.

The second conductive type channel layer 4 is located above the first conductive type SiC epitaxial layer 1, the second conductive type well region 2 and the trench 3; the thickness of the second conductive type channel layer 4 does not exceed 120 nm, and the recommended thickness is less than 80nm, preferably less than 50nm;

In some embodiments of the present invention, the thickness of the second conductive type channel layer 4 ranges from 50 nm to 60 nm.

The second conductive type channel layer 4 has second conductive type channel layer etching windows periodically distributed along the y direction, and the second conductive type channel layer etching windows penetrate the second conductive type channel layer. 4 and contact the trench 3 to facilitate the removal of the sacrificial layer and the connection with the gate electrode during the device manufacturing process. The boundary distance L2 between the etching window of the second conductive type channel layer and the trench 3 ranges from 0.1um to 1.0um, and the preferred range is 0.1um to 0.5um; the width W in the y direction of the etching window of the second conductive type channel layer Not less than 0.8um, preferably not less than 1.5um; the x-direction length L of the second conductivity type channel layer etching window is not less than 1.0um, preferably not less than 1.5um; the spacing between the second conductivity type channel layer etching windows The range of W1 is 1.5um~2.0um; see Figure 14.

In some embodiments of the present invention, as shown in Figure 14, the width W of the etching window of the second conductive type channel layer ranges from 1.5um to 2.0um, and the length L ranges from 1um to 1.2um. The channel layer etching window spacing W1 ranges from 1.5um to 2.0um, and the boundary distance L2 between the second conductivity type channel layer etching window and trench 3 is about 0.15um.

The first conductivity type source region 5 penetrates the second conductivity type channel layer 4, extends into the second conductivity type well region 2 and is adjacent to the trench 3;

Different from the surrounding gate channel silicon carbide field effect transistor shown in Figure 1, as shown in Figure 3, this embodiment also includes a second conductivity type channel layer 4 that penetrates and extends into a second conductivity type well. The second conductivity type heavily doped region 6 in region 2 and away from the trench 3; the depth range of the second conductivity type heavily doped region 6 is 0.6um~1.0um, and the peak doping concentration is greater than 1E19cm ^-3 ;

Penetrating the second conductivity type channel layer 4 and extending into the first conductivity type SiC epitaxial layer 1, the first conductivity type current expansion region 7 is located in the middle of the device neck region; the width of the first conductivity type current expansion region is greater than 0.5um. ; In some embodiments of the present invention, the depth range of the first conductive type current expansion region 7 is 0.8~1.2um, and the width range is 0.6um~1.0um;

The gate dielectric layer 8 includes a first gate dielectric layer 8-1 located on the inner surface of the trench 3, a second gate dielectric layer 8-2 located on the upper surface of the second conductive type channel layer 4, and a second gate dielectric layer 8-2 located on the upper surface of the second conductive type channel layer 4. Type channel layer etches the third gate dielectric layer 8-3 on the inner wall of the window; the gate dielectric layer 8 is made of silicon oxide, and the thickness range is 30nm~100nm, the preferred range is 50nm~100nm; the optimal range is 60nm~80nm . In some other embodiments of the present invention, the gate dielectric layer 8 can be made of materials such as Al ₂ O ₃ , HfO ₂ , and AlON, and the thickness range can be adjusted according to the material.

The gate electrode 9 includes a first gate electrode 9-1 that fills the trench 3 and is wrapped by the first gate dielectric layer 8-1, and a second gate electrode 9-2 that covers part of the upper surface of the second gate dielectric layer 8-2. , and the third gate electrode 9-3 that fills the etching window of the second conductivity type channel layer and is wrapped by the third gate dielectric layer 8-3; the gate electrode 9 is made of doped polysilicon, and the thickness of the second gate electrode 9-2 The range is 600nm~800nm. The boundary distance L1 between the boundary of the second gate electrode 9-2 and the trench 3 is greater than 0.2um, and the preferred range is 0.3um~0.6um. The second gate electrode 9-2 and the first gate electrode 9-1 are connected through the etching window of the second conductive type channel layer in the second conductive type channel layer 4, that is, through the third gate electrode 9-3. Specifically, See Figure 4. The first gate electrode 9-2 completely fills the trench 3, and there is no void in the trench 3. In some other embodiments of the present invention, the gate electrode 9 can also be a metal electrode, and the material of the gate electrode 9 can be selected according to actual needs.

The isolation dielectric layer 10 covers the second gate electrode 9-2 and the second gate dielectric layer 8-2, and also covers part of the first conductivity type source region 5; the isolation dielectric layer 10 is made of silicon dioxide, silicon nitride, or silicon dioxide. A composite of silicon and silicon nitride, the thickness range is 0.2um~1.0um.

The source ohm 11 is connected to part of the second conductivity type channel layer 4 , part of the first conductivity type source region 5 and the second conductivity type heavily doped region 6 .

Specifically, in addition to the above parts, a surround gate channel silicon carbide field effect transistor of the present invention should also have a first conductive type SiC substrate located on the lower surface of the first conductive type SiC epitaxial layer 1, located on the first conductive type SiC substrate. Drain ohms and drain thickening metal on the lower surface of the type SiC substrate, and source thickening metal covering the isolation dielectric layer 10 and source ohms 11 .

In some examples of the present invention, the first conductivity type is N-type, and the second conductivity type is P-type. The P-type doping of SiC basically uses only Al, and the N-type doping basically uses nitrogen.

This embodiment adopts a strip-shaped unit cell design, that is, strip-shaped gate electrodes are periodically arranged to form a device structure.

The concentration and thickness of the first conductive type SiC epitaxial layer 1 are related to the device voltage level. For example, a SiC MOSFET device with a 650V voltage resistance specification usually corresponds to an N-type SiC with a doping concentration of 1E16cm ^-3 ~ 2E16cm ^-3 and a thickness of 5um ~ 6um. Epitaxial materials.

The manufacturing method of a surround gate channel silicon carbide field effect transistor of the present invention is shown in Figures 5 to 13. The specific steps are:

S1. Epitaxy the first conductive type SiC epitaxial layer 1 on the first conductive type SiC substrate;

S2. As shown in Figure 5 (A) and Figure 5 (B), the second conductive type well region 2 is selectively implanted in the first conductive type SiC epitaxial layer 1; the second conductive type well region 2 is formed by one injection or Formed by multiple epitaxial implants, the multiple epitaxial implantation method can be: first conduct the second conductivity type implant, then conduct additional first conductivity type epitaxy, and finally conduct the second conductivity type implant, in which the doping of the first conductivity type epitaxy The concentration is basically the same as the epitaxial concentration in S1, and the thickness is within the penetrable range of the implantation depth, such as 1um; the second conductive type implantation for the second time is the same as the first implantation area, and the second conductive type implantation for the second time Need to penetrate the new 1um epitaxial layer. Through this method, the final second conductivity type implantation region can be made deeper; specifically, in some embodiments of the present invention, it is formed using a multi-energy injection method, and the highest injection energy is 600keV~640keV. After S2, the first conductivity type can be selectively doped and connected to the first conductivity type source region 5 in the subsequent S6 to reduce the source region series circuit, that is, to make the first conductivity type source region 5 deeper. The first conductivity type is selectively doped to form a deeper first conductivity type source region 5, and the same mask pattern is used for the implantation pattern and the implantation of the first conductivity type source region 5 in S6. After S2, the second conductivity type can be selectively doped to form a heavily doped region in the second conductivity type well region away from the neck region to improve the body diode characteristics; that is, the second conductivity type heavily doped region 6 is deeper, and a deeper second conductivity type heavily doped region 6 is formed through selective doping of the second conductivity type here.

S3. As shown in Figure 6 (A) and Figure 6 (B), the trench 3 is formed through photolithography and etching processes; specifically, the first conductive type SiC epitaxial layer 1 and the second conductive type well are first A trench etching area 13 is set at the junction of area 2, and trench 3 is formed on the trench etching area 13. The length and width of the trench etching area 13 are the same as the length and width of trench 3; trench 3 is located at the The junction of a conductive type SiC epitaxial layer 1 and a second conductive type well region 2, and the bottom of the trench 3 is higher than the second conductive type well region 2, that is to say, the etching depth of the trench 3 is not greater than the second conductive type well region Zone 2 Depth. The trench 3 is continuous in the direction along the grating. The depth of trench 3 is greater than 0.5um, and the width of trench 3 along the x direction is greater than 0.3um and less than 1.5um; the preferred width is greater than 0.5um and less than 1.2um; the bottom depth of trench 3 is shallower than the second conductive type well region 2, The difference should be greater than 0.2um, preferably greater than 0.5um;

S4. As shown in Figure 7(A) and Figure 7(B), fill the trench 3 with the sacrificial layer 3-1; the sacrificial layer 3-1 is used to fill the trench 3 to make the device surface flat and facilitate subsequent deposition. channel layer. The sacrificial layer 3-1 uses a carbon film, and the filling method includes photoresist coating, carbonization and surface planarization processes; the sacrificial layer can also be a medium. The sacrificial layer 3-1 completely fills the trench 3; after the sacrificial layer 3-1 is deposited, an additional planarization process can be performed to remove the sacrificial layer 3-1 on the non-trench 3 surface to keep the overall surface flat;

S5. As shown in Figure 8(A) and Figure 8(B), deposit the second conductivity type channel layer 4; the second conductivity type channel layer 4 is located in the first conductivity type SiC epitaxial layer 1 and the second conductivity type. Above the well region 2 and the trench 3; specifically, the second conductivity type channel layer 4 is deposited by ALD to grow the second conductivity type SiC, and the deposition temperature does not exceed 1000°C, preferably no more than 800°C. The second conductivity type The deposition thickness of the channel layer 4 ranges from 10 nm to 250 nm, and the preferred deposition thickness range is from 50 nm to 60 nm to achieve the growth of an ultra-thin second conductive type channel layer. Among them, when the gate dielectric layer is formed by thermal oxidation, the recommended deposition thickness of the second conductive type channel layer is 80nm~250nm. When the gate dielectric layer is formed by deposition, the recommended deposition thickness of the second conductive type channel layer is is 10nm~120nm; because the thickness of the second conductivity type channel layer remains unchanged when the gate dielectric layer is formed by deposition, but when the gate dielectric layer is formed by thermal oxidation, the second conductivity type channel layer will be consumed SiC, makes the channel layer thinner, so the recommended deposition thickness of the second conductivity type channel layer needs to be increased. In this embodiment, the atomic layer deposition (ALD) process is used to realize the production of ultra-thin channel layers, which facilitates precise process control and has the ability to control mass production processes;

S6. As shown in Figure 9 (A) and Figure 9 (B), the first conductive type source region 5 is selectively implanted on the device surface formed in step S5, and the first conductive type source region 5 penetrates the second conductive type. The channel layer 4 extends into the second conductivity type well region 2 and is adjacent to the trench 3. In this embodiment, the first conductivity type source region 5 is in contact with the trench 3 away from the device neck region; in the present invention In other preferred solutions, the second conductivity type heavily doped region 6 and the first conductivity type current expansion region 7 can be selectively implanted on the device surface formed in step S5; wherein the second conductivity type heavily doped region 6 penetrates the first conductivity type current expansion region 6. The second conductivity type channel layer 4 extends into the second conductivity type well region 2 and away from the trench 3 and the device neck region; the first conductivity type current expansion region 7 penetrates the second conductivity type channel layer 4 and extends to the first conductivity type channel layer 4 . Type SiC epitaxial layer 1, and is located in the middle of the device neck area; the device neck area refers to the first conductivity type SiC epitaxial layer 1 between adjacent trenches 3; the width of the first conductivity type current expansion area is greater than 0.5um;

S7. As shown in Figure 10 (A) and Figure 10 (B), the second conductive type channel layer 4 is etched to form the second conductive type channel layer etching window 14. The second conductive type channel layer The etching windows 14 are periodically distributed along the y direction on the second conductive type channel layer 4. The etching windows 14 of the second conductive type channel layer penetrate the second conductive type channel layer 4 and stop at the sacrificial layer 3-1. to facilitate the subsequent removal of the sacrificial layer 3-1 and the deposition of the gate dielectric layer 8; there is an additional high-temperature activation annealing process before etching the second conductivity type channel layer 4, and the annealing temperature range is 1500°C~1700°C. As shown in Figures 14 and 15, the projection of the trench etching area 13 is mapped to the device surface formed in S6, that is, several second conductive type channel layer etching windows 14 are formed on the second conductive type channel layer 4. , in this embodiment, all the second conductivity type channel layer etching windows have the same shape, that is, the length, width and depth are exactly the same; the spacing between the second conductivity type channel layer etching windows 14 is W1; the second conductivity type The boundary distance between the channel layer etching window and the trench etching area 13 is L2. The range of L2 is 0.1um~1.0um, and the preferred range is 0.1um~0.5um. The width of the second conductive type channel layer etching window is W. Not less than 0.8um, preferably not less than 1.5um; the etching window length L of the second conductive type channel layer is not less than 1.0um, preferably not less than 1.5um; in this embodiment, L2 is about 0.15um; the second conductive type channel layer The width W of the etching window ranges from 1.5um to 2.0um, the length L ranges from 1um to 1.2um, and the etching window spacing W1 of the adjacent second conductive type channel layer ranges from 1.5um to 2.0um.

S8. Remove the sacrificial layer 3-1; when the sacrificial layer 3-1 is a carbon film, use high-temperature thermal oxidation to remove it. The oxidation temperature is recommended not to exceed 1150°C; the preferred oxidation temperature range is 900°C~1000°C. When the sacrificial layer 3-1 is a dielectric, it is removed by wet etching. There should be a high-temperature activation annealing before S9, and the temperature should not be lower than 1400°C. In particular, when a dielectric is used as the sacrificial layer 3-1, the activation annealing should be set after the sacrificial layer 3-1 is removed. In this embodiment, the sacrificial layer 3-1 uses media such as silicon oxide SiO ₂ and silicon nitride Si ₃ N _4. The corresponding wet etching solutions are different. For example, SiO ₂ is usually etched with BOE, and Si ₃ N ₄ is usually etched with phosphoric acid. corrosion.

S9. As shown in Figure 11 (A) and Figure 11 (B), deposit the gate dielectric layer 8, including the first gate dielectric layer 8-1 located on the inner surface of the trench 3 and the second conductive type channel layer. The second gate dielectric layer 8-2 on the upper surface of 4, and the third gate dielectric layer 8-3 located on the inner wall of the etching window 14 of the second conductivity type channel layer; as can be seen from Figure 11 (A) The first gate dielectric layer 8-1 on the inner surface of the trench 3 and the second gate dielectric layer 8-2 on the upper surface of the second conductivity type channel layer 4 can be seen from Figure 11(B). The first gate dielectric layer 8-1 on the inner surface of the trench 3, the second gate dielectric layer 8-2 on the upper surface of the second conductivity type channel layer 4, and the etching window 14 of the second conductivity type channel layer The third gate dielectric layer 8-3 on the inner wall; it should be noted that at this time, the gate dielectric layer 8 did not fill the trench 3 during the deposition process. The gate dielectric layer 8 can be grown by thermal oxidation or LPCVD deposition. After the gate dielectric layer 8 is grown, it is provided with an additional high-temperature annealing treatment;

S10. As shown in Figure 12(A) and Figure 12(B), the gate electrode 9 material is deposited and etched to form the first gate electrode 9-1, the second gate electrode 9-2 and the third gate electrode 9- 3; The second gate electrode 9-2 covers part of the upper surface of the second gate dielectric layer 8-2, the first gate electrode 9-1 fills the trench 3 and is wrapped by the first gate dielectric layer 8-1, and the third gate electrode 9-3 fills the etching window 14 of the second conductivity type channel layer and is wrapped by the third gate dielectric layer 8-3, and the third gate electrode 9-3 connects the first gate electrode 9-1 and the second gate electrode 9-2 ; The first gate electrode 9-1 and the second gate electrode 9-2 can be seen from Figure 12 (A), and the first gate electrode 9-1 and the second gate electrode 9 can be seen from Figure 12 (B) -2 and the third gate electrode 9-3; the second gate electrode 9-2 covers part of the upper surface of the second gate dielectric layer 8-2. In this step, the gate is first deposited entirely on the second gate dielectric layer 8-2. For the electrode material, gate electrode etching areas 12 are provided on both sides of the device surface formed at this time, and the gate electrode material in the gate electrode etching area 12 is etched to leak out the second gate dielectric layer 8-2 on both sides; As shown in Figure 14, the distance between the gate electrode etching region 12 and the trench etching region 13 is L1. The distance L1 is not less than 0.1um, preferably not less than 0.3um. L1 is also the boundary between the second gate electrode 9-2 and The boundary spacing of trench 3; the gate electrode is made of doped polysilicon, and the deposition thickness is 600nm~800nm. The growth of gate electrode 9 needs to use a partial isotropic growth method to ensure that trench 3 is completely filled without voids;

S11. As shown in Figure 13 (A) and Figure 13 (B), deposit the isolation dielectric layer 10 to form the source ohm 11, the drain ohm, the source thickened metal and the drain thickened metal. The isolation dielectric layer 10 covers the second gate electrode 9-2 and the second gate dielectric layer 8-2, and also covers part of the first conductivity type source region 5; the source ohm 11 and part of the second conductivity type channel layer 4, part of the The first conductivity type source region 5 is in contact with the second conductivity type heavily doped region 6 and is in contact with part of the sidewall of the isolation dielectric layer 10 . The drain ohm and the drain thickening metal are located on the lower surface of the first conductive type SiC substrate, and the source thickening metal covers the isolation dielectric layer 10 and the source ohm 11 .

The present invention adopts the deposition of the sacrificial layer in the etching trench and the removal of the sacrificial layer before making the gate dielectric to realize the production of upper and lower double-layer gate electrodes. Compared with the conventional vertical SiC FinFET, the present invention uses ALD film to control the trench. The thickness of the channel layer avoids the use of high-precision (50nm~100nm) level longitudinal line width control, provides the design structure of the present invention with a manufacturing method compatible with existing processes, and has high practical value.

Example 2

The structure of Embodiment 2 is similar to that of Embodiment 1. The difference is that the grooves 3 are discontinuous in the y direction and are periodically distributed rectangles, as shown in Figures 16 and 17. Figure 18 is a schematic cross-sectional structural diagram along the position A-A’ in Figure 2 in Embodiment 2. The manufacturing process of Embodiment 2 is basically the same as that of Embodiment 1. The difference is that the trenches 3 etched by the trench etching area 13 in S3 are discontinuous in the y direction and are periodically distributed rectangles, as shown in Figure 16 As shown, each trench etching area 13 covers an integral number of second conductivity type channel layer etching windows 14. In this embodiment, each trench etching area 13 covers two second conductivity type channel layer etching windows. window 14. The second conductive type channel layer etching window length L, the second conductive type channel layer etching window width W, the adjacent second conductive type channel layer etching window spacing W1, the gate electrode etching area 12 and the trench The value range of the spacing L1 between the etched areas 13 is the same as that in Embodiment 1.

This embodiment sacrifices part of the surrounding gate channel in exchange for a part of the vertical channel in the non-surrounding gate area, which can be used as an alternative to Embodiment 1.

As shown in the middle of Figure 18, the second conductive type channel layer 4 is a non-surrounding gate area, but this area is not only affected by the upper gate electrode, but also affected by the gate electrodes on the left and right sides, forming a channel extending in the vertical area. There is no impact on overall device functionality.

It can be seen from the overall content of the present invention and the above two embodiments that the present invention adopts a surround gate channel design and uses upper and lower double-layer gate electrodes to achieve gate-controlled conduction of the channel, which can achieve ultra-high channel mobility and greatly Reduce the on-resistance of the device to a certain extent. Reference (Enhanced Performance of 50 nm Ultra-Narrow-Body SiliconCarbide MOSFETs based on FinFET effect, DOI: 10.1109/ISPSD46842.2020.9170182), which discloses a MOSFET structure based on a traditional trench and controls the channel width to below the 100nm scale , ultra-high channel mobility can be obtained, but in the traditional SiC trench MOSFET structure, the current in the channel area is conducted vertically, and the goal of narrowing the channel layer is achieved by narrowing the size of adjacent trenches. However, the process of this structure is extremely difficult, and extremely narrow line width control is required to achieve this structure. On the one hand, usually the characteristic size of SiC power devices is 0.5um~1um, which can be satisfied by using 0.35um or 0.18um photolithography equipment. However, the reference structure requires 45nm-level photolithography. Considering the overlay deviation, etc., it may require more High; on the other hand, SiC itself is more difficult to etch than Si material, and it is difficult to control this large aspect ratio etching process, which is not conducive to high-consistency mass production; in the present invention, according to the above-mentioned ultra-high groove The realization principle of channel mobility is based on the conventional planar SiC MOSFET structure, using a breakthrough upper and lower surrounding gate design. The channel current is changed from the original upper and lower flow to a planar flow, transforming the demand for ultra-narrow channels into ultra-thin The structure of the channel layer can be realized by atomic layer deposition ALD, and the process difficulty is greatly reduced. The ultra-thin channel layer (<150nm) generated by ALD is the first major feature of this invention. In order to realize the structure of the upper and lower electrodes sandwiching the channel, considering the need for SiC ultra-high temperature carrier activation, it is impossible to adopt the layer-by-layer deposition method of gate electrode-channel layer-gate electrode. Therefore, the present invention creatively forms a suspended trench first. Channel layer structure, a process method of post-filling the gate dielectric and polysilicon gate electrode, and this structure requires the construction and removal of the sacrificial layer, so the etching window on the channel layer and the process related to the sacrificial layer are the second major part of the present invention. Features. Through the structure and process flow design of the present invention, ultra-high channel mobility can be achieved, and process capability requirements and process control requirements are simplified. It is suitable for large-scale product mass production, has both innovation and practicality, and has huge potential. development potential and practical prospects.

The above are only the preferred embodiments of the present invention. It should be pointed out that those of ordinary skill in the art can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications can also be made. should be regarded as the protection scope of the present invention.

Claims (10)

1. A surround-gate channel silicon carbide field effect transistor, characterized in that it includes: First conductivity type SiC epitaxial layer; a second conductivity type well region in the first conductivity type SiC epitaxial layer; In the first conductivity type SiC epitaxial layer, the trench adjacent to the second conductivity type well region defines the x direction as the device length direction, the y direction as the device width direction, which is also the gate bar direction, and the z direction as the device height direction; x The first conductivity type SiC epitaxial layer between adjacent trenches in the direction is defined as the device neck region; A first conductivity type SiC epitaxial layer, a second conductivity type well region and a second conductivity type channel layer on the trench; a first conductivity type source region that penetrates the second conductivity type channel layer and extends into the second conductivity type well region, and is adjacent to the trench; Etch windows of the second conductive type channel layer are periodically distributed along the direction of the gate strips on the second conductive type channel layer, penetrate the second conductive type channel layer and contact the trench; The gate dielectric layer includes a first gate dielectric layer located on the inner surface of the trench, a second gate dielectric layer located on the upper surface of the second conductive type channel layer, and located on the inner wall of the etching window of the second conductive type channel layer. The third gate dielectric layer; The gate electrode includes a first gate electrode that fills the trench and is wrapped by the first gate dielectric layer, a second gate electrode that covers part of the upper surface of the second gate dielectric layer, and an etched window that fills the second conductivity type channel layer and is The third gate electrode wrapped by the third gate dielectric layer; the second gate electrode and the first gate electrode are distributed on the upper and lower sides of the second conductive type channel layer, in the non-second conductive type channel of the second conductive type channel layer The layer etching window is not directly connected, and the second gate electrode and the first gate electrode are connected through the third gate electrode at the etching window of the second conductivity type channel layer; an isolation dielectric layer covering the second gate electrode and the second gate dielectric layer and covering part of the first conductive type source region; The source ohm is connected to part of the second conductivity type channel layer and part of the first conductivity type source region. 2. A surround-gate channel silicon carbide field effect transistor according to claim 1, characterized in that: the trench is continuous along the direction of the gate bar, or is a periodically distributed rectangle; the trench is in the z direction. The projection on completely covers the etching window of the second conductive type channel layer; the depth of the trench is greater than 0.5um, and the width of the trench along the x direction is greater than 0.3um and less than 1.5um; the depth of the bottom of the trench is shallower than that of the second conductive type channel layer. In the conductive type well region, the difference between the two is greater than 0.2um, and the distance between the boundary of the second gate electrode and the trench is greater than 0.2um. 3. A surround-gate channel silicon carbide field effect transistor according to claim 1, characterized in that: the second conductivity type well region does not completely cover the trench, and the trench is connected to the adjacent well region. The lateral boundary difference of the second conductivity type well region on the side close to the device neck region is less than 0.8um. 4. A surround-gate channel silicon carbide field effect transistor according to claim 1, wherein the thickness of the second conductive type channel layer does not exceed 120 nm. 5. A surround-gate channel silicon carbide field effect transistor according to claim 1, characterized in that: the length of the second conductivity type channel layer etching window in the x direction is not less than 1.0um; the second conductivity type The width of the channel layer etching window in the y direction is not less than 0.8um; the spacing between the second conductive type channel layer etching windows is 1.5um~2.0um; the second conductive type channel layer etching window and the trench The boundary distance range is 0.1um~1.0um. 6. A surround-gate channel silicon carbide field effect transistor according to claim 1, further comprising: a second conductivity type heavily doped region penetrating the second conductivity type channel layer, extending into the second conductivity type well region and away from the trench; The first conductivity type current expansion region runs through the second conductivity type channel layer and extends into the first conductivity type SiC epitaxial layer, and is located in the middle of the device neck region. 7. A method for manufacturing a surround gate channel silicon carbide field effect transistor, which is characterized by including the following steps: S1. Form a first conductive type SiC epitaxial layer on the first conductive type SiC substrate; S2. Selectively dope the first conductive type epitaxial layer to form a second conductive type well region; S3. Etch the first conductive type SiC epitaxial layer to form a trench; S4. Form a sacrificial layer in the trench; S5. Form a second conductivity type channel layer on the first conductivity type SiC epitaxial layer 1, the second conductivity type well region 2 and the trench 3; S6. Perform selective doping to form a first conductivity type source region. The first conductivity type source region penetrates the second conductivity type channel layer and extends into the second conductivity type well region, and is adjacent to the trench; S7. Etch the second conductive type channel layer to form an etching window for the second conductive type channel layer. The etching window for the second conductive type channel layer is periodically formed on the second conductive type channel layer along the direction of the gate bar. Distribution, the etching window of the second conductivity type channel layer penetrates the second conductivity type channel layer and stops on the sacrificial layer; S8. Remove the sacrificial layer; S9. Grow a gate dielectric layer, including a first gate dielectric layer located on the inner surface of the trench, a second gate dielectric layer located on the upper surface of the second conductive type channel layer, and an inner wall of the etching window of the second conductive type channel layer. the third gate dielectric layer on; S10. Grow the gate electrode material and etch it to form a gate electrode, including a first gate electrode filling the trench, a second gate electrode covering part of the upper surface of the second gate dielectric layer, and etching the channel layer filling the second conductivity type. The third gate electrode is windowed and wrapped by the third gate dielectric layer; the second gate electrode and the first gate electrode are distributed on the upper and lower sides of the second conductive type channel layer, and the non-second conductive parts of the second conductive type channel layer are The etching window of the type channel layer is not directly connected, and the second gate electrode and the first gate electrode are connected through the third gate electrode at the etching window of the second conductivity type channel layer; S11. Grow an isolation dielectric layer to form source ohms, drain ohms, source thickened metal and drain thickened metal. 8. A method for manufacturing a surround-gate channel silicon carbide field effect transistor according to claim 7, wherein the sacrificial layer adopts a carbon film or dielectric, and when a carbon film is used, the filling method includes photoresist coating. , carbonization and surface planarization process, high-temperature thermal oxidation is used for removal, and the oxidation temperature does not exceed 1150 degrees Celsius; the sacrificial layer is removed by wet etching when using dielectric. 9. A method for manufacturing a surround-gate channel silicon carbide field effect transistor according to claim 7, wherein the deposition thickness of the second conductive type channel layer ranges from 10 nm to 250 nm, wherein when the gate dielectric When the layer is formed by thermal oxidation, the deposition thickness of the second conductivity type channel layer is 80nm~250nm. When the gate dielectric layer is formed by deposition, the deposition thickness of the second conductivity type channel layer is 10nm~120nm. 10. A method for manufacturing a surround-gate channel silicon carbide field effect transistor according to claim 7, characterized in that the process of forming the etching window in step S7 includes: the location of the trench is defined as the trench etching. The etched area, the projection of the trench etched area is mapped onto the second conductive type channel layer to form several second conductive type channel layer etching windows, the length of the second conductive type channel layer etching window in the x direction Not less than 1.0um; the width of the etching window of the second conductive type channel layer in the y direction is not less than 0.8um; the spacing between the etching windows of the second conductive type channel layer ranges from 1.5um to 2.0um; the second conductive type The boundary distance between the channel layer etching window and the trench etching area ranges from 0.1um to 1.0um.