CN116709854A - Display substrate and display device - Google Patents

Abstract

A display substrate and a display device, wherein the display substrate has a display area and a non-display area, the display area is provided with an array of sub-pixels and a plurality of first signal lines, and the non-display area is provided with a first power supply line to a second N power supply lines, the first signal line at least partially extends along the first direction, any power supply line from the first power supply line to the Nth power supply line at least partially extends along the second direction, the first signal line is electrically connected to the sub-pixel, and is Configured to provide initial signals to sub-pixels; the display area is divided into M display sub-areas arranged along the second direction, the first signal lines in the same display sub-area are connected to the same power supply line, and at least two display sub-areas The first signal lines are connected to different power supply lines.

Description

Display substrate and display device

technical field

The present disclosure relates to the field of display technology, in particular to a display substrate and a display device.

Background technique

Organic Light Emitting Diode (OLED for short) and Quantum-dot Light Emitting Diodes (QLED for short) are active light-emitting display devices with self-illumination, wide viewing angle, high contrast, low power consumption, high The advantages of response speed, thinness, bendability and low cost. With the continuous development of display technology, a flexible display device (Flexible Display), which uses OLED or QLED as a light-emitting device and is signal-controlled by a Thin Film Transistor (TFT for short), has become a mainstream product in the display field.

Contents of the invention

The following is an overview of the topics described in detail in this article. This summary is not intended to limit the scope of the claims.

In a first aspect, the present disclosure provides a display substrate, which has a display area and a non-display area, the display area is provided with sub-pixels arranged in an array and a plurality of first signal lines, and the non-display area is provided with a first From the power supply line to the Nth power supply line, the first signal line at least partially extends along the first direction, any power supply line from the first power supply line to the Nth power supply line at least partially extends along the second direction, and the first signal line extends at least partially along the second direction. a direction intersects the second direction;

The first signal line is electrically connected to the sub-pixel and configured to provide an initial signal to the sub-pixel;

The display area is divided into M display sub-areas arranged along the second direction, the first signal lines in the same display sub-area are connected to the same power supply line, and the first signal lines in at least two display sub-areas Connect different power supply lines, M, N≥2.

In an exemplary embodiment, the display area is provided with a plurality of first initial signal lines and a plurality of second initial signal lines extending along the first direction, and the sub-pixel includes a pixel driving circuit and a light emitting device, so The pixel driving circuit is configured to drive the light-emitting device to emit light, the pixel driving circuit includes: a driving transistor, the light-emitting device includes: a first electrode, and the first initial signal line is configured to connect to the driving transistor One of the source and drain electrodes provides an initial signal, and the second initial signal line is configured to provide an initial signal to the first electrode of the light emitting device;

The first signal line includes any one of a first initial signal line and a second initial signal line.

In an exemplary embodiment, the display area is further provided with a plurality of third initial signal lines extending along the first direction, and the third initial signal lines are configured to feed into the source-drain electrodes of the driving transistors. The other electrode of provides the initial signal;

The first signal line includes any one of a first initial signal line, a second initial signal line and a third initial signal line.

In an exemplary embodiment, when the first signal line is the second initial signal line, M=K or 2K-1, and K is the second initial signal line within the target duration to effectively initialize the first electrode of the light emitting device The effective initialization refers to the second initial signal line adjusting the first electrode of the light emitting device from the first signal to the second signal, the voltage value of the first signal is different from the voltage value of the second signal, so The second signal is a signal transmitted by the second initial signal line, and the target duration is equal to the duration of one display frame.

In an exemplary embodiment, when M=K, the m-th display sub-area includes: (m-1)*X/K+1-th row of sub-pixels to m*X/K-th row of sub-pixels, 1≤m≤M , X is the total number of rows of sub-pixels included in the display area.

In an exemplary embodiment, N=M, the second initial signal line of the nth display sub-area is electrically connected to the nth power supply line, 1≤n≤N;

The voltage values of the signals from the first power supply line to the Nth power supply line are the same.

In an exemplary embodiment, when M=2K-1, a blanking area is included between two adjacent display frames; the a-th sub-pixel group includes: (X*a/K)-Y+1th row of sub-pixels To (X*a/K)+Y rows of sub-pixels, X is the total number of rows of sub-pixels included in the display area, and Y is the ratio of the time length in the blanking area to the time length displayed by a row of sub-pixels;

The first sub-pixel group to the K-1th sub-pixel group are respectively located in different display sub-regions.

In an exemplary embodiment, when M=2K-1, the 2ath display sub-area includes: the a-th sub-pixel group, and the first display sub-area includes: the first row of sub-pixels to (X/K)-Y+th 1 row of sub-pixels, the 2K-1th display sub-area includes: (X*(K-1)/K)+Y+1th row of sub-pixels The X-th row of sub-pixels, the b-th display sub-area includes: (X* (b-1)/2*K)+Y+1 row of sub-pixels to (X*(b+1)/2*K)-Y row of sub-pixels.

In an exemplary embodiment, when M=2K-1, the second initial signal line of the odd-numbered display sub-area is electrically connected to the first power supply line, and the second initial signal line of the even-numbered display sub-area is electrically connected to the second Electrical connection of power supply lines;

The voltage value of the signal of the first power supply line is smaller than the voltage value of the signal of the second power supply line.

In an exemplary embodiment, the number of any one of the first power supply line to the Nth power supply line is two, and are respectively located on opposite sides of the display area.

In an exemplary embodiment, the display area is further provided with a plurality of first initial connection lines, a plurality of second initial connection lines and a plurality of third initial connection lines; the first initial connection lines, the second Any one of the initial connecting line and the third initial connecting line extends at least partially along the second direction;

The first initial connection lines located in different display sub-areas are arranged at intervals, the second initial connection lines located in different display sub-areas are arranged at intervals, and the third initial connection lines located in different display sub-areas are arranged at intervals. The first initial connection lines and the first initial signal lines in the display sub-area have a network structure and are electrically connected to each other, and the second initial connection lines and the second initial signal lines located in the same display sub-area have a network structure and are electrically connected to each other. connection, the third initial connection line and the third initial signal line located in the same display sub-area have a network structure and are electrically connected to each other;

The non-display area is further provided with: a first initial power supply line and a third initial power supply line extending at least partially along the second direction, the first initial power supply line and the first initial signal line located in all sub-display areas Connecting, the third initial power supply line is connected to the third initial signal line located in all sub-display areas;

The number of the first initial power supply lines is two, and they are respectively located on opposite sides of the display area, and the number of the third initial power supply lines is two, and they are respectively located on opposite sides of the display area. on both sides of the display area; the first power supply line to the Nth power supply line, the first initial power supply line and the third initial power supply line located on the same side of the display area are arranged along the first direction.

In an exemplary embodiment, it includes: a substrate and a driving structure layer disposed on the substrate, and the driving structure layer includes: a pixel driving circuit, a first initial signal line, a second initial signal line, and a third initial signal line , the first power supply line to the Nth power supply line, the first initial power supply line and the third initial power supply line;

Any power supply line from the first power supply line to the Nth power supply line is arranged on the same layer as the first initial power supply line and the third initial power supply line, and is located on the first initial signal line and the second initial signal line and any one of the third initial signal lines is far away from the side of the substrate.

In an exemplary embodiment, the non-display area includes: a binding area located on one side of the display area and a frame area located on the other side of the display area, and the non-display area is also provided with at least one second signal Wire;

The second signal line is respectively electrically connected to the two first initial power supply lines located on both sides of the display area and the first initial connection line located on the display area, or to the two third initial power supply lines located on both sides of the display area electrically connected with the third initial connection line located in the display area;

Any one of the first power supply line to the Nth power supply line, the first initial power supply line, and the third initial power supply line is located in the frame area and the binding area, and the first The two signal lines are located in the binding area.

In an exemplary embodiment, the non-display area further includes a test pin group arranged on a side of the binding area away from the display area;

The second signal line includes: a first connection section, a second connection section, a third connection section, a fourth connection section, a fifth connection section, a sixth connection section and a seventh connection section, the first connection section, Any one of the third connecting section and the seventh connecting section extends at least partially along the first direction, and the second connecting section, the fourth connecting section, the fifth connecting section and the Any one of the sixth connecting sections extends at least partially along the second direction;

In the state where the second signal line is electrically connected to the two first initial power supply lines located on both sides of the display area and the first initial connection line located in the display area, one end of the first connecting section is connected to the One end of a first initial power supply line is electrically connected, the other end of the first connecting section is electrically connected to the middle section of the second connecting section, one end of the second connecting section is electrically connected to one end of the third connecting section, and the other end of the third connecting section The other end is electrically connected to one end of the fifth connection section, one end of the fourth connection section is electrically connected to the middle of the third connection section, the other end of the fourth connection section is electrically connected to the first initial connection line, and the other end of the fifth connection section is electrically connected to the middle of the third connection section. One end is electrically connected to one end of the sixth connection section, the other end of the sixth connection section is electrically connected to the test pin group, one end of the seventh connection section is electrically connected to the middle of the fifth connection section, and the other end of the seventh connection section is electrically connected to the middle part of the fifth connection section. Another first initial power supply line is electrically connected;

In the state where the second signal line is electrically connected to the two third initial power supply lines located on both sides of the display area and the third initial connection line located in the display area, one end of the first connection section is connected to the One end of a third initial power supply line is electrically connected, the other end of the first connecting section is electrically connected to the middle section of the second connecting section, one end of the second connecting section is electrically connected to one end of the third connecting section, and the other end of the third connecting section The other end is electrically connected to one end of the fifth connection section, one end of the fourth connection section is electrically connected to the middle of the third connection section, the other end of the fourth connection section is electrically connected to the third initial connection line, and the other end of the fifth connection section One end is electrically connected to one end of the sixth connection section, the other end of the sixth connection section is electrically connected to the test pin group, one end of the seventh connection section is electrically connected to the middle of the fifth connection section, and the other end of the seventh connection section is electrically connected to the middle part of the fifth connection section. Another third initial power supply line is electrically connected.

In an exemplary embodiment, the non-display area further includes: a first power line and a second power line, the first power line is electrically connected to the pixel driving circuit and configured to provide the pixel driving circuit with For a power signal, the second power line is electrically connected to the second electrode of the light emitting device and is configured to provide a power signal to the second electrode of the light emitting device; the binding area includes: The first fan-out area, the bending area, the second fan-out area, the first circuit area, the third fan-out area, the driver chip area and the binding pin area are arranged in sequence in the direction of the area; the first power line and The second power line is located in the binding area and the frame area;

The first connection section, the second connection section, the third connection section, the fifth connection section, the sixth connection section and the seventh connection section are all located in the second fan-out area On the side away from the display area, the first connection section and the seventh connection section are located on the side of the third connection section away from the display area, and are located in the first circuit area, thirty-three Any one of the third fan-out area and the drive chip area, any one of the second connection section and the fifth connection section is at least partially located in the first circuit area, the third sector area, the driver chip area, and the binding pin area, the sixth connection section is located in the binding pin area, and the fourth connection section is located in a part of the first circuit area close to the display area. side, and at least partially located in the first fan-out area, the bending area and the second fan-out area;

The orthographic projections of the first connection section and the seventh connection section on the base are at least partially overlapped with the orthographic projections of the first power line and the second power line on the base; the fourth connection The orthographic projection of the segment on the substrate at least partially overlaps the orthographic projection of the first power line on the substrate.

In an exemplary embodiment, the fourth connection section includes: a first subsection, a second subsection, and a third subsection are sequentially arranged along a direction close to the display area, and the third signal line located in the display area;

The first subsection is electrically connected to the third connection section and the second subsection, and the third subsection is electrically connected to the second subsection;

The first sub-section is at least partially located in the second fan-out area, and the orthographic projection on the base and the orthographic projection of the first power line on the base at least partially overlap, and the second sub-section is at least partially Located in the bending area, the third subsection is at least partially located in the first fan-out area.

In an exemplary embodiment, the first connection section and the seventh connection section are located on a side of the first power line or the second power line close to the base, and the second connection section, the first The third connection section, the fifth connection section and the sixth connection section are located on the side of the first connection section away from the base, the first subsection is located on the side of the third connection section close to the base, and the second subsection The segment is located on the side of the first sub-section away from the base, the third sub-section is located on the side of the second sub-section close to the base, and the sixth connecting segment is located on a side of the fifth connecting segment away from the base. side.

In an exemplary embodiment, the display area is further provided with signal connection lines, the signal connection lines are respectively electrically connected to the initial connection lines connected to the third subsection and the second signal line, and the signal connection lines are single The layer structure is located on the side of the second sub-section close to the base.

In an exemplary embodiment, an opening is provided on a side of the first power line located in the binding area close to the display area, and the second subsection extends to the opening of the first power line.

In a second aspect, the present disclosure further provides a display device, including: the above-mentioned display substrate.

Other aspects will be apparent to others upon reading and understanding the drawings and detailed description.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute limitations to the technical solutions of the present disclosure. The shape and size of one or more components in the drawings do not reflect true scale, but are for purposes of schematically illustrating the present disclosure.

1 is a schematic structural view of a display device;

2 is a schematic plan view of a display substrate;

3A is a schematic structural diagram of a pixel driving circuit;

FIG. 3B is a working process of the pixel driving circuit provided in FIG. 3A;

FIG. 4 is a timing diagram of signals within a display frame;

Fig. 5 is a schematic diagram of turning on the signal for realizing the effective reset of the anode;

FIG. 6 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

FIG. 7 is a first structural schematic diagram of a display substrate provided in an exemplary embodiment;

FIG. 8 is a second structural schematic diagram of a display substrate provided in an exemplary embodiment;

FIG. 9 is a schematic diagram of the load of any power supply line in the display frame provided in FIG. 7;

Fig. 10 is a schematic diagram of the load of any power supply line in the display substrate provided in Fig. 7 in the blanking area;

FIG. 11 is a schematic diagram of the connection between the first display sub-region and the first power supply line in the display substrate provided in FIG. 7;

FIG. 12 is a schematic diagram of the connection between the second display sub-region and the second power supply line in the display substrate provided in FIG. 7;

FIG. 13 is a schematic diagram of the connection between the third display sub-region and the third power supply line in the display substrate provided in FIG. 7;

FIG. 14 is a schematic diagram of the connection between the odd-numbered display sub-region and the first power supply line in the display substrate provided in FIG. 8;

FIG. 15 is a schematic diagram of the connection between the even-numbered display sub-region and the second power supply line in the display substrate provided in FIG. 8;

Fig. 16 is a schematic structural diagram of a display substrate provided in an exemplary embodiment;

Fig. 17 is a schematic structural diagram of a binding region provided in an exemplary embodiment;

Fig. 18 is an enlarged view of area A1 in Fig. 17;

Fig. 19 is an enlarged view of area A2 in Fig. 17;

Figure 20 is an enlarged view of area A3 in Figure 17;

Figure 21 is a partial schematic diagram of the binding region.

Detailed ways

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.

In the drawings, the size of one or more constituent elements, the thickness of layers, or regions are sometimes exaggerated for the sake of clarity. Therefore, one mode of the present disclosure is not necessarily limited to the dimensions, and the shape and size of one or more components in the drawings do not reflect the true scale. In addition, the drawings schematically show ideal examples, and one aspect of the present disclosure is not limited to shapes, numerical values, and the like shown in the drawings.

Ordinal numerals such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the number. "Plurality" in the present disclosure means two or more quantities.

In this specification, for convenience, "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner" are used , "external" and other words indicating the orientation or positional relationship are used to illustrate the positional relationship of the constituent elements with reference to the drawings, which are only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation , are constructed and operate in a particular orientation and therefore are not to be construed as limitations on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the described constituent elements. Therefore, it is not limited to the words and phrases described in the specification, and may be appropriately replaced according to circumstances.

In this specification, unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be interpreted in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or a connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements. Those of ordinary skill in the art can understand the meanings of the above terms in the present disclosure according to the situation.

In this specification, "electrically connected" includes the case where constituent elements are connected together through an element having some kind of electrical function. The "element having some kind of electrical function" is not particularly limited as long as it can transmit electrical signals between connected components. Examples of "elements having some kind of electrical function" include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

In this specification, a transistor refers to an element including at least three terminals of a gate, a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source . In this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first electrode may be the drain and the second electrode may be the source, or the first electrode may be the source and the second electrode may be the drain. In cases where transistors with opposite polarities are used, or when the direction of current changes during circuit operation, the functions of "source" and "drain" may be interchanged. Therefore, in this specification, "source" and "drain" can be interchanged with each other. In addition, the gate may also be referred to as a control electrode.

In the present specification, "parallel" refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°. In addition, "perpendicular" means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.

In this specification, circle, ellipse, triangle, rectangle, trapezoid, pentagon or hexagon, etc. are not strictly defined, and may be approximately circular, approximately elliptical, approximately triangular, approximately rectangular, approximately trapezoidal, Approximate pentagons or approximate hexagons, etc., may have some small deformations caused by tolerances, such as chamfers, arc edges, and deformations.

"About" and "approximately" in the present disclosure refer to the situation that the limit is not strictly limited, and the error range of process and measurement is allowed. In the present disclosure, "substantially the same" refers to the case where the numerical value differs within 10%.

In the present disclosure, A extending along the B direction means that A may include a main part and a secondary part connected with the main part, the main part is a line, a line segment or a bar-shaped body, the main part extends along the B direction, and the main body The portion extends along the B direction for a greater length than the secondary portion extends along the other directions. In the present disclosure, "A extends along the B direction" all means "the main part of A extends along the B direction".

FIG. 1 is a schematic structural diagram of a display device. In some examples, as shown in FIG. 1 , the display device may include: a timing controller 21 , a data driver 22 , a scanning driving circuit 23 , a light emitting driving circuit 24 and a sub-pixel array 25 . In some examples, the sub-pixel array 25 may include a plurality of sub-pixels PX arranged regularly. The scanning driving circuit 23 can be configured to provide the scanning signal to the sub-pixel PX along the scanning signal line; the data driver 22 can be configured to provide the data voltage to the sub-pixel PX along the data line; The light emission control signal is supplied to the sub-pixel PX; the timing controller 21 may be configured to control the scanning driving circuit 23 , the light emitting driving circuit 24 and the data driver 22 .

In some examples, as shown in FIG. 1 , the timing controller 21 can provide gray values and control signals suitable for the specification of the data driver 22 to the data driver 22; The scan clock signal, scan start signal, etc. are provided to the scan driving circuit 23; The data driver 22 may generate data voltages to be supplied to the data lines D1 to Di using the grayscale values and control signals received from the timing controller 21 . For example, the data driver 22 may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data lines D1 to Di in units of sub-pixel rows. The scan driving circuit 23 may generate scan signals to be supplied to the scan lines S1 to Sj by a scan clock signal, a scan start signal, etc. received from the timing controller 21 . For example, the scan driving circuit 23 may sequentially supply scan signals having on-level pulses to the scan lines. In some examples, the scan driver 23 may include a shift register, and may generate scan signals in a manner of sequentially transmitting a scan start signal provided in the form of a conduction level pulse to a next-stage circuit under the control of a scan clock signal. The light emission driving circuit 24 may generate a light emission control signal to be supplied to the light emission control lines E1 to Eo by a light emission clock signal, a light emission start signal, etc. received from the timing controller 21 . For example, the light emission drive circuit 24 may sequentially supply light emission control signals having off-level pulses to the light emission control lines. The light-emitting driving circuit 24 may include a shift register to generate a light-emitting control signal in a manner of sequentially transmitting a light-emitting start signal provided in the form of an off-level pulse to a next-stage circuit under the control of a clock signal. Among them, i, j and o are all natural numbers.

In some examples, a display device may include a display substrate. The sub-pixel array, scanning driving circuit and light emitting driving circuit can be directly arranged on the display substrate. For example, the scanning driving circuit can be arranged on the left frame of the display substrate, and the light emitting driving circuit can be arranged on the right frame of the display substrate; or, the scanning driving circuit and the light emitting driving circuit can be arranged on both the left frame and the right frame of the display substrate. In some examples, the scan driving circuit and the light emitting driving circuit may be formed together with the sub-pixel in a process of forming the sub-pixel.

In some examples, the data driver may be provided on a separate chip or printed circuit board. For example, the data driver may adopt chip-on-glass, chip-on-plastic, chip-on-film, etc. to be disposed on the lower frame of the display substrate so as to be connected to pins of the driver chip. The timing controller may be provided separately from the data driver or integrally provided with the data driver. However, this embodiment does not limit it.

FIG. 2 is a schematic plan view of a display substrate. In some examples, as shown in FIG. 2 , the display substrate may include: a display area AA, a binding area B1 located on one side of the display area AA, and a frame area B2 located on the other side of the display area AA. The binding area B1 may be, for example, the lower border of the display substrate, and the border area B2 may include the upper border, left border and right border of the display substrate. In some examples, the display area AA may be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX are configured to display dynamic pictures or still images. The display area may be referred to as an active area. In some examples, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curled, bent, folded or rolled.

In some examples, the bezel area B2 may include a circuit area, a power line area, a crack dam area and a cutting area sequentially arranged along the direction of the display area AA. The circuit area may be connected to the display area AA, and may at least include a plurality of cascaded gate driving circuits, and the gate driving circuits are electrically connected to a plurality of gate lines in the display area AA. The power line area is connected to the circuit area, and may at least include low-level power lines. The low-level power lines may extend along a direction parallel to the edge of the display area, and be connected to the cathode of the display area. The crack dam region may be connected to the power line region and may include at least a plurality of cracks disposed in the composite insulation layer. The cutting area may be connected to the crack dam area, and may at least include cutting grooves provided on the composite insulating layer, and the cutting grooves may be configured such that after all the film layers of the display substrate are prepared, the cutting devices may respectively cut along the cutting grooves.

In some examples, the binding area B1 and the frame area B2 can be provided with a first isolation dam and a second isolation dam, and the first isolation dam and the second isolation dam can extend along a direction parallel to the edge of the display area to form a surrounding display area In the ring structure of AA, the edge of the display area is the edge of the display area on the side close to the binding area B1 or the frame area B2.

In some examples, as shown in FIG. 2 , the display area AA may at least include a plurality of sub-pixels PX, a plurality of gate lines Gate, and a plurality of data lines Data. A plurality of gate lines Gate may extend along the first direction X, and a plurality of data lines Data may extend along the second direction Y. Orthographic projections of multiple gate lines Gate and multiple data lines Data on the base substrate intersect to form multiple sub-pixel regions, and a sub-pixel PX is arranged in each sub-pixel region. The multiple data lines Data are electrically connected to the multiple sub-pixels PX, and the multiple data lines Data may be configured to provide data signals to the multiple sub-pixels PX. A plurality of data lines Data can extend to the bonding area B1. The multiple gate lines Gate are electrically connected to the multiple sub-pixels PX, and the multiple gate lines Gate may be configured to provide gate control signals to the multiple sub-pixels PX. In some examples, the gate control signal may include a scan signal and a light emission control signal.

In some examples, as shown in FIG. 2, the first direction X may be the extending direction (row direction) of the gate lines Gate in the display area AA, and the second direction Y may be the extending direction (column direction) of the data lines Data in the display area AA. direction). The first direction X and the second direction Y may intersect, for example, the first direction X and the second direction Y may be perpendicular to each other.

In some examples, one pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels are red sub-pixels, green sub-pixels and blue sub-pixels respectively. However, this embodiment does not limit it. In some examples, one pixel unit may include four sub-pixels, and the four sub-pixels are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel.

In some examples, the shape of a sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically or squarely; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically or squarely . However, this embodiment does not limit it.

In some examples, a sub-pixel may include: a pixel driving circuit and a light emitting element electrically connected to the pixel driving circuit. The pixel driving circuit may include a plurality of transistors and at least one capacitor. For example, the pixel driving circuit may have a 3T1C (ie, 3 transistors and 1 capacitor) structure, a 7T1C (ie, 7 transistors and 1 capacitor) structure, a 5T1C (ie, 5 1 transistor and 1 capacitor) structure, 8T1C (ie 8 transistors and 1 capacitor) structure or 8T2C (ie 8 transistors and 2 capacitors) structure, etc.

In some examples, the light-emitting element can be a light-emitting diode (LED, Light Emitting Diode), an organic light-emitting diode (OLED, Organic Light Emitting Diode), a quantum dot light-emitting diode (QLED, QuantumDot Light Emitting Diodes), a micro LED (including: mini -LED or micro-LED) and the like. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light under the drive of its corresponding pixel driving circuit. The color of light emitted by the light emitting element can be determined according to needs. In some examples, the light emitting element may include: a first electrode, a second electrode, and an organic light emitting layer between the first electrode and the second electrode. The first electrode of the light emitting element may be electrically connected to a corresponding pixel driving circuit. However, this embodiment does not limit it.

FIG. 3A is a schematic structural diagram of a pixel driving circuit. Figure 3A uses 8T1C as an example for illustration. As shown in Figure 3A, the pixel driving circuit can be connected with 11 signal lines (data line Data, first scanning line Gate1, second scanning line Gate2, first reset line Reset1, second reset line Reset2, light emitting line E, first The initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the first power line VDD and the second power line VSS) are connected. Wherein, the gate lines include: a first scan line Gate1 , a second scan line Gate2 , a first reset line Reset1 , a second reset line Reset2 , and an emission line E.

In an exemplary embodiment, as shown in FIG. 3A , the control electrode of the first transistor M1 is connected to the first reset line Reset1, the first electrode of the first transistor M1 is connected to the first initial signal line INIT1, and the first electrode of the first transistor M1 is connected to the first initial signal line INIT1. The two poles are connected to the third node N3. The control electrode of the second transistor M2 is connected to the second scanning line Gate2, the first electrode of the second transistor M2 is connected to the first node N1, and the second electrode of the second transistor M2 is connected to the third node N3. The control electrode of the third transistor M3 is connected to the first node N1, the first electrode of the third transistor M3 is connected to the second node N2, and the second electrode of the third transistor M3 is connected to the third node N3. The control electrode of the fourth transistor M4 is connected to the first scanning line Gate1, the first electrode of the fourth transistor M4 is connected to the data line Data, and the second electrode of the fourth transistor M4 is connected to the second node N2. The control electrode of the fifth transistor M5 is connected to the light emitting line E, the first electrode of the fifth transistor M5 is connected to the first power line VDD, and the second electrode of the fifth transistor M5 is connected to the second node N2. The control electrode of the sixth transistor M6 is connected to the light emitting line E, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the fourth node N4. The control electrode of the seventh transistor M7 is connected to the second reset line Reset2, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is connected to the fourth node N4. The control electrode of the eighth transistor M8 is connected to the second reset line Reset2, the first electrode of the eighth transistor M8 is connected to the third initial signal line INIT3, the second electrode of the eighth transistor M8 is connected to the second node N2, and the capacitor C The first terminal is connected to the first power line VDD, and the second terminal of the capacitor C is connected to the first node N1.

In an exemplary embodiment, the first electrode of the light emitting device is electrically connected to the fourth node N4, the second electrode of the light emitting device is connected to the second power line VSS,

In an exemplary embodiment, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal.

According to the characteristics of transistors, transistors can be divided into N-type transistors and P-type transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage ). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage ).

In example embodiments, the first to eighth transistors M1 to M8 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product. In some possible implementation manners, the first transistor M1 to the eighth transistor M8 may include P-type transistors and N-type transistors.

In an exemplary embodiment, the first transistor M1 to the eighth transistor M8 may use a low temperature polysilicon thin film transistor, or may use an oxide thin film transistor, or may use a low temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. The low temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate to form a low temperature polycrystalline oxide (LowTemperature Polycrystalline Oxide (LTPO for short) display substrate can take advantage of the advantages of the two, realize low-frequency drive, reduce power consumption, and improve display quality.

In an exemplary embodiment, as shown in FIG. 3A , the second transistor M2 may be an N-type transistor, and the first transistor M1 , the third transistor M3 to the eighth transistor M8 may be P-type transistors.

FIG. 3B is a working process of the pixel driving circuit provided in FIG. 3A . In an exemplary embodiment, the working process of the pixel driving circuit may include:

The first stage P1 is called the first reset stage, the signal of the second reset line Reset2 is a low level signal, and the signals of the first reset line Reset1, the first scanning line Gate1, the second scanning line Gate2 and the light emitting line E are high level signal. The signal of the second reset line Reset2 is a low-level signal, so that the seventh transistor M7 and the eighth transistor M8 are turned on, and the signal of the second initial signal line INIT2 is supplied to the fourth node N4, and the first electrode of the light emitting device L is activated. Initialization (resetting), clearing the original charge in the first electrode of the light emitting device L. The signal of the third initial signal line INIT3 is provided to the second node N2 to initialize (reset) the second node N2 and clear the original charges in the second node N2. At this stage, the third transistor M3 is turned on. The signal of the second scan line Gate2 is a high level signal, and the second transistor M2 is turned on. The signal of the second node N2 is provided to the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized, the signals of the first reset line Reset1, the first scan line Gate1 and the light emitting line E are as follows: High level signal, the first transistor M1, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off. At this stage, the light emitting device L does not emit light.

The second stage P2 is called the second reset stage, the signal of the first reset line Reset1 is a low level signal, and the signals of the second reset line Reset2, the first scanning line Gate1, the second scanning line Gate2 and the light emitting line E are high level signal. The signal of the first reset line Reset1 is a low-level signal, so that the first transistor M1 and the signal of the first initial signal line INIT1 are provided to the third node N3, and the third node N3 is initialized (reset) again, and the third node is cleared. The original charge in N3. At this stage, the third transistor M3 is continuously turned on. The signal of the second scan line Gate2 is a high level signal, and the second transistor M2 is turned on. The third node N3 is provided to the first node N1 to continuously initialize the first node N1, the signals of the second reset line Reset2, the first scanning line Gate1 and the light emitting line E are high level signals, the fourth transistor M4, the first The fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are turned off. At this stage, the light emitting device L does not emit light.

The third stage P3 is called the data writing stage or the threshold compensation stage, the signal of the first scanning line Gate1 is a low level signal, the first reset line Reset1, the second reset line Reset2, the second scanning line Gate2 and the light emitting line E The signal is a high level signal. The data line Data outputs a data voltage. At this stage, the third transistor M3 is continuously turned on. The signal of the first scan line Gate1 is a low level signal to turn on the fourth transistor M4. The signal of the second scan line Gate2 is a high level signal, and the second transistor M2 is turned on. The data voltage output by the data line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, and the The difference between the data voltage output by the data line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C, and the voltage at the second terminal (first node N1) of the capacitor C is Vd-|Vth|, and Vd is the voltage output by the data line Data The data voltage, Vth is the threshold voltage of the third transistor M3. The signals of the first reset line Reset1 , the second reset line Reset2 and the light emitting line E are high level signals, and the first transistor M1 , the fifth transistor M5 , the sixth transistor M6 , the seventh transistor M7 and the eighth transistor M8 are turned off. At this stage, the light emitting device L does not emit light.

In the fourth stage P4, called the continuous compensation stage, the signals of the first reset line Reset1, the second reset line Reset2, the first scanning line Gate1, the second scanning line Gate2 and the light emitting line E are high-level signals. The signal of the second scanning line Gate2 is a high level signal, the second transistor M2 is continuously turned on, the signals of the first scanning line Gate1, the first reset line Reset1, the second reset line Reset2 and the light emitting line E are high level signals, The first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are turned off. Although the signal of the data line Data stops writing, the second node N2 is still provided to the first node N1 through the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, and the third transistor M3 The threshold voltage is continuously compensated.

The fifth stage P5 is called the bias stage, the signals of the second scanning line Gate2 and the second reset line Reset2 are low-level signals, and the signals of the first reset line Reset1, the first scanning line Gate1 and the light-emitting line E are high-level signals flat signal. The signal of the second scanning line Gate2 is a low-level signal, the signals of the first scanning line Gate1, the first reset line Reset1 and the light-emitting line E are high-level signals, the first transistor M1, the second transistor M2, and the fourth transistor M4 , the fifth transistor M5 and the sixth transistor M6 are all turned off. The signal of the second reset line Reset2 is a low level signal, the seventh transistor M7 and the eighth transistor M8 are turned on, the signal of the third initial signal line INIT3 is written into the second node N2 and the third node N3, the second initial signal line The signal of INIT2 is written into the fourth node N3, at this stage, the third transistor M3 is in a biased state, and the light emitting device L does not emit light.

The sixth stage P6 is called the light-emitting stage. The signals of the light-emitting line E and the second scanning line Gate2 are low-level signals, and the signals of the first reset line Reset1, the second reset line Reset2, and the first scanning line Gate1 are high-level signals Signal. The signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor M5 and the sixth transistor M6 are turned on, and the power supply voltage output by the first power line VDD passes through the turned-on fifth transistor M5, third transistor M3 and sixth transistor M5. The transistor M6 provides a driving voltage to the first electrode of the light emitting device L to drive the light emitting device L to emit light.

During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor M3 is:

I=K*(Vgs-Vth) ² ＝K*[(Vdd-Vd+|Vth|)-Vth] ² ＝K*[(Vdd-Vd] ²

Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current for driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, and Vth is the first electrode of the third transistor M3. The threshold voltage of the three transistors M3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the first power line VDD.

From the derivation result of the above current formula, it can be seen that in the light emitting stage, the driving current of the third transistor M3 is no longer affected by the threshold voltage of the third transistor M3, thereby eliminating the influence of the threshold voltage of the third transistor M3 on the driving current , can ensure that the display brightness of the display product is uniform, and improve the display effect of the entire display product.

With the maturity of display technology, more and more display products use LTPO display substrates, especially gaming display products. The market has more and more urgent requirements for high refresh rate and frequency conversion of display products.

FIG. 4 is a timing diagram of signals within a display frame. As shown in Figure 4, a display frame includes: multiple frequency conversion units, and the pixel drive circuit in each frequency conversion unit drives the light-emitting device to emit light once. Display products can be realized by increasing the number of frequency conversion units contained in each display frame. Display the switching of different frequencies of the product. FIG. 4 is illustrated by taking three frequency conversion units included in one display frame as an example. As shown in Figure 4, the light-emitting duty cycle and the effective reset times of the anode in each frequency conversion unit are the same, wherein the effective reset times of the anode refers to changing the signal of the first electrode of the light-emitting device from the first signal to the second The number of signals on the initial signal line, although in Figure 4 the second reset signal line Reset2 is an active level signal twice in a frequency conversion unit, that is, the second initial signal line INIT2 resets the first electrode of the light emitting device twice , however, when the second initial signal line INIT2 resets the first electrode of the light-emitting device for the first time, the signal of the first electrode of the light-emitting device changes from the first signal to the signal of the second initial signal line, which can be called the primary anode Effective reset, and when the second initial signal line INIT2 resets the first electrode of the light-emitting device for the second time, the signal of the first electrode of the light-emitting device does not change, and the signal of the second initial signal line is still maintained, which is not possible this time. It is called anode effective reset, therefore, in each frequency conversion unit, only the anode effective reset times is once.

In an exemplary embodiment, taking the anode effective reset frequency as 360Hz as an example, when each display frame includes three frequency conversion units, the refresh frequency of the display frame can satisfy 120Hz; when each display frame includes four frequency conversion units , the refresh rate of the display frame can meet 90Hz. Therefore, refresh rates that are divisible by 360 (for example, 120Hz/90Hz/72Hz/60HZ/45HZ/40HZ/36Hz/30Hz/20Hz/10Hz/1Hz) can be switched. Similarly, when the effective reset frequency of the anode is 240Hz, the refresh frequency that can be divisible by 240 can be switched. This disclosure does not make any limitation on this.

Fig. 5 is a schematic diagram of turning on the signal for realizing the effective reset of the anode. FIG. 5 is illustrated by taking the first display frame to the third display frame as an example, and each display frame includes three frequency conversion units. The abscissa in FIG. 5 is the scan time, wherein ti refers to the moment when the second reset signal line is an active level signal. The number of second reset signal lines on the ordinate in FIG. 5 is illustrated by taking 18 second reset signal lines G1 to G18 as an example. 1, 2, and 3 in the table in Fig. 5 respectively represent the first frequency conversion unit, the second frequency conversion unit, and the third frequency conversion unit in a display frame when the second reset signal line Reset2 is an active level signal for the first time Signal pulses, hereinafter referred to as 1 is the first pulse signal, 2 is the second pulse signal, and 3 is the third pulse signal. As shown in Figure 5, a blanking area is included between two adjacent display frames. Figure 5 shows that the duration of the blanking area is 2t. The first blanking area includes t19 and t20, and the second blanking area includes: t39 and t40 are described as examples.

In an exemplary embodiment, the blanking zone refers to a period of virtual time, which is used to adapt to display driving timing and signal transmission, and the blanking zone is also referred to as a "cycloidal period" or a "synchronous pulse period". .

As shown in Figure 5, from a horizontal perspective, the signals of the first second reset signal line G1 at t1, t21, and t41 are the first pulse signals, and the signals at t7, t27, and t47 are the second pulse signals. The signals of t13, t33, and t53 are the third pulse signal, and the other second reset signal lines are analogized in sequence.

As shown in Figure 5, from a vertical perspective, taking t13 as an example, at t13, the signal of the first second reset signal line is the third pulse signal, and the signal of the seventh second reset signal line is the second pulse signal , the signal of the thirteenth reset signal line is the first pulse signal, that is, at t13, the first second reset signal line, the seventh second reset signal line and the thirteenth reset signal line are simultaneously turned on. When the second reset signal line is turned on, the second initial signal line provides an initial signal to the fourth node, that is, at t13, the first second reset signal line, the seventh second reset signal line and the thirteenth node The second initial signal line in the sub-pixel connected to the first reset signal line provides an initial signal to the fourth node to effectively reset the fourth node. The rest of the time and so on.

As shown in Figure 5, when the first scan of the first pulse signal is completed, the display substrate enters the first blanking area (t19 and t20), at t19, the seventh second reset signal line G7 and the thirteenth reset signal line The second reset signal line G13 is turned on at the same time, and at t20, the eighth second reset signal line G8 and the fourteenth second reset signal line G14 are turned on at the same time. After the first scan of the second pulse signal is completed, at t25, the fifth second reset signal line G5 and the thirteenth second reset signal line G13 are simultaneously turned on, and at t26, the sixth second reset signal line G6 and the fourteenth second reset signal line G14 are turned on at the same time. After the first scan of the third pulse signal is completed, at t31, the fifth second reset signal line G5 and the eleventh second reset signal line G11 is turned on at the same time, at t32, the sixth second reset signal line G6 and the twelfth second reset signal line G12 are turned on at the same time, and so on, when the second scan of the first pulse signal is completed, the display substrate enters In the second blanking period (t39 and t40), at t39, the seventh second reset signal line G7 and the thirteenth second reset signal line G13 are simultaneously turned on, and at t40, the eighth second reset signal line G8 and the fourteenth second reset signal line G14 are turned on at the same time. After the second scan of the second pulse signal is completed, at t45, the fifth second reset signal line G5 and the thirteenth second reset signal line G13 are simultaneously turned on, and at t46, the sixth second reset signal line G6 and the fourteenth second reset signal line G14 are turned on at the same time. After the second scan of the third pulse signal is completed, at t51, the fifth second reset signal line G5 and the eleventh second reset signal line G11 is turned on at the same time, and at t52, the sixth second reset signal line G6 and the twelfth second reset signal line G12 are turned on at the same time.

As shown in FIG. 5 , the three second reset signal lines on the display substrate are turned on at the same time at other times of the display frame except for the first display frame and the above several times. The timing sequence of the signal in Figure 4 will cause the difference in the number of rows of the second reset signal lines that are simultaneously turned on in the blanking area and the display frame, that is, the number of rows of the second reset signal lines that are turned on at the same time in the display frame is three rows. The number of rows of the second reset signal lines that are turned on at the same time in the blanking area is two rows.

As shown in Figure 5, when the three second reset signal lines are turned on at the same time, the numbers K1, K2 and K3 of the three second reset signals that are turned on are respectively satisfied, 1≤K1≤6, 7≤K2≤12, 13≤ K3≤18. If the display area of the display substrate is evenly divided into three areas along the column direction, they respectively include the first display sub-area to the third display sub-area. Wherein, the first display sub-area includes the first row of sub-pixels to the sixth row of sub-pixels, the second display sub-area includes the seventh row of sub-pixels to the twelfth row of sub-pixels, and the third display sub-area includes: the thirteenth row of sub-pixels The sub-pixels to the eighteenth row of sub-pixels, that is to say, the three second reset signal lines that are turned on are respectively located in the first display sub-region, the second display sub-region and the third display sub-region, that is to say, the anode The three second initial signal lines for effective reset are respectively located in the first display sub-area, the second display sub-area and the third display sub-area.

As shown in Figure 5, when the two second reset signal lines are turned on at the same time, the two second reset signal lines that are turned on are respectively located in the first display sub-area and the second display sub-area, or are respectively located in the second display sub-area and the third display sub-area, that is to say, the two second initial signal lines that simultaneously perform anode effective reset are respectively located in the first display sub-area and the second display sub-area, or respectively located in the second display sub-area and the third display sub-area sub-areas, or respectively located in the first display sub-area and the third display sub-area.

A display substrate is further provided with a second initial power supply line, the second initial power supply line is electrically connected to all second initial signal lines located in the display area, and is configured to provide initial signals for the second initial signal lines. According to Fig. 4 and Fig. 5, it can be seen that the number of rows of the second reset signal lines that the display substrate conducts at the same time during part of the display frame is three rows, which means that the load of the second initial power supply line is the fourth of the three rows of sub-pixels. The sum of the capacitances of the nodes, the number of rows of the second reset signal lines that are simultaneously turned on in the blanking area is two rows, which means that the load of the second initial power supply line is the sum of the capacitances of the fourth nodes of the two rows of sub-pixels. Because in the display frame and the blanking area, the load of the second initial power supply line is different, the potential of the fourth node of the sub-pixel displayed in the display frame is higher than that of the fourth node of the sub-pixel displayed in the blanking area, so that the blanking area The lighting speed of the light-emitting device of the displayed sub-pixel is relatively slow, and the display effect is relatively dark. According to the analysis of FIG. 5, it can be seen that the number of rows of the second reset signal lines that are turned on at the same time is two rows, and the sub-pixels displayed are roughly located at one-third and two-thirds of the display substrate, that is, the display substrate. One-third and two-thirds are darker than other parts of the display substrate, and the rest of the region is brighter, thereby forming a display split screen, resulting in a poor display effect of the display substrate. The analysis in Fig. 4 and Fig. 5 is illustrated by taking a display frame including three frequency conversion units, and the display screen effect is a three-split screen. When a display frame includes four frequency conversion units, it is a quarter of the display substrate. 1. Two-quarters and three-quarters are darker, and the display effect is a quarter-screen.

FIG. 6 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure. As shown in FIG. 6, the display substrate provided by the embodiment of the present disclosure has a display area AA and a non-display area. The display area AA is provided with sub-pixels PX arranged in an array and a plurality of first signal lines S1. The sub-pixels include: pixel drive Circuits and light-emitting devices, the non-display area is provided with the first power supply line SL-1 to the Nth power supply line SL-N, the first signal line at least partially extends along the first direction X, and the first power supply line SL-1 to the Nth power supply line SL-1 Any power supply line in the lines SL-N at least partially extends along the second direction Y, and the first direction X and the second direction Y intersect. Wherein, the first signal line is electrically connected to the pixel driving circuit or the light emitting device, and is configured to provide an initial signal to the pixel driving circuit or the light emitting device.

As shown in Figure 6, the display area AA is divided into M display sub-areas R1 to RM arranged along the second direction, the first signal lines in the same display sub-area are connected to the same power supply line, at least two display sub-areas The first signal line in is connected to different power supply lines, M, N≥2.

In an exemplary embodiment, the pixel driving circuit may be the pixel driving circuit provided in FIG. 3A .

In an exemplary embodiment, as shown in FIG. 6 , the non-display area includes: a binding area B1 located on one side of the display area and a frame area B2 located on the other side of the display area AA,

The display substrate provided by the embodiment of the present disclosure has a display area and a non-display area, the display area is provided with sub-pixels arranged in an array and a plurality of first signal lines, and the non-display area is provided with a first power supply line to an Nth power supply line, The first signal line at least partially extends along the first direction, any one of the first power supply line to the Nth power supply line extends at least partly along the second direction, the first signal line is electrically connected to the sub-pixel, and is configured to feed the sub-pixel Pixels provide initial signals; the display area is divided into M display sub-areas arranged along the second direction, the first signal lines in the same display sub-area are connected to the same power supply line, and the first signal lines in at least two display sub-areas Lines are connected to different power supply lines, M, N≥2. In the present disclosure, by setting the first power supply line to the Nth power supply line, the first signal line in the same display sub-area is connected to the same power supply line, and at least two display sub-areas The first signal line is connected to different power supply lines, which can reduce the load difference between any power supply line in the display frame and the blanking area, and can improve the display effect of the display substrate.

In an exemplary embodiment, the display area is provided with a plurality of first initial signal lines and a plurality of second initial signal lines extending along a first direction, the sub-pixel includes: a pixel driving circuit and a light emitting device, and the pixel driving circuit includes: a driving The transistor, the light emitting device includes: a first electrode, the first initial signal line is configured to drive one of the source and drain electrodes of the transistor to provide an initial signal, and the second initial signal line is configured to provide an initial signal to the first electrode of the light emitting device Signal. The first signal line includes any one of a first initial signal line and a second initial signal line.

In an exemplary embodiment, the display area is provided with a plurality of first initial signal lines, a plurality of second initial signal lines, and a plurality of third initial signal lines extending along a first direction, and the pixel driving circuit includes: a driving transistor, a light emitting The device includes: a first electrode, the first initial signal line is configured to provide an initial signal to one of the source and drain electrodes of the drive transistor, the second initial signal line is configured to provide an initial signal to the first electrode of the light emitting device, the first The three initial signal lines are configured to supply an initial signal to the other of the source-drain electrodes of the driving transistor. The first signal line includes any one of a first initial signal line, a second initial signal line, and a third initial signal line.

FIG. 7 is a first structural schematic diagram of a display substrate provided in an exemplary embodiment, and FIG. 8 is a second structural schematic diagram of a display substrate provided in an exemplary embodiment. FIG. 7 and FIG. 8 are illustrated by taking the first signal line as the second initial signal line INIT2 as an example.

In an exemplary embodiment, as shown in FIG. 7 and FIG. 8 , M=K or 2K-1, K is the number of times the second initial signal line effectively initializes the first electrode of the light-emitting device within the target duration, and the effective initialization refers to The second initial signal line adjusts the first electrode of the light-emitting device from the first signal to the second signal, the voltage value of the first signal is different from the voltage value of the second signal, and the second signal is transmitted by the second initial signal line Signal, the target duration is equal to the duration of one display frame. FIG. 7 takes M=K=3 as an example, and FIG. 8 takes K=3 and M=2K-1=5 as an example for illustration.

In an exemplary embodiment, as shown in FIG. 7 , when M=K, the m-th display sub-area includes: (m-1)*X/K+1-th row of sub-pixels to m*X/K-th row of sub-pixels , 1≤m≤M, X is the total number of rows of sub-pixels included in the display area, that is, the display area is evenly divided. Exemplarily, taking X=18 and K=3 as an example, the display area includes three display sub-areas, the first display sub-area includes the first row of sub-pixels to the sixth row of sub-pixels, and the second display sub-area includes: There are seven rows of sub-pixels to the twelfth row of sub-pixels, and the third display sub-region includes the thirteenth row of sub-pixels to the eighteenth row of sub-pixels.

In an exemplary embodiment, as shown in FIG. 7, when M=K, N=M, the second initial signal line of the nth display sub-area is electrically connected to the nth power supply line, 1≤n≤N; the first The voltage values of the signals from the power supply line to the Nth power supply line are the same. Exemplarily, the second initial signal line INIT2 of the first display sub-region R1 is electrically connected to the first power supply line SL-1, and the second initial signal line INIT2 of the second display sub-region R2 is electrically connected to the second power supply line SL-2. The second initial signal line INIT2 of the third display sub-region R3 is electrically connected to the third power supply line SL-3.

According to the analysis of Figure 4 and Figure 5, it can be seen that at any time, the multiple second reset signal lines that are turned on at the same time are located in different display sub-areas, that is, the multiple second initial signal lines that are simultaneously performing active anode reset are located in different display sub-areas. sub-area. Figure 7 connects different power supply lines by setting the second initial signal lines of different display sub-areas, so that at any time, multiple second initial signal lines that are turned on at the same time are respectively connected to different power supply lines, that is, any power supply line is in any The load at all times is a second initial signal line.

In an exemplary embodiment, FIG. 9 is a schematic diagram of a load of any power supply line in a display frame provided in FIG. 7 , and FIG. 10 is a schematic diagram of a load of any power supply line in a blanking area of the display substrate provided in FIG. 7 . As shown in Figure 9 and Figure 10, the load of the second power supply line SL-2 and the third power supply line SL-3 in the display substrate shown in Figure 7 is a second The initial signal line INIT2, the load of the first power supply line SL-1 at any moment in the display frame is a second initial signal line INIT2, and there is no load at any moment in the blanking area, that is to say, in the blanking area There is no second initial signal line in a display sub-area to reset the first electrode of the light-emitting device in the sub-pixel, so the difference between the first power supply line SL-1 in the display frame and the blanking area will not affect the display As a result, the display substrate provided in Figure 7 can make the signals of the fourth node of any sub-pixel located in all sub-pixel rows approximately the same, and the reset degree of the first electrode of any light-emitting device is consistent, thereby eliminating the dark band at the split screen , Eliminate bad screen splitting, and improve the display effect of the display substrate.

In an exemplary embodiment, the second initial signal lines located in different display sub-regions are independent of each other and do not affect each other. The first power supply line to the Nth power supply line can be combined into one bus in the bonding area of the display substrate, which can save the number of chip pins, or can be three independent signal lines.

In an exemplary embodiment, as shown in FIG. 8 , a blanking area is included between two adjacent display frames. The first sub-pixel group to the K-1th sub-pixel group are respectively located in different display sub-regions. The a-th sub-pixel group includes: (X*a/K)-Y+1 row of sub-pixels to (X*a/K)+Y row of sub-pixels, X is the total number of rows of sub-pixels included in the display area, and Y is The ratio of the duration in the blanking area to the duration displayed by a row of sub-pixels. Exemplarily, taking X=18, Y=2, K=3 as an example for illustration, the first sub-pixel group includes: the fifth row to the eighth row of sub-pixels, and the second sub-pixel group includes: the eleventh row From the sub-pixels to the fourteenth row of sub-pixels, the first sub-pixel group is approximately located at one-third of the display substrate, and the second sub-pixel group is approximately located at two-thirds of the display substrate. The sub-pixels included in the first sub-pixel group to the K-1th sub-pixel group are the second reset signal lines that are turned on at the same time as shown in Figure 4 and Figure 5. The number of rows of the second reset signal line is two rows, and the signal is an active level at all times. The combination of sub-pixels connected to the second reset signal line (G5 to G8, G11 to G14) of the signal.

In an exemplary embodiment, when M=2K-1, the 2ath display sub-area includes: the a-th sub-pixel group, and the first display sub-area includes: the first row of sub-pixels to (X/K)-Y+th 1 row of sub-pixels, the 2K-1th display sub-area includes: (X*(K-1)/K)+Y+1th row of sub-pixels The X-th row of sub-pixels, the b-th display sub-area includes: (X* (b-1)/2*K)+Y+1 row of sub-pixels to (X*(b+1)/2*K)-Y row of sub-pixels. Exemplarily, when X=18, K=3, Y=2, the display area includes five display sub-areas, the first display sub-area includes: the first row of sub-pixels to the fourth row of sub-pixels, the second display sub-area The area includes: the fifth row of sub-pixels to the eighth row of sub-pixels, the third display sub-area includes: the ninth row of sub-pixels to the tenth row of sub-pixels, and the fourth display sub-area includes: the eleventh row of sub-pixels to the fourteenth row of sub-pixels The row of sub-pixels, the fifth display sub-region includes: the fifteenth row of sub-pixels to the eighteenth row of sub-pixels.

In an exemplary embodiment, as shown in FIG. 8, when M=2K-1, the second initial signal line INIT2 of the odd-numbered display sub-area is electrically connected to the first power supply line SL-1, and the even-numbered display sub-area The second initial signal line INIT2 of the zone is electrically connected to the second power supply line SL-1; the voltage value of the signal on the first power supply line SL-1 is smaller than the voltage value of the signal on the second power supply line SL-1.

The display substrate provided in FIG. 8 can be used for sub-pixels in the even-numbered display sub-regions by differently setting the voltage value of the signal of the first power supply line SL-1 and the voltage value of the signal of the second power supply line SL-2. The reset degree of the fourth node is compensated, so that the signal of the fourth node of the sub-pixel of the even-numbered display sub-region after the fourth node is reset is the same as the signal of the sub-pixel of the odd-numbered display sub-region after the reset of the fourth node The signals of the fourth node are the same, thereby eliminating the dark band at the split screen, avoiding poor split screen, and improving the display effect of the display substrate.

In an exemplary embodiment, as shown in FIG. 6 to FIG. 8 , there are two power supply lines among the first power supply line SL-1 to the Nth power supply line SL-N, and they are respectively located at opposite sides of the display area. Set both sides.

In an exemplary embodiment, as shown in FIGS. 6 to 8 , the display area is further provided with a plurality of first initial connection lines (not shown in the figures), a plurality of second initial connection lines CL2 and a plurality of third initial connection lines. A connection line (not shown in the figure); any one of the first initial connection line, the second initial connection line CL2 and the third initial connection line at least partially extends along the second direction Y.

In an exemplary embodiment, the first initial connection lines located in different display sub-areas are arranged at intervals, the second initial connection lines CL2 located in different display sub-areas are arranged at intervals, and the third initial connection lines located in different display sub-areas are arranged at intervals.

In an exemplary embodiment, the first initial connection lines and the first initial signal lines located in the same display sub-region have a mesh structure and are electrically connected to each other. The network structure of the first initial connection lines and the first initial signal lines located in the same display sub-region can ensure the display uniformity of the display substrate.

In an exemplary embodiment, the second initial connection lines and the second initial signal lines located in the same display sub-region have a mesh structure and are electrically connected to each other. The mesh structure of the second initial connection lines and the second initial signal lines located in the same display sub-region can ensure display uniformity of the display substrate.

In an exemplary embodiment, the third initial connection lines and the third initial signal lines located in the same display sub-region have a mesh structure and are electrically connected to each other. The mesh structure of the second initial connection lines and the second initial signal lines located in the same display sub-region can ensure display uniformity of the display substrate.

FIG. 11 is a schematic diagram of the connection between the first display sub-region and the first power supply line in the display substrate provided in FIG. 7 , and FIG. 12 is a schematic diagram of the connection between the second display sub-region and the second power supply line in the display substrate provided in FIG. 7 , and FIG. 13 Figure 7 is a schematic diagram of the connection between the third display sub-region and the third power supply line in the display substrate, Figure 14 is a schematic diagram of the connection between the odd display sub-region and the first power supply line in the display substrate provided in Figure 8, and Figure 15 is FIG. 8 is a schematic diagram of the connection between the even-numbered display sub-region and the second power supply line in the display substrate. As shown in Figures 11 to 15, the non-display area is further provided with: a first initial power supply line INITL1 and a third initial power supply line INITL3 extending at least partially along the second direction Y, and the first initial power supply line INITL1 is connected to all sub-display The first initial signal line INIT1 of the sub-display area is connected, and the third initial power supply line INITL3 is connected to the third initial signal line INIT3 located in all sub-display areas.

In an exemplary embodiment, any one of the first power supply line to the Nth power supply line, the first initial power supply line and the third initial power supply line may be located in the frame area and the binding area.

In an exemplary embodiment, there are two first initial power supply lines INITL1, which are respectively located on opposite sides of the display area.

In an exemplary embodiment, there are two third initial power supply lines INITL3, which are respectively located on opposite sides of the display area.

In an exemplary embodiment, as shown in FIGS. 11 to 15 , the first power supply line SL-1 to the Nth power supply line SL-N, the first initial power supply line INITL1 and the third initial power supply line located on the same side of the display area The line INITL3 is arranged along the first direction X. The arrangement order of the first power supply line SL- 1 to the Nth power supply line SL-N, the first initial power supply line INITL1 and the third initial power supply line INITL3 may be any order, and this disclosure does not impose any limitation on this.

In an exemplary embodiment, the display substrate may include: a base and a driving structure layer disposed on the base, and the driving structure layer includes: a pixel driving circuit, a first initial signal line, a second initial signal line, a third initial signal line, the first power supply line to the Nth power supply line, the first initial power supply line and the third initial power supply line;

In an exemplary embodiment, any one of the first power supply line to the Nth power supply line is arranged on the same layer as the first initial power supply line and the third initial power supply line, and is located between the first initial signal line, the second initial signal line Any one of the signal lines and the third initial signal line is away from the side of the substrate.

When the display substrate is an LTPO display substrate, the driving structure layer may include: a light-shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, and a second insulating layer stacked on the substrate in sequence. The second conductive layer and the fourth insulating layer. A second semiconductor layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a fifth conductive layer, a seventh insulating layer and a flat layer.

The pixel driving circuit includes at least one low-temperature polysilicon transistor and at least one metal oxide transistor. The signal line connected to the control electrode of the low-temperature polysilicon transistor is called the first gate line. Taking FIG. 3A as an example, the first gate line may include the first scanning line, the first reset line, the second reset line and the light emitting line, the signal line connected to the control electrode of the metal oxide transistor is called the second gate line, taking Figure 3A as an example, the second gate line may include the second scan line . Wherein, the first gate line may have a single-layer structure, and the second gate line may have a double-layer structure.

In an exemplary embodiment, any one of the first initial signal line, the second initial signal line, and the third initial signal line may be located in any one of the light-shielding layer, the third conductive layer, or the fourth conductive layer. .

In example embodiments, an active layer of the low temperature polysilicon transistor may be located on the first semiconductor layer.

In an exemplary embodiment, the first grid line and one of the plates of the capacitor may be located on the first conductive layer.

In an exemplary embodiment, the other plate of the capacitor and one film layer of the second gate line may be located on the second conductive layer.

In an exemplary embodiment, another film layer of the second gate line may be located on the third conductive layer.

In an exemplary embodiment, the first electrodes and the second electrodes of all transistors in the pixel driving circuit may be located on the fourth conductive layer.

In an exemplary embodiment, any one of the data signal line, the first power line, the first initial connection line, the second initial connection line and the third initial connection line may be located in the fourth conductive layer and the fifth conductive layer At least one film layer in .

In some examples, the substrate can be a rigid substrate, such as a glass substrate. However, this embodiment does not limit it. For example, the substrate may be a flexible substrate, for example made of insulating material such as resin. In addition, the substrate may be a single-layer structure or a multi-layer structure. When the substrate has a multilayer structure, inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride may be placed in a single layer or in multiple layers between layers.

In an exemplary embodiment, as shown in FIGS. 11 to 15 , any one of the first power supply line to the Nth power supply line and the first initial power supply line and the third initial power supply line may be located on the fifth conductive layer.

In an exemplary embodiment, the display substrate may further include: a light emitting structure layer, an encapsulation structure layer, and an encapsulation cover plate. In some possible implementation manners, the display substrate may include other film layers, such as spacer pillars, touch structure layers, etc., which are not limited in this disclosure.

In exemplary embodiments, the light emitting structure layer may include an anode layer, a pixel definition layer, an organic light emitting layer, and a second electrode. The anode layer can include the first electrode of the light emitting element, the anode can be arranged on the flat layer of the driving structure layer, and be electrically connected to the transistor of the pixel driving circuit through the via hole opened on the flat layer; the pixel definition layer is arranged on the anode layer and the flat layer On the pixel definition layer, a pixel opening is provided, and the pixel opening exposes at least part of the surface of the first electrode; the organic light-emitting layer is at least partially arranged in the pixel opening, and the organic light-emitting layer is connected to the first electrode; the second electrode is arranged on the organic light-emitting layer. On the layer, the second electrode is connected with the organic light-emitting layer; the organic light-emitting layer emits light of a corresponding color under the drive of the first electrode and the second electrode.

In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may use inorganic materials, and the second encapsulation layer may use The organic material, the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

In exemplary embodiments, the organic light emitting layer may include at least a hole injection layer, a hole transport layer, a light emitting layer, and a hole blocking layer stacked on the anode. In some examples, the hole injection layers of all sub-pixels can be a common layer connected together, the hole transport layers of all sub-pixels can be a common layer connected together, and the light-emitting layers of adjacent sub-pixels can have a small amount of Overlapping, or may be separate, hole blocking layers may be common layers connected together. However, this embodiment does not limit it.

In an exemplary embodiment, FIG. 16 is a schematic structural diagram of a display substrate provided in an exemplary embodiment. The non-display area is also provided with at least one second signal line S2; the second signal line S2 is respectively electrically connected to the two first initial power supply lines INITL1 located on both sides of the display area and the first initial connection line CL1 located in the display area, or The two third initial power supply lines INITL3 on both sides of the display area are electrically connected to the third initial connection line CL3 on the display area. Wherein, the second signal line S2 is located in the bonding area B1.

As shown in Figure 3B, the signal of the third initial signal line INIT3 will be written into the third node N3 before the light-emitting phase, and after the light-emitting phase, the third node N3 quickly pulls the potential of the fourth node N4 to rise, so that the light-emitting device emits light Therefore, when the display screen of the display substrate is of low gray scale and low brightness, the voltage value of the signal of the third initial signal line INIT3 will directly affect the speed at which the light-emitting device is turned on, and the voltage of the signal of the third initial signal line INIT3 The larger the value, the faster the light-emitting device turns on; on the contrary, the smaller the voltage value of the signal of the third initial signal line INIT3, the slower the light-emitting device turns on. Therefore, if the third initial signal line INIT3 fluctuates, it will easily cause deviations in low gray scale brightness. For the display substrate without the second signal line S2, the third initial signal of the third initial signal line is input to the display area from both sides of the display substrate, while the transition coupling of other signals in the display substrate Under the influence, the reset degree of the third node N3 of the sub-pixel located in the middle and both sides of the display substrate may be different, the reset degree of the third node N3 of the sub-pixel located in the middle of the display substrate is small, and the reset degree of the third node N3 of the sub-pixel located on both sides of the display substrate may be different. The reset degree of the third node N3 of the sub-pixel is relatively large, so that the display substrate has the problem that the center is brighter, the two sides are darker, and the display effect is not good. However, the setting of the second signal line S2 in the present disclosure enables the third initial signal not only to be input to the display area from both sides of the display substrate, but also to be output from the middle of the display substrate to the display area, which can improve the performance of the third initial power supply line. Load capacity and stability, reducing the difference in the reset degree of the third node of the sub-pixel located on both sides and the middle of the display substrate, eliminating the problem of brightness differences between the two sides and the middle of the display substrate, and improving the display effect of the display substrate .

In an exemplary embodiment, FIG. 17 is a schematic structural diagram of a binding area provided in an exemplary embodiment. As shown in FIG. 17 , the non-display area also includes test pins arranged on the side of the binding area away from the display area Group 51.

As shown in FIG. 17, the second signal line may include: a first connection segment L1, a second connection segment L2, a third connection segment L3, a fourth connection segment L4, a fifth connection segment L5, a sixth connection segment L6 and a Seven connecting segment L7. Wherein, any one of the first connecting section L1, the third connecting section L3 and the seventh connecting section L7 extends at least partly along the first direction X, and the second connecting section L2, the fourth connecting section L4, and the fifth connecting section Any one of L5 and sixth connecting segment L6 at least partially extends along the second direction Y. FIG. 18 illustrates an example in which the second signal line is electrically connected to the two third initial power supply lines INITL3 located on both sides of the display area and the third initial connection line CL3 located in the display area.

In the state where the second signal line is electrically connected to the two first initial power supply lines located on both sides of the display area and the first initial connection line located in the display area, one end of the first connection section L1 is connected to one of the first initial power supply lines One end of the line is electrically connected, the other end of the first connection section L1 is electrically connected to the middle section of the second connection section L2, one end of the second connection section L2 is electrically connected to one end of the third connection section L3, and the third connection section L3 The other end is electrically connected to one end of the fifth connection section L5, one end of the fourth connection section L4 is electrically connected to the middle of the third connection section L3, the other end of the fourth connection section L4 is electrically connected to the first initial connection line, and the fifth connection section L4 is electrically connected to the middle of the third connection section L3. The other end of the connection section L5 is electrically connected to one end of the sixth connection section L6, the other end of the sixth connection section L6 is electrically connected to the test pin group, and one end of the seventh connection section L7 is electrically connected to the middle of the fifth connection section L5 , the other end of the seventh connection section L7 is electrically connected to another first initial power supply line;

In an exemplary embodiment, as shown in FIG. 17 , in a state where the second signal line is electrically connected to two third initial power supply lines located on both sides of the display area AA and the third initial connection line INITL3 located in the display area , one end of the first connection section L1 is electrically connected to one end of one of the third initial power supply lines, the other end of the first connection section L1 is electrically connected to the middle section of the second connection section L2, and one end of the second connection section L2 is electrically connected to the first One end of the third connection section L3 is electrically connected, the other end of the third connection section L3 is electrically connected to one end of the fifth connection section L5, one end of the fourth connection section L4 is electrically connected to the middle of the third connection section L3, and the fourth connection section The other end of L4 is electrically connected to the third initial connection line (not shown in the figure), the other end of the fifth connection section L5 is electrically connected to one end of the sixth connection section L6, and the other end of the sixth connection section L6 is connected to the test lead. The legs are electrically connected, one end of the seventh connection section L7 is electrically connected to the middle of the fifth connection section L5, and the other end of the seventh connection section L7 is electrically connected to another third initial power supply line INITL3.

In an exemplary embodiment, the non-display area further includes: a first power line PL1 and a second power line PL2, the first power line is electrically connected to the pixel driving circuit and is configured to provide a power signal to the pixel driving circuit, and the second power line The wire is electrically connected to the second electrode of the light emitting device and is configured to provide a power signal to the second electrode of the light emitting device.

In an exemplary embodiment, as shown in FIG. 17 , the binding area B1 may include: a first fan-out area B111, a bending area B112, a second fan-out area B113, a second fan-out area B113, and a A circuit area B114, a third fan-out area B115, a driver chip area B116, and a binding pin area B10.

In an exemplary embodiment, as shown in FIG. 17 , the first fan-out area B111 may be connected to the display area AA. The bending area B112 is connected between the first fan-out area B111 and the second fan-out area B112, and can be configured such that the binding area B1 is bent to the back of the display area AA. The first circuit area B114 may at least include: a test circuit group 42 . The test circuit group may include multiple test circuits, and the test circuits may be configured to be electrically connected to multiple data lines in the display area and provide test data signals to the multiple data lines in the display area. The driver chip area B116 includes a driver chip pin group 61 . The driver chip pin group can be electrically connected to multiple data lines, and is configured to be bound to at least one driver chip. For example, each driver chip pin group can be configured to be bound to one driver chip. In FIG. 17 , the fan-out wirings in the first fan-out area B111 , the second fan-out area B113 and the third fan-out area B115 are omitted. FIG. 17 schematically shows several connection lines between the test circuit group and the binding pin group, and the connection lines between the binding pin group and the test pin group. This embodiment does not limit the number of these connecting lines.

In an exemplary embodiment, the first fan-out area B111 further includes: multiple groups of first fan-out routings. Multiple groups of first fan-out routings may be arranged along the first direction X. Each group of first fan-out routings may include multiple first fan-out routings, and the first fan-out routings may include: data extension lines of multiple data lines in the display area in the bonding area.

In an exemplary embodiment, as shown in FIG. 17 , the bonding area B1 may include a plurality of first power lines PL1 and a plurality of second power lines PL2 . The binding pin group 41 in the binding pin area B10 can be electrically connected to two second power lines PL2 and one first power line PL1, and the first power line PL1 can be located on the two second power lines in the first direction X. between power lines PL2. The first power line PL1 can be electrically connected to the second power pin of the binding pin group in the binding pin area B10, and the second power line PL2 can be electrically connected to the first power pin in the binding pin group .

In some examples, the number of driver chip pin groups in the driver chip area B116 and the number of bonding pin groups in the bonding pin area B10 may be the same. Multiple driver chip pin groups and multiple binding pin groups can be connected in one-to-one correspondence. The pins in the pin group of the driver chip can be electrically connected to the pins in the corresponding binding pin group through the pin connecting wire 600 . The pin connection lines 600 may generally extend along the second direction Y, and may be sequentially arranged along the first direction X. Referring to FIG. For example, the driver chip pin group 61 is correspondingly connected to the binding pin group 41 . This embodiment does not limit it.

In an exemplary embodiment, the first power line PL1 and the second power line PL2 may be located in the bonding area B1 and the bezel area B2.

FIG. 18 is an enlarged view of area A1 in FIG. 17 , FIG. 19 is an enlarged view of area A2 in FIG. 17 , and FIG. 20 is an enlarged view of area A3 in FIG. 17 . In an exemplary embodiment, as shown in FIGS. 17 to 20 , the first connecting section L1, the second connecting section L2, the third connecting section L3, the fifth connecting section L5, the sixth connecting section L6 and the seventh connecting section L7 is located on the side of the second fan-out area B113 away from the display area AA, the first connection segment L1 and the seventh connection segment L7 are located on the side of the third connection segment L3 away from the display area, and are located in the first circuit area B114, the second Any one of the three fan-out areas B115 and the driver chip area B116, any one of the second connection segment L2 and the fifth connection segment L5 is at least partially located in the first circuit area B114, the third fan-out area B115, the driver chip area B116 and the binding pin area B10, the sixth connection section L6 is located in the binding pin area B10, the fourth connection section L4 is located on the side of the first circuit area B114 close to the display area AA, and is at least partially located in the first fan-out zone B111, bending zone B112 and second fan-out zone B113.

In an exemplary embodiment, as shown in FIGS. 18 to 20 , the orthographic projections of the first connection section L1 and the seventh connection section L7 on the substrate are respectively the same as the projections of the first power line PL1 and the second power line PL2 on the substrate. The orthographic projections are at least partially overlapped; the orthographic projections of the fourth connecting segment L4 on the substrate and the orthographic projections of the first power line PL1 on the substrate are at least partially overlapped.

In an exemplary embodiment, as shown in FIG. 20 , the fourth connection section L4 may include: sequentially disposing a first subsection L41 , a second subsection L42 and a third subsection L43 along a direction close to the display area AA. Wherein, the first subsection L41 is electrically connected to the third connection section L3 and the second subsection L42 respectively, and the third subsection L43 is electrically connected to the second subsection L42; the first subsection L41 is at least partly located in the second fan-out area B113, and the orthographic projection on the substrate at least partially overlaps the orthographic projection of the first power line PL1 on the substrate, the second subsection L42 is at least partially located in the bending area B112, and the third subsection L43 is at least partially located in the first sector Exit area B111.

In some examples, the first power line PL1 and the second power line PL2 can be single-layer wiring, for example, can be located on the fourth conductive layer or the fifth conductive layer; or, the first power line PL1 and the second power line PL2 can be It is a double-layer routing, for example, it may be a layered structure routing of the fourth conductive layer and the fifth conductive layer. This embodiment does not limit it. FIG. 18 and FIG. 19 are illustrated by taking the first power line PL1 and the second power line PL2 as the wiring of the stacked structure of the fourth conductive layer and the fifth conductive layer as an example.

In an exemplary embodiment, as shown in FIGS. 18 and 19 , the first connection section L1 and the seventh connection section L7 are located on a side of the first power line PL1 or the second power line PL2 close to the substrate. Exemplarily, the first connection segment L1 and the seventh connection segment L7 may be located in at least one film layer of the first conductive layer, the second conductive layer and the third conductive layer.

In an exemplary embodiment, as shown in FIG. 18 and FIG. 19 , the second connecting segment L2, the third connecting segment L3, the fifth connecting segment L5 and the sixth connecting segment L6 are located on the side of the first connecting segment L1 away from the base , the sixth connection section L6 is located on the side of the fifth connection section L5 away from the base. The second connecting segment L2, the third connecting segment L3 and the fifth connecting segment L5 may be located on the fourth conductive layer, and the sixth connecting segment may be located on the fifth conductive layer.

In an exemplary embodiment, as shown in FIG. 20 , the first subsection L41 is located on the side of the third connecting section L3 close to the base, the second subsection L42 is located on the side of the first subsection away from the base, and the third subsection L42 is located on the side of the second subsection close to the base. Exemplarily, the first subsection L41 may be located in at least one film layer of the first conductive layer and the second conductive layer, and the second subsection L42 may be located in at least one film layer of the fourth conductive layer and the fifth conductive layer, The third subsection L43 may be located in at least one film layer of the first conductive layer and the second conductive layer.

In an exemplary embodiment, as shown in FIG. 20 , the display area is further provided with a signal connection line CL, and the signal connection line CL is electrically connected to the initial connection line connected to the third subsection L43 and the second signal line respectively, and the signal connection The line CL is located on the side of the second subsection L42 close to the base. The signal connection line CL can be located on the first conductive layer or the second conductive layer.

In an exemplary embodiment, as shown in FIG. 20 , an opening V is provided on the side of the first power line PL1 in the binding area B1 close to the display area, and the second subsection L42 extends to the opening V of the first power line PL1. place.

In an exemplary embodiment, FIG. 21 is a partial schematic diagram of a binding region. As shown in Figure 21, the binding area also includes: the first connection line H-1 to the N+2th connection line H-(N+2), the nth connection line is electrically connected to the nth power supply line, and the N+1th connection line is electrically connected to the nth power supply line. The power supply line is electrically connected to the first initial power supply line, and the N+2th power supply line is electrically connected to the third initial power supply line. The driver chip area includes: the first pin P-1 to the P-(N+2) pin, The i-th connection line is electrically connected to the i-th pin P-i, where i is a positive integer greater than or equal to 1 and less than or equal to N+2. FIG. 21 takes N=2 as an example for illustration.

In an exemplary embodiment, the first to N+2th connection lines may be located on the fifth conductive layer, and the first to P-(N+2)th pins may be located on the fourth conductive layer.

In an exemplary embodiment, as shown in FIG. 21 , the binding area is further provided with a virtual connection line DUL. The setting of the virtual connection line DUL can ensure the uniformity of etching of the display substrate.

In an exemplary embodiment, the dummy connection line DUL may be disposed on the same layer as the first to N+2th connection lines.

In an exemplary embodiment, the resistance of the signal line mentioned in the present disclosure can be realized by adjusting the width of the signal line.

An embodiment of the present disclosure also provides a display device, including: a display substrate.

The display substrate is the display substrate provided by any one of the above-mentioned embodiments, and the realization principle and the realization effect are similar, and will not be repeated here.

In an exemplary embodiment, the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. The other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present application.

The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

In the drawings used to describe the embodiments of the present disclosure, the thickness and size of layers or microstructures are exaggerated for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element, Or intervening elements may be present.

Although the embodiments disclosed in the present disclosure are as above, the content described is only the embodiments adopted to facilitate understanding of the present disclosure, and is not intended to limit the present disclosure. Anyone skilled in the art to which this disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this disclosure, but the scope of patent protection of this disclosure must still be The scope defined by the appended claims shall prevail.

Claims (20)

1. A display substrate having a display region and a non-display region, wherein the display region is provided with a plurality of first signal lines and sub-pixels arranged in an array, the non-display region is provided with first to nth power lines, the first signal lines extend at least partially in a first direction, any one of the first to nth power lines extends at least partially in a second direction, and the first and second directions intersect;

the first signal line is electrically connected with the sub-pixel and is configured to provide an initial signal to the sub-pixel;

the display area is divided into M display subareas which are arranged along the second direction, first signal lines in the same display subarea are connected with the same power supply line, and first signal lines in at least two display subareas are connected with different power supply lines, wherein M and N are more than or equal to 2.

2. The display substrate according to claim 1, wherein the display region is provided with a plurality of first initial signal lines and a plurality of second initial signal lines extending in the first direction, the sub-pixel includes a pixel driving circuit configured to drive the light emitting device to emit light, and a light emitting device, the pixel driving circuit includes: a driving transistor, the light emitting device comprising: a first electrode configured to supply an initial signal to one of source and drain electrodes of the driving transistor, and a second initial signal line configured to supply an initial signal to the first electrode of the light emitting device;

the first signal line includes any one of a first initial signal line and a second initial signal line.

3. The display substrate according to claim 2, wherein the display region is further provided with a plurality of third initial signal lines extending in the first direction, the third initial signal lines being configured to supply an initial signal to another electrode of the source-drain electrodes of the driving transistors;

the first signal line includes any one of a first initial signal line, a second initial signal line, and a third initial signal line.

4. A display substrate according to claim 2 or 3, wherein when the first signal line is a second initial signal line, m=k or 2K-1, K is the number of times the second initial signal line effectively initializes the first electrode of the light emitting device within a target period, the effective initialization means that the second initial signal line adjusts the first electrode of the light emitting device from the first signal to a second signal, the voltage value of the first signal is different from the voltage value of the second signal, the second signal is a signal transmitted by the second initial signal line, and the target period is equal to the period of one display frame.

5. The display substrate of claim 4, wherein when M = K, the mth display sub-region comprises: the number of the sub-pixels in the (M-1) X/K+1 row is from the sub-pixels in the (M-1) X/K row to the sub-pixels in the (M-X/K) row, wherein M is more than or equal to 1 and less than or equal to M, and X is the total number of the sub-pixels included in the display area.

6. The display substrate according to claim 5, wherein n=m, the second initial signal line of the N-th display sub-area is electrically connected to the N-th power supply line, and N is 1.ltoreq.n;

the voltage values of the signals of the first to nth power supply lines are the same.

7. The display substrate according to claim 4, wherein when m=2k_1, a blanking region is included between two adjacent display frames; the a-th subpixel group includes: the (X a/K) -Y+1 row of sub-pixels to (X a/K) +Y row of sub-pixels, wherein X is the total number of rows of sub-pixels included in the display area, and Y is the ratio of the duration in the blanking area to the duration in which one row of sub-pixels is displayed;

The first sub-pixel group to the K-1 sub-pixel group are respectively positioned in different display subareas.

8. The display substrate of claim 7, wherein when M = 2K-1, the 2 nd display sub-region comprises: an a-th sub-pixel group, the first display sub-region comprising: the first row of subpixels to (X/K) -Y+1 row of subpixels, the 2K-1 display sub-region includes: the (X (K-1)/K) +Y+1 row of subpixels, the X row of subpixels, the b display sub-region comprises: the (X (b-1)/2*K) +Y+1 row sub-pixels are provided to the (X (b+1)/2*K) -Y row sub-pixels.

9. The display substrate according to claim 5 or 8, wherein when M = 2K "1, the second initial signal line of the odd-numbered display sub-area is electrically connected to the first power supply line, and the second initial signal line of the even-numbered display sub-area is electrically connected to the second power supply line;

the voltage value of the signal of the first power supply line is smaller than the voltage value of the signal of the second power supply line.

10. A display substrate according to claim 3, wherein the number of any one of the first to nth power supply lines is two and is located on opposite sides of the display area, respectively.

11. A display substrate according to claim 3, wherein the display area is further provided with a plurality of first initial connecting lines, a plurality of second initial connecting lines and a plurality of third initial connecting lines; any one of the first, second, and third initial connecting lines extends at least partially along the second direction;

The first initial connecting lines are arranged at intervals and the second initial connecting lines are arranged at intervals and the third initial connecting lines are arranged at intervals and the first initial connecting lines and the first initial signal lines are in a net structure and are electrically connected with each other, the second initial connecting lines and the second initial signal lines are in a net structure and are electrically connected with each other, and the third initial connecting lines and the third initial signal lines are in a net structure and are electrically connected with each other;

the non-display area is further provided with: a first initial power supply line and a third initial power supply line extending at least partially in the second direction, the first initial power supply line being connected to first initial signal lines located in all sub-display areas, the third initial power supply line being connected to third initial signal lines located in all sub-display areas;

the number of the first initial power supply lines is two, and the first initial power supply lines are respectively positioned at two sides of the display area which are oppositely arranged; the first to nth power supply lines, the first initial power supply line, and the third initial power supply line located on the same side of the display area are arranged along the first direction.

12. The display substrate of claim 11, comprising: a substrate and a drive structure layer disposed on the substrate, the drive structure layer comprising: a pixel driving circuit, a first initial signal line, a second initial signal line, a third initial signal line, first to nth power supply lines, first and third initial power supply lines;

any one of the first power supply line to the Nth power supply line is arranged on the same layer as the first initial power supply line and the third initial power supply line, and is positioned on one side of any one of the first initial signal line, the second initial signal line and the third initial signal line, which is far away from the substrate.

13. The display substrate of claim 12, wherein the non-display region comprises: the binding area is positioned at one side of the display area, the frame area is positioned at the other sides of the display area, and the non-display area is also provided with at least one second signal line;

the second signal lines are respectively and electrically connected with two first initial power supply lines positioned at two sides of the display area and a first initial connecting line positioned in the display area, or two third initial power supply lines positioned at two sides of the display area and a third initial connecting line positioned in the display area;

Any one of the first power supply line to the nth power supply line, the first initial power supply line and the third initial power supply line is located in the frame area and the binding area, and the second signal line is located in the binding area.

14. The display substrate of claim 13, wherein the non-display region further comprises a set of test pins disposed on a side of the bonding region remote from the display region;

the second signal line includes: a first connection section, a second connection section, a third connection section, a fourth connection section, a fifth connection section, a sixth connection section, and a seventh connection section, any one of the first connection section, the third connection section, and the seventh connection section extending at least partially in the first direction, any one of the second connection section, the fourth connection section, the fifth connection section, and the sixth connection section extending at least partially in a second direction;

in a state that the second signal wire is respectively electrically connected with two first initial power supply wires positioned at two sides of the display area and a first initial connecting wire positioned at the display area, one end of the first connecting section is electrically connected with one end of one first initial power supply wire, the other end of the first connecting section is electrically connected with the middle section of the second connecting section, one end of the second connecting section is electrically connected with one end of the third connecting section, the other end of the third connecting section is electrically connected with one end of the fifth connecting section, one end of the fourth connecting section is electrically connected with the middle section of the third connecting section, the other end of the fourth connecting section is electrically connected with the first initial connecting wire, the other end of the fifth connecting section is electrically connected with one end of the sixth connecting section, the other end of the sixth connecting section is electrically connected with the test pin group, one end of the seventh connecting section is electrically connected with the middle section of the fifth connecting section, and the other end of the seventh connecting section is electrically connected with the other first initial power supply wire;

And in a state that the second signal wire is respectively electrically connected with two third initial power supply wires positioned at two sides of the display area and a third initial connecting wire positioned at the display area, one end of the first connecting section is electrically connected with one end of one third initial power supply wire, the other end of the first connecting section is electrically connected with the middle section of the second connecting section, one end of the second connecting section is electrically connected with one end of the third connecting section, the other end of the third connecting section is electrically connected with one end of the fifth connecting section, one end of the fourth connecting section is electrically connected with the middle section of the third connecting section, the other end of the fourth connecting section is electrically connected with the third initial connecting wire, the other end of the fifth connecting section is electrically connected with one end of the sixth connecting section, the other end of the sixth connecting section is electrically connected with the test pin group, one end of the seventh connecting section is electrically connected with the middle section of the fifth connecting section, and the other end of the seventh connecting section is electrically connected with the other third initial power supply wire.

15. The display substrate of claim 14, wherein the non-display region further comprises: a first power line electrically connected to the pixel driving circuit and configured to supply a power signal to the pixel driving circuit, and a second power line electrically connected to the second electrode of the light emitting device and configured to supply a power signal to the second electrode of the light emitting device; the binding area includes: the first fan-out area, the bending area, the second fan-out area, the first circuit area, the third fan-out area, the driving chip area and the binding pin area are sequentially arranged along the direction away from the display area; the first power line and the second power line are positioned in the binding area and the frame area;

The first connection section, the second connection section, the third connection section, the fifth connection section, the sixth connection section and the seventh connection section are all located on one side of the second fan-out area away from the display area, the first connection section and the seventh connection section are located on one side of the third connection section away from the display area and located in any one of the first circuit area, the third fan-out area and the driving chip area, any one of the second connection section and the fifth connection section is located at least partially in the first circuit area, the third fan-out area, the driving chip area and the binding pin area, the sixth connection section is located in the binding pin area, the fourth connection section is located on one side of the first circuit area close to the display area and located at least partially in the first fan-out area, the bending area and the second fan-out area;

orthographic projections of the first connecting section and the seventh connecting section on the substrate are overlapped with orthographic projections of the first power line and the second power line on the substrate at least partially respectively; the orthographic projection of the fourth connection section on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate.

16. The display substrate of claim 15, wherein the fourth connection section comprises: the first subsection, the second subsection and the third subsection are sequentially arranged along the direction close to the display area, and the third signal line is positioned in the display area;

the first subsection is electrically connected with the third connecting section and the second subsection respectively, and the third subsection is electrically connected with the second subsection;

the first sub-section is at least partially located in the second fan-out area, the orthographic projection on the substrate and the orthographic projection of the first power line on the substrate are at least partially overlapped, the second sub-section is at least partially located in the bending area, and the third sub-section is at least partially located in the first fan-out area.

17. The display substrate according to claim 16, wherein the first connection section and the seventh connection section are located at a side of the first power line or the second power line close to the substrate, the second connection section, the third connection section, the fifth connection section, and the sixth connection section are located at a side of the first connection section away from the substrate, the first sub-section is located at a side of the third connection section close to the substrate, the second sub-section is located at a side of the first sub-section away from the substrate, the third sub-section is located at a side of the second sub-section close to the substrate, and the sixth connection section is located at a side of the fifth connection section away from the substrate.

18. The display substrate according to claim 17, wherein the display area is further provided with signal connection lines electrically connected to the initial connection lines to which the third sub-segment and the second signal line are connected, respectively, the signal connection lines having a single-layer structure and being located at a side of the second sub-segment near the substrate.

19. The display substrate of claim 16, wherein an opening is provided on a side of the first power line located in the bonding region near the display region, and the second sub-segment extends to the opening of the first power line.

20. A display device, comprising: a display substrate according to any one of claims 1 to 19.