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CN116722830B - A fully differential low offset high gain operational amplifier - Google Patents

A fully differential low offset high gain operational amplifier Download PDF

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Publication number
CN116722830B
CN116722830B CN202310758597.5A CN202310758597A CN116722830B CN 116722830 B CN116722830 B CN 116722830B CN 202310758597 A CN202310758597 A CN 202310758597A CN 116722830 B CN116722830 B CN 116722830B
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mos tube
drain
mos
gate
resistor
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CN116722830A (en
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李泽宏
汪鑫
曾传扬
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45484—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit
    • H03F3/45488—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by using feedback means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45484—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit
    • H03F3/45547—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by using feedforward means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention belongs to the technical field of operational amplifiers, and particularly relates to a fully-differential low-offset high-gain operational amplifier. The invention comprises an operational amplifier core and a feedforward common mode feedback, wherein the operational amplifier core amplifies differential signals, and the feedforward common mode feedback circuit stabilizes the common mode voltage of input and output. The invention uses the common gate circuit of the floating bias and the series resistance of the high-gain NPN tube as the current mirror, obviously improves the gain, reduces the input offset voltage, has higher output swing and good stability, and is suitable for being used in the programmable gain circuit of the analog front end.

Description

Full-differential low-offset high-gain operational amplifier
Technical Field
The invention belongs to the technical field of operational amplifiers, and particularly relates to a fully-differential low-offset high-gain operational amplifier.
Background
The fully differential operational amplifier is used as a basic module in an analog-digital hybrid circuit, and the most common application is in an analog front-end circuit as a variable gain amplifier for analog front-end sampling. In some high-performance hybrid circuits, the accuracy and noise performance of the front-end sampling directly determine the performance of the whole chip, and for the op-amp of the front-end sampling, high gain and low offset determine the accuracy of the front-end sampling. In addition, various portable devices have strong demands for low power consumption, so that extensive researches on fully differential operational amplifiers with low offset, low noise, low power consumption and high gain are conducted in academia and industry.
Disclosure of Invention
The invention aims to provide a fully differential operational amplifier circuit with low power consumption, low noise, high gain and low offset.
The technical scheme adopted by the invention is as follows:
A fully differential low-offset high-gain operational amplifier comprises a gain stage circuit, an output stage circuit, a Miller compensation circuit and a feedforward common-mode feedback circuit;
The gain stage circuit comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a first triode Q1, a second triode Q2, a first resistor R1 and a second resistor R2, wherein the source electrode of the third MOS transistor M3 is connected with a power supply, the grid electrode of the third MOS transistor M3 is connected with the common mode feedback output of a feedforward common mode feedback circuit, the drain electrode of the third MOS transistor M3 is connected with the source electrode of the first MOS transistor M1 and the source electrode of the second MOS transistor M2, the grid electrode of the first MOS transistor M1 is connected with the negative input end of an amplifier, the drain electrode of the first MOS transistor M4 is connected with the source electrode of the fourth MOS transistor M4, the grid electrode of the fourth MOS transistor M4 and the grid electrode of the fifth MOS transistor M5 are connected with a floating bias voltage, the drain electrode of the fourth MOS transistor M4 is connected with the collector electrode of the first triode Q1, the drain electrode of the fifth MOS transistor M5 is connected with the drain electrode of the second MOS transistor Q2, the drain electrode of the third MOS transistor M1 is connected with the drain electrode of the third MOS transistor Q2 through the first triode Q2 and the drain electrode of the third MOS transistor Q2;
The miller compensation circuit comprises a first capacitor C1, a second capacitor C2, a third resistor R3 and a fourth resistor R4, wherein the output stage circuit comprises a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8 and a ninth MOS tube M9, wherein the source electrode of the sixth MOS tube M6 is connected with a power supply, the drain electrode of the sixth MOS tube M6 is connected with the drain electrode of the fourth MOS tube M4 and the grid electrode of the ninth MOS tube M9 after passing through the first capacitor C1 and the third resistor R3, the drain electrode of the sixth MOS tube M6 is also connected with the drain electrode of the ninth MOS tube M9, the grid electrode of the sixth MOS tube M6 is connected with the feedforward output of the feedforward common mode feedback circuit, the source electrode of the seventh MOS tube M7 is connected with the drain electrode of the fifth MOS tube M5 and the grid electrode of the eighth MOS tube M8 after passing through the second capacitor C2 and the fourth resistor R4, and the grid electrode of the seventh MOS tube M7 is connected with the feedforward output of the feedforward common mode feedback circuit;
The feed-forward common mode feedback circuit comprises a third capacitor C3, a fourth capacitor C4, a fifth resistor R5, a sixth resistor R6, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13 and a fourteenth MOS tube M14, wherein the third capacitor C3 and the fifth resistor R5 form a first parallel circuit, one end of the first parallel circuit is connected with the grid electrode of the twelfth MOS tube M12, the other end of the first parallel circuit is connected with the drain electrode of the seventh MOS tube M7, the fourth capacitor C4 and the sixth resistor R6 form a second parallel circuit, one end of the second parallel circuit is connected with the grid electrode of the twelfth MOS tube M12, the other end of the second parallel circuit is connected with the drain electrode of the sixth MOS tube M6, the grid electrode of the tenth MOS tube M10 is connected with the drain electrode of the thirteenth MOS tube M12, the drain electrode of the thirteenth MOS tube M10 is connected with the drain electrode of the thirteenth MOS tube M14, the drain electrode of the thirteenth MOS tube M13 is connected with the drain electrode of the thirteenth MOS tube M13;
the drain electrode of the sixth MOS tube M6 is connected with the negative output end of the amplifier, and the drain electrode of the seventh MOS tube M7 is connected with the positive output end of the amplifier.
The invention has the beneficial effects that the gain is improved by using the common gate and the NPN triode, the input voltage range is improved by adopting the floating bias of the common gate, the offset voltage and the noise are reduced by adopting the NPN triode and the resistor as a current mirror, and the common mode stability and the output voltage range are improved by adopting the simple common source stage with feedforward common mode feedback.
Drawings
FIG. 1 is a schematic diagram of a fully differential low offset high gain operational amplifier provided by the present invention;
FIG. 2 is a graph of the frequency response of a fully differential low offset high gain operational amplifier provided by the present invention;
FIG. 3 is a schematic diagram of simulation results of input offset voltage through 300 Monte Carlo simulations in an embodiment of the present invention;
FIG. 4 is a plot of noise frequency for a high fully differential low offset high gain operational amplifier provided by the present invention;
FIG. 5 is a schematic diagram of a sinusoidal output simulation waveform when a closed loop 2-fold gain is achieved in accordance with an embodiment of the present invention.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a fully differential low offset high gain operational amplifier according to the present invention, including a first stage gain stage, a second stage output stage, a miller compensation circuit, and a feed-forward common mode feedback. The first-stage gain electrode adopts a current mirror load formed by a common gate, a PNP tube and a resistor to improve the output resistance of the first stage, thereby improving the first-stage gain. The common-gate tube adopts floating bias, and the bias voltage VBP2 is 1.5V lower than the fixed voltage of the drain electrode M3. The current mirror is composed of Q1, Q2, R1 and R2, and the PNP tube is used as the current mirror to further reduce mismatch voltage. The grid voltage of the bias current tube of the first-stage gain stage is the common-mode feedback output VP1, so that the common-mode stability is improved. And the second-stage output stage is a simple common-source stage circuit, and the current bias adopts feedforward common-mode feedback voltage output VP2 to form common-mode feedforward feedback, so that the common-mode stability is greatly improved. The miller compensation circuit is connected in series by using a resistor and a capacitor, so that the differential mode stability of the circuit is improved. The feedforward common mode feedback adopts two pairs of resistor-capacitor voltage division to adopt an output common mode voltage, a PMOS (P-channel metal oxide semiconductor) with a diode connection method is used as a load, an NMOS (N-channel metal oxide semiconductor) pair tube is used as an input to form the common mode feedback with feedforward, wherein the voltage VCM is a reference common mode level.
As shown in fig. 1, in the fully differential low-offset high-gain operational amplifier according to the embodiment of the invention, MOS transistors M1 and M2 are input pair transistors, and the area of the transistors is larger, so that offset and noise are reduced. M4 and M5 are common gate tubes, and the grid voltage VBP2 is 1.5V lower than the source voltage of the input tube, so that floating bias is realized. The operational amplifier current mirror is composed of Q1, R1, Q2 and R2, and the existence of the resistor further improves the gain. The second stage is a simple common source circuit, and the MOS transistors M8 and M9 are second stage input transistors, wherein l is smaller, and a larger output swing is achieved for reducing overdrive voltage. The Miller compensation circuit consisting of the capacitors C1 and C2 and the resistors R3 and R4 carries out frequency response compensation on the operational amplifier, and the in-band zero point is introduced through the resistors R3 and R4, so that the operational amplifier has a phase margin of more than sixty degrees, and the working state is stabilized.
The right side of fig. 1 is a feedforward common-mode feedback section of the present invention, taking common-mode levels of output voltages through C3, C4, R5, R6, amplifying the pipes M12 and M11 through common-mode inputs, and feeding back the output common-mode feedback signals to the first-stage bias and the second-stage bias in the form of mirror currents generating M10 and M11. The common mode feedback voltage generated by M11 is directly transmitted to output signals VOUTP and VOUTN through second stage bias tubes M6 and M7, so that the common mode feedback voltage becomes feedforward common mode feedback. This feedback enables the common mode level to be maintained stable even in the case where the differential mode high gain is achieved and the common mode feedback power consumption is low. The common mode feedback module only consumes 6.03 muA current, and the total power consumption of the invention is only 58.35 muA.
Fig. 2 shows the frequency characteristic simulation result of a fully differential low offset high gain operational amplifier, and the input resistance is 1M ohms, the gain is 118.51dB when the gain is set to 3.2 times, and the phase margin is 81 °. The gain improvement technical effect is obvious.
Fig. 3 is a simulation result of input offset voltage of two hundred times Monte Carlo simulation of a fully differential low offset high gain operational amplifier, and the maximum offset voltage is 183.4 mu V only, so that the technical effect is obvious.
FIG. 4 is a graph of the noise frequency of the high fully differential low offset high gain operational amplifier provided by the present invention, with an integral noise of only 276 μV at 0.1Hz-10 KHz.
FIG. 5 is a schematic diagram of a sinusoidal output simulation waveform when the embodiment of the invention is connected into a closed loop with a 3.2-time gain, and can see that the output can reach an output swing of + -4V when the power supply voltage is 4.5V.

Claims (1)

1.一种全差分低失调高增益运算放大器，其特征在于，包括增益级电路、输出级电路、密勒补偿电路和前馈共模反馈电路；1. A fully differential low offset high gain operational amplifier, characterized in that it comprises a gain stage circuit, an output stage circuit, a Miller compensation circuit and a feedforward common mode feedback circuit; 所述增益级电路包括第一MOS管M1、第二MOS管M2、第三MOS管M3、第四MOS管M4、第五MOS管M5、第一三极管Q1、第二三极管Q2、第一电阻R1和第二电阻R2；其中第三MOS管M3的源极接电源，其栅极接前馈共模反馈电路的共模反馈输出，其漏极接第一MOS管M1的源极和第二MOS管M2的源极；第一MOS管M1的栅极接放大器的负向输入端，其漏极接第四MOS管M4的源极；第二MOS管M2的栅极接放大器的正向输入端，其漏极接第五MOS管M5的源极；第四MOS管M4的栅极和第五MOS管M5的栅极连接浮动偏置电压，第四MOS管M4的漏极接第一三极管Q1的集电极，第五MOS管M5的漏极接第二三极管Q2的集电极；第一三极管Q1的基极和第二三极管Q2的基极接偏置电压，第一三极管Q1的发射极通过第一电阻R1后接地，第二三极管Q2的发射极通过第二电阻R2后接地；The gain stage circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a first triode Q1, a second triode Q2, a first resistor R1 and a second resistor R2; wherein the source of the third MOS tube M3 is connected to the power supply, the gate thereof is connected to the common mode feedback output of the feedforward common mode feedback circuit, and the drain thereof is connected to the source of the first MOS tube M1 and the source of the second MOS tube M2; the gate of the first MOS tube M1 is connected to the negative input terminal of the amplifier, and the drain thereof is connected to the source of the fourth MOS tube M4; the second The gate of the MOS tube M2 is connected to the positive input terminal of the amplifier, and the drain thereof is connected to the source of the fifth MOS tube M5; the gate of the fourth MOS tube M4 and the gate of the fifth MOS tube M5 are connected to the floating bias voltage, the drain of the fourth MOS tube M4 is connected to the collector of the first triode Q1, and the drain of the fifth MOS tube M5 is connected to the collector of the second triode Q2; the base of the first triode Q1 and the base of the second triode Q2 are connected to the bias voltage, the emitter of the first triode Q1 is grounded after passing through the first resistor R1, and the emitter of the second triode Q2 is grounded after passing through the second resistor R2; 所述密勒补偿电路包括第一电容C1、第二电容C2、第三电阻R3和第四电阻R4，所述输出级电路包括第六MOS管M6、第七MOS管M7、第八MOS管M8和第九MOS管M9；其中第六MOS管M6的源极接电源，其漏极通过第一电容C1和第三电阻R3后接第四MOS管M4的漏极和第九MOS管M9的栅极，第六MOS管M6的漏极还接第九MOS管M9的漏极，第六MOS管M6的栅极接前馈共模反馈电路的前馈输出；第七MOS管M7的源极接电源，其漏极通过第二电容C2和第四电阻R4后接第五MOS管M5的漏极和第八MOS管M8的栅极，第七MOS管M7的栅极接前馈共模反馈电路的前馈输出；第八MOS管M8的源极和第九MOS管M9的源极接地；The Miller compensation circuit includes a first capacitor C1, a second capacitor C2, a third resistor R3 and a fourth resistor R4, and the output stage circuit includes a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8 and a ninth MOS tube M9; wherein the source of the sixth MOS tube M6 is connected to the power supply, and the drain thereof is connected to the drain of the fourth MOS tube M4 and the gate of the ninth MOS tube M9 through the first capacitor C1 and the third resistor R3, the drain of the sixth MOS tube M6 is also connected to the drain of the ninth MOS tube M9, and the gate of the sixth MOS tube M6 is connected to the feedforward output of the feedforward common mode feedback circuit; the source of the seventh MOS tube M7 is connected to the power supply, and the drain thereof is connected to the drain of the fifth MOS tube M5 and the gate of the eighth MOS tube M8 through the second capacitor C2 and the fourth resistor R4, and the gate of the seventh MOS tube M7 is connected to the feedforward output of the feedforward common mode feedback circuit; the source of the eighth MOS tube M8 and the source of the ninth MOS tube M9 are grounded; 所述前馈共模反馈电路包括第三电容C3、第四电容C4、第五电阻R5、第六电阻R6、第十MOS管M10、第十一MOS管M11、第十二MOS管M12、第十三MOS管M13、第十四MOS管M14；其中第三电容C3和第五电阻R5构成第一并联电路，第一并联电路的一端接第十二MOS管M12的栅极，另一端接第七MOS管M7的漏极；第四电容C4和第六电阻R6构成第二并联电路，第二并联电路的一端接第十二MOS管M12的栅极，另一端接第六MOS管M6的漏极；第十MOS管M10的源极接电源，其栅极和漏极互连，其漏极接第十二MOS管M12的漏极，第十MOS管M10的漏极为前馈共模反馈电路的共模反馈输出；第十一MOS管M11的源极接电源，其栅极和漏极互连，其漏极接第十三MOS管M13的漏极，第十一MOS管M11的漏极为前馈共模反馈电路的前馈输出；第十三MOS管M13的栅极接共模电源，第十三MOS管M13的源极接第十二MOS管M12的源极和第十四MOS管M14的漏极；第十四MOS管M14的栅极接偏置电压，其源极接地；The feedforward common-mode feedback circuit includes a third capacitor C3, a fourth capacitor C4, a fifth resistor R5, a sixth resistor R6, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, and a fourteenth MOS tube M14; wherein the third capacitor C3 and the fifth resistor R5 form a first parallel circuit, one end of the first parallel circuit is connected to the gate of the twelfth MOS tube M12, and the other end is connected to the drain of the seventh MOS tube M7; the fourth capacitor C4 and the sixth resistor R6 form a second parallel circuit, one end of the second parallel circuit is connected to the gate of the twelfth MOS tube M12, and the other end is connected to the drain of the sixth MOS tube M6; the tenth MOS The source of the transistor M10 is connected to the power supply, the gate and the drain thereof are interconnected, the drain thereof is connected to the drain of the twelfth MOS transistor M12, and the drain of the tenth MOS transistor M10 is the common-mode feedback output of the feedforward common-mode feedback circuit; the source of the eleventh MOS transistor M11 is connected to the power supply, the gate and the drain thereof are interconnected, the drain thereof is connected to the drain of the thirteenth MOS transistor M13, and the drain of the eleventh MOS transistor M11 is the feedforward output of the feedforward common-mode feedback circuit; the gate of the thirteenth MOS transistor M13 is connected to the common-mode power supply, the source of the thirteenth MOS transistor M13 is connected to the source of the twelfth MOS transistor M12 and the drain of the fourteenth MOS transistor M14; the gate of the fourteenth MOS transistor M14 is connected to the bias voltage, and the source thereof is grounded; 第六MOS管M6的漏极连接放大器的负向输出端，第七MOS管M7的漏极连接放大器的正向输出端。The drain of the sixth MOS tube M6 is connected to the negative output terminal of the amplifier, and the drain of the seventh MOS tube M7 is connected to the positive output terminal of the amplifier.
CN202310758597.5A 2023-06-26 2023-06-26 A fully differential low offset high gain operational amplifier Active CN116722830B (en)

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CN111464139A (en) * 2020-04-24 2020-07-28 电子科技大学 A Common Mode Feedback Circuit for Wide Swing Fully Differential Operational Amplifiers

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US9438188B2 (en) * 2014-09-15 2016-09-06 Qualcomm Incorporated Common-gate amplifier for high-speed DC-coupling communications
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CN109728786A (en) * 2019-03-01 2019-05-07 赣南师范大学 A High-Gain Two-Stage Operational Transconductance Amplifier with Crossover Structure

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Publication number Priority date Publication date Assignee Title
CN101355346A (en) * 2008-09-17 2009-01-28 清华大学 Frequency Compensation Method of Broadband Common Mode Feedback Loop for Two-Stage Operational Amplifier
CN111464139A (en) * 2020-04-24 2020-07-28 电子科技大学 A Common Mode Feedback Circuit for Wide Swing Fully Differential Operational Amplifiers

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