CN116743172B - Analog-to-digital converter sampling bias circuit and analog-to-digital converter sampling method - Google Patents

Abstract

The invention discloses an analog-to-digital converter sampling bias circuit and an analog-to-digital converter sampling method, wherein the circuit comprises a voltage bias module, a floating voltage generation module and a sampling control module which are sequentially connected in a ring shape; the voltage bias module is used for biasing the voltage to be sampled to generate bias voltage and sending bias signals corresponding to the bias voltage to the sampling control module; the floating voltage generation module is used for generating a floating voltage based on the voltage to be sampled and the bias voltage so that the voltage value of the floating voltage is within the sampling range of the analog-to-digital converter; the sampling control module is used for obtaining the sampling voltage obtained after the analog-to-digital converter collects the floating voltage, and obtaining the voltage value of the voltage to be sampled based on the bias signal and the sampling voltage. According to the invention, the basic voltage in the voltage to be sampled is removed by setting the bias voltage, and only the variation range is sampled, so that the sampling precision and resolution of the analog-digital converter are greatly improved.

Description

Analog-to-digital converter sampling bias circuit and analog-to-digital converter sampling method

Technical field

The present invention relates to the technical field of analog-to-digital converter acquisition, and in particular to an analog-to-digital converter sampling bias circuit and an analog-to-digital converter sampling method.

Background technique

The Baseboard Management Controller (BMC) chip in a traditional server system usually has an Analog-to-Digital Converter (ADC) pin in it for collecting voltage signals. Servers usually use digital-to-analog converter pins to monitor the power supply inside the motherboard, such as the voltage of power rails such as P12V, P5V, and P3.3V. These power rails are allowed to have an error range of 10% during normal operation. In order to ensure the normal operation of the system and facilitate later debugging, the normal operating voltage of the power rails, etc., needs to be monitored and recorded.

Generally, the sampling range of the digital-to-analog converter is small (usually 0V ~ 3.3V). For signals whose variation range is within the sampling range of the digital-to-analog converter, the digital-to-analog converter can directly sample. However, when the signal that needs to be sampled and changed exceeds the digital-to-analog converter sampling range, When the analog-to-analog converter has a normal sampling range, the voltage to be collected needs to be proportionally reduced by resistor voltage division, so as to comply with the sampling variation range of the digital-to-analog converter. For example, when a 12V working voltage needs to be sampled, it needs to be divided into equal proportions to about 3.3V through resistors.

The voltage variation range of the existing resistor dividing method for voltage sampling is small, but the basic voltage is relatively high. The digital-to-analog converter often cannot make full use of the sampling range of the digital-to-analog converter when sampling, causing the digital-to-analog converter to fail in sampling. There is a problem of low accuracy.

Contents of the invention

The technical problem to be solved by the present invention is that the high-voltage acquisition method of the existing digital-to-analog converter has a small voltage variation range, and the sampling range of the digital-to-analog converter cannot be fully utilized during sampling, so that the digital-to-analog converter has low accuracy during sampling. The problem.

In order to solve the above technical problems, the present invention provides an analog-to-digital converter sampling bias circuit, which is characterized in that it includes a voltage bias module, a floating voltage generation module and a sampling control module connected in sequence in a ring;

The voltage bias module is used to bias the voltage to be sampled to generate a bias voltage, and send a bias signal corresponding to the bias voltage to the sampling control module;

The floating voltage generation module is configured to generate a floating voltage based on the voltage to be sampled and the bias voltage, so that the floating voltage value is within the sampling range of the analog-to-digital converter;

The sampling control module is used to obtain the sampling voltage obtained after the analog-to-digital converter collects the floating voltage, and obtain the voltage value of the voltage to be sampled based on the bias signal and the sampling voltage. The analog-to-digital converter sampling bias circuit of the present invention removes the basic voltage in the voltage to be sampled by setting the bias voltage and only samples the floating voltage, which greatly improves the sampling accuracy and resolution of the analog-to-digital converter.

Preferably, the voltage bias module includes a connected bias trigger unit and a voltage bias unit;

The bias triggering unit is configured to provide different bias parameters for the voltage bias unit based on the voltage to be sampled within different threshold ranges;

The voltage bias unit is used to generate bias voltages of different voltage values based on different bias parameters. The bias triggering unit implements a hierarchical operation on the voltage to be sampled, so that the voltage to be sampled within different threshold ranges corresponds to different bias parameters. The voltage bias unit is used to provide different bias voltages based on different bias parameters, thereby achieving the purpose of providing different bias voltages for voltages to be sampled in different threshold ranges.

Preferably, the bias triggering unit includes a base resistor and at least one set of bias components connected in parallel to both ends of the base resistor;

The bias component includes a bias resistor and a bias control switch connected in series, and a trigger switch connected to the bias control switch. The trigger switch is used to control the bias control switch based on the voltage to be sampled. opening and closing; the bias control switch is used to control whether to connect the bias resistor in parallel to both ends of the basic resistor;

Among them, the trigger switches in different bias components have different trigger voltage values. Through the design of the above-mentioned electronic components and connection relationships, multi-level control of different threshold ranges of the voltage to be sampled is achieved.

Preferably, the trigger switch is a Zener diode, and the bias control switch is an NMOS transistor. The Zener diode can ensure the stability of the voltage, and the NMOS tube plays the role of accurate voltage control switching.

Preferably, the voltage bias unit includes a three-terminal adjustable shunt regulator, a first resistor connected in parallel between the cathode and the reference terminal of the three-terminal adjustable shunt regulator, and a resistor connected to the three-terminal adjustable shunt regulator. A second resistor connected to the cathode of the shunt regulator. The basic resistor is connected in parallel between the anode and the reference terminal of the three-terminal adjustable shunt regulator. The voltage to be sampled is input to the three terminals through the second resistor. Adjustable shunt regulator cathode. The voltage bias unit realizes the voltage bias function through the above-mentioned simple circuit structure, saving costs.

Preferably, the floating voltage generation module includes a differential amplifier circuit, the non-inverting input terminal of the differential amplifier circuit inputs the voltage to be sampled, the inverting input terminal of the differential operational amplifier circuit inputs the bias voltage, and the differential amplifier circuit inputs the bias voltage to the inverting input terminal. The output terminal of the amplifier circuit outputs a floating voltage. The floating voltage generation module amplifies the floating voltage and bias voltage, and controls the floating voltage within a certain range to meet the sampling requirements of the analog-to-digital converter.

Preferably, the positive-phase amplification coefficient and the inverse-phase amplification coefficient of the differential amplifier circuit are equal. The above setting of the amplification coefficient achieves the effect of proportional amplification of the floating voltage and the bias voltage.

Preferably, when the positive-phase amplification coefficient and the inverse-phase amplification coefficient of the differential amplifier circuit are both 1, the voltage value of the voltage to be sampled is the sum of the bias voltage and the sampling voltage. The above setting of the amplification coefficient achieves the proportional amplification effect of the floating voltage and the bias voltage, and makes it easier to calculate the voltage value of the voltage to be sampled. In order to solve the above technical problems, the present invention also provides an analog-to-digital converter sampling method based on the analog-to-digital converter sampling bias circuit, including:

Input the voltage to be sampled into the analog-to-digital converter sampling bias circuit;

The analog-to-digital converter collects the floating voltage output by the floating voltage generation module in the analog-to-digital converter sampling bias circuit, obtains the sampling voltage, and inputs the sampling voltage into the analog-to-digital converter sampling bias circuit. Sampling control module;

The sampling control module outputs the voltage value of the voltage to be sampled.

Preferably, when the operational amplifier circuit in the floating voltage generation module of the analog-to-digital converter sampling bias circuit has both a positive-phase amplification coefficient and an inverse-phase amplification coefficient of 1, the voltage value of the voltage to be sampled is The sum of the bias voltage generated by the voltage bias module of the digital converter sampling bias circuit and the sampling voltage. The analog-to-digital converter sampling method of the present invention removes the basic voltage in the voltage to be sampled by setting a bias voltage and only samples the floating voltage, which greatly improves the sampling accuracy and resolution of the analog-to-digital converter.

Compared with the existing technology, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

The analog-to-digital converter sampling bias circuit provided by the embodiment of the present invention is used to obtain the bias voltage corresponding to the voltage to be sampled through the voltage bias module, and the floating voltage generation module limits the voltage to be sampled within the sampling range of the analog-to-digital converter. , so that the analog-to-digital converter only collects the floating voltage value, and the voltage value to be sampled can be obtained based on the floating voltage value and the bias voltage, which solves the problem when the existing analog-to-digital converter collects voltages outside the sampling range. The existing problems of small voltage variation range and low accuracy need to expand the sampling coverage of the analog-to-digital converter. Furthermore, the basic voltage in the voltage to be sampled is removed by setting the bias voltage, and only the variation range is sampled, which greatly improves the sampling accuracy and resolution of the analog-to-digital converter. In addition, this solution has the advantages of multiple adjustable bias voltages and output range amplification.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and obtained by the structure particularly pointed out in the written description, claims and appended drawings.

Description of the drawings

The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation of the present invention. In the attached picture:

Figure 1 shows a schematic structural diagram of an analog-to-digital converter sampling bias circuit according to an embodiment of the present invention;

Figure 2 shows the circuit diagram of the voltage bias module and the floating voltage generation module in Embodiment 1 of the present invention;

FIG. 3 shows a schematic flow chart of the analog-to-digital converter sampling method in Embodiment 2 of the present invention.

Detailed ways

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples, so that the implementation process of how to apply technical means to solve technical problems and achieve technical effects of the present invention can be fully understood and implemented accordingly. It should be noted that as long as there is no conflict, the various embodiments of the present invention and the various features in the embodiments can be combined with each other, and the resulting technical solutions are within the protection scope of the present invention.

In the design process of the analog-to-digital converter, the main considerations are the sampling range of the analog-to-digital converter and the sampling accuracy of the analog-to-digital converter. The sampling range of the analog-to-digital converter is the range within which the input voltage of the analog-to-digital converter pin is allowed to change, generally 0V to 3.3V; the sampling accuracy of the analog-to-digital converter is usually 10-bit (2^10) sampling accuracy or 12-bit (2^12) Sampling accuracy. According to the sampling accuracy, the resolution of the analog-to-digital converter can be calculated: resolution = sampling range/sampling accuracy.

When the analog-to-digital converter sampling range is between 0V and 3.3V, when the resistor dividing method is used to measure the 12V working voltage, the input voltage 12V can be divided to 3V according to the resistor dividing formula, and the voltage dividing factor is 4. The changing range before voltage division is 10.8V~13.2V, and the changing range after voltage division is 2.7V~3.3V. It only utilizes 18% of the sampling range and does not fully utilize the full performance of the analog-to-digital converter.

Embodiment 1

In order to solve the technical problems existing in the prior art, embodiments of the present invention provide an analog-to-digital converter sampling bias circuit.

Figure 1 shows a schematic structural diagram of an analog-to-digital converter sampling bias circuit according to an embodiment of the present invention; with reference to Figure 1, the analog-to-digital converter sampling bias circuit according to the embodiment of the present invention includes voltage bias modules, floating The voltage generation module and the sampling control module are also connected to the voltage bias module, and the three modules form a ring connection structure.

The analog-to-digital converter sampling bias circuit in the embodiment of the present invention is mainly used to assist the analog-to-digital converter to collect high voltage values that exceed the sampling range of the analog-to-digital converter. In this implementation, the voltage to be sampled by the analog-to-digital converter is used as the voltage to be sampled.

The voltage bias module is mainly used to bias the voltage to be sampled to generate a corresponding bias voltage; while obtaining the bias voltage, it also generates a bias signal corresponding to the bias voltage value, and The signal is sent to the sampling control module.

Further, the voltage bias module includes a connected bias trigger unit and a voltage bias unit.

The bias trigger unit is used to provide different bias parameters for the voltage bias unit based on the voltage to be sampled within different threshold ranges. That is, when the voltage values to be sampled fall within different threshold ranges, different parameter control switches will be triggered, thereby providing bias parameters of different values to the voltage bias unit.

Figure 2 shows a circuit diagram of the voltage bias module and the floating voltage generation module in Embodiment 1 of the present invention; with reference to Figure 2, the bias trigger unit may specifically include a basic resistor and multiple sets of bias components. The multiple sets of bias components are connected in parallel to both ends of the basic resistor. Except for differences in component models, each set of bias components has the same internal structure.

Each set of bias components includes a bias resistor, a bias control switch and a trigger switch; the bias resistor and the bias control switch are connected in series, and the bias control switch is used to control whether the bias resistor is connected in parallel to both ends of the basic resistor. The trigger switch is used to control the opening and closing of the bias control switch based on the voltage to be sampled. Therefore, it can be seen that the bias component mainly uses the voltage to be sampled as a trigger condition. By controlling whether the bias resistor is connected in parallel to both ends of the basic resistor, it can change the overall resistance value in the voltage bias module, thereby achieving various bias parameter values. provided.

In order to bias the voltage to be sampled in different threshold ranges, in this embodiment, the trigger switches in different bias components are set to have different trigger voltage values. And different threshold ranges can also be set based on actual conditions.

Referring to Figure 2, the trigger switch can be set to a Zener diode, and the bias control switch can be set to an NMOS tube. At this time, the gate of the NMOS tube (Gate) is connected to the anode of the Zener diode, the drain (DRAIN) of the NMOS tube is connected to the bias resistor, and the source (SOURCE) of the NMOS tube is connected to ground; the cathode of the Zener diode is connected to the voltage to be sampled. connection; and in order to ensure the startup of the NMOS tube and protect the Zener diode from breakdown, a protection resistor is also connected between the anode of the Zener diode and the ground terminal.

In order to realize that the voltages to be sampled within different threshold ranges can trigger different bias components, it is necessary to set the Zener diodes in different bias components in this embodiment to have different trigger voltage values. For example, the conduction voltages of the Zener diodes in multiple bias components can be set to 3.3V, 6.6V, 9.9V, 13.2V, 16.5V and 19.8V in sequence; thus, when the voltage to be sampled is between 3.3V and 6.6V Within the V range, the bias voltage in only one bias component can be connected in parallel to both ends of the basic resistor; when the voltage to be sampled is in the range of 6.6V to 9.9V, the bias voltages in two bias components can be connected in parallel. At both ends of the basic resistor, the overall resistance is reduced; and by analogy, it is possible to automatically adjust and provide different bias parameters for the voltage to be sampled within different threshold ranges.

The voltage bias unit is mainly used to generate bias voltages of different voltages based on different bias parameters provided by the bias trigger unit. Referring to Figure 2, the voltage bias unit includes a three-terminal adjustable shunt regulator, a first resistor and a second resistor; the first resistor is connected in parallel between the cathode and the reference end of the three-terminal adjustable shunt regulator, and the bias The basic resistor in the trigger unit is connected in parallel between the anode and the reference terminal of the three-terminal adjustable shunt regulator, and the voltage to be sampled is input to the cathode of the three-terminal adjustable shunt regulator through the second resistor.

The three-terminal adjustable shunt regulator sets the output voltage to any value between Vref (approximately 2.5V) and 36V through the overall resistance formed by the first resistor, the base resistor and the bias resistor connected in parallel at both ends. value. At this time, the bias voltage is calculated as follows: bias voltage = (1+the overall resistance formed by the first resistor/the basic resistor and the bias resistor connected in parallel at both ends)*Vref.

In order to ensure the output accuracy, the first resistor, the basic resistor and the bias resistor used in this embodiment can all be selected to be accurate to 0.1% and have a small temperature drift ratio. The second resistor is a current-limiting resistor, which is used to ensure that the required reference source current (IREF) provided by this device remains within the appropriate operating area during turn-on. The reference source current may be as high as 4μA, so it is recommended that the second resistor be a resistor. The value of the resistor is small enough to reduce the error caused by the reference pulling current through VIN.

The floating voltage generation module is mainly used to generate a floating voltage based on the voltage to be sampled and the bias voltage. The generated floating voltage value needs to be within the sampling range of the analog-to-digital converter to meet the sampling requirements of the analog-to-digital converter. Its working principle is to use an operational amplifier to build a subtraction circuit. By differentially amplifying the voltage to be sampled and the bias voltage, the range of changes in the voltage to be sampled is extracted and amplified into the sampling range of the analog-to-digital converter. In order to realize that the analog-to-digital converter only measures the floating voltage to obtain the voltage value exceeding its sampling range voltage.

Referring to Figure 2, the floating voltage generation module specifically includes an operational amplifier U1A and surrounding resistors and capacitors. The operational amplifier U1A and the surrounding resistors and capacitors form a differential amplification circuit (ie, a subtraction circuit). The non-inverting input terminal of the differential amplifier circuit inputs the voltage to be sampled, the inverting input terminal of the differential amplifier circuit inputs the bias voltage, and the output terminal of the differential amplifier circuit outputs a floating voltage. Further, the resistors configured around the operational amplifier U1A include resistors R1, R4, R5 and R7. The resistors R1, R4, R5 and R7 are all feedback resistors for limiting the corresponding amplification coefficient. At this time, the floating voltage is calculated as: floating voltage = -(R7/R5)*bias voltage+(R1/R4)*voltage to be sampled. In order to achieve higher output accuracy and lower error in practical applications, the above-mentioned feedback resistors are all selected with resistors with a high accuracy of 0.1% and low temperature drift. The capacitors configured around the operational amplifier U1A include capacitor C1 and capacitor C2. Both capacitor C1 and capacitor C2 are decoupling capacitors.

Furthermore, in order to ensure that the difference between the voltage to be sampled and the bias voltage is proportional, it is necessary to set the positive-phase amplification coefficient and the inverse-phase amplification coefficient of the differential amplifier circuit to be equal. Furthermore, when the positive-phase amplification coefficient and the inverse-phase amplification coefficient of the differential amplifier circuit are both 1, the value of the floating voltage output by the differential operational amplifier at this time is the difference between the voltage to be sampled and the bias voltage.

After obtaining the bias signal corresponding to the bias voltage, the sampling control module also needs to obtain the sampling voltage obtained after the analog-to-digital converter collects the floating voltage. Then, the corresponding bias voltage is obtained based on the bias signal, and the voltage value of the voltage to be sampled is calculated and obtained based on the bias signal, the sampling voltage, the amplification factor of the differential amplifier circuit, etc. When the positive-phase amplification coefficient and the inverse-phase amplification coefficient of the differential amplifier circuit are both 1, the voltage value of the voltage to be sampled is the sum of the bias voltage and the sampling voltage generated by the voltage bias module of the analog-to-digital converter sampling bias circuit. . Assuming that the forward amplification coefficient and the inverting amplification coefficient of the differential amplifier circuit are both 1/2, the voltage value of the voltage to be sampled is two times the bias voltage generated by the voltage bias module of the analog-to-digital converter sampling bias circuit. The sum of times and twice the sampling voltage, where the concept of twice is the reciprocal of the amplification factor 1/2.

And when the circuit structure of the differential amplifier circuit is not the above structure, when the positive-phase input voltage of the differential amplifier circuit to be sampled and the reverse-input bias voltage are disproportionately reduced due to the differential amplifier circuit structure or external circuit structure, etc. Or expand; at this time, the differential amplifier circuit can be set to have different positive-phase amplification coefficients and inverse-phase amplification coefficients, so that the forward voltage to be subtracted and the voltage to be sampled are proportional to the differential amplifier circuit during the subtraction operation. , and the inverted voltage to be subtracted exists in proportion to the bias voltage, and the two ratios are the same; this ensures that the floating voltage obtained is a proportional scaling of the difference voltage, and the difference voltage is the voltage to be sampled The voltage obtained by differing from the bias voltage can still obtain the floating voltage based on the voltage to be sampled, the bias voltage and the amplification factor of the differential amplifier circuit.

In order to explain the analog-to-digital converter sampling bias circuit more clearly according to the embodiment of the present invention, the circuit diagram shown in FIG. 2 is used as a specific example to illustrate the working methods of the voltage bias module and the floating voltage generation module.

Among them, the analog-to-digital converter sampling bias circuit includes a voltage bias module, a floating voltage generation module and a sampling control module connected in a ring. The voltage bias module includes a connected bias trigger unit and a voltage bias unit. The bias trigger unit includes a basic resistor R8 and six groups of bias components connected in parallel to both ends of the basic resistor. Each group of bias components includes a bias resistor and a bias control switch connected in series, and a trigger switch connected to the bias control switch. , the trigger switch is a Zener diode, and the bias control switch is an NMOS tube. The voltage bias unit includes a three-terminal adjustable shunt regulator D1, a first resistor R6 connected in parallel between the cathode and the reference terminal of the three-terminal adjustable shunt regulator D1, and the three-terminal adjustable shunt regulator D1 The cathode of the second resistor R2 is connected, and the basic resistor R8 is connected in parallel between the anode and the reference terminal of the three-terminal adjustable shunt regulator. The voltage to be sampled is input to the cathode of the three-terminal adjustable shunt regulator D1 through the second resistor R2.

The floating voltage generation module includes a differential amplifier circuit U1A and its surrounding configurations of resistors R1, R4, R5 and R7. The resistor R4 is connected to the positive input terminal of the differential amplifier circuit U1A, the resistor R1 is connected between the positive input terminal of the differential amplifier circuit U1A and the ground terminal, the capacitor C1 is connected in parallel to both ends of the resistor R1, and the resistor R5 is connected to the reverse input terminal of the differential amplifier circuit U1A. Phase input terminal, resistor R7 is connected between the positive phase input terminal and the output terminal of the differential amplifier circuit U1A; the output terminal of the differential amplifier circuit U1A is also connected to a resistor R3. In order to achieve higher output accuracy and lower error in practical applications, resistors R1, R4, R5, R7 and R3 should all be selected with high accuracy of 0.1% and low temperature drift.

Assume that the floating voltage is Ufloat, the bias voltage is U3, and the voltage to be sampled is Vcc. At this time, there is the following relationship:

Ufloat=-(R7/R5)*Vcc+(R1/R4)*U3; when R7=R5 and R1=R4, the above formula can be simplified to:

Ufloat=Vcc–U3

That is, the floating voltage is the difference between the voltage to be sampled and the bias voltage.

The bias trigger unit of the voltage bias module in this circuit scheme includes 6 sets of bias components, and the trigger voltages of the 6 sets of bias components are 3.3V, 6.6V, 9.9V, 13.2V, 16.5V and 19.8V respectively. .

The process of automatically adjusting the bias voltage based on the voltage value of the voltage to be sampled is as follows:

When the voltage to be sampled exceeds 3.3V and is lower than 6.6V: Zener diode D7 turns on, the gate pin level of NMOS tube Q6 changes from 0 to high level, NMOS tube Q6 turns on, bias resistor R14 and basic Resistor R8 is connected in parallel to form a voltage divider with the first resistor R6. At this time, the three-terminal adjustable parallel regulator D1 provides a bias voltage of 3.3V for the voltage stabilizing circuit; at the same time, the OFFSET_3V3 bias signal changes from the default 0 It is a high level for the sampling control module to read and judge.

When the voltage to be sampled exceeds 6.6V and is lower than 9.9V: Zener diodes D6 and D7 are turned on, the gate pin levels of NMOS tubes Q5 and Q6 change from 0 to high level, and NMOS tubes Q5 and Q6 are turned on. The bias resistor R14, the bias resistor R13 and the basic resistor R8 are connected in parallel to form a voltage divider with the first resistor R6. At this time, the three-terminal adjustable shunt regulator D1 provides a bias voltage of 6.6V for the voltage stabilizing circuit; At the same time, the OFFSET_6.6V bias signal changes from the default 0 to high level for the sampling control module to read and judge.

When the voltage to be sampled exceeds 9.9V and is lower than 13.2V: the voltage regulator tubes D5, D6, and D7 are turned on, and the gate pin levels of the NMOS tubes Q6, Q5, and Q4 change from 0 to high level, and the NMOS tubes Q6, Q5 and Q4 are turned on, and R8 is connected in parallel with R14, R13, and R12 to form a voltage divider with R6. At this time, the voltage stabilizing circuit dominated by D1 provides a bias voltage of 9.9V; at the same time, the OFFSET_9V9 bias signal changes from the default 0 It is a high level for the sampling control module to read and judge.

When the voltage to be sampled exceeds 13.2V and is lower than 16.5V: Zener diodes D4, D5, D6 and D7 are turned on, and the gate pin levels of NMOS tubes Q3, Q4, Q5 and Q6 change from 0 to high level. NMOS tubes Q3, Q4, Q5 and Q6 are turned on, and the bias resistor R14, bias resistor R13, bias resistor R12, bias resistor R11 and basic resistor R8 are connected in parallel with the first resistor R6 to form a voltage divider. At this time, the three terminals The adjustable shunt regulator D1 provides a bias voltage of 13.2V for the main voltage stabilizing circuit; at the same time, the OFFSET_13.2V bias signal changes from the default 0 to a high level for the sampling control module to read and judge.

When the voltage to be sampled exceeds 16.5V and is lower than 19.8V: Zener diodes D3, D4, D5, D6 and D7 are turned on, and the gate pin levels of NMOS tubes Q2, Q3, Q4, Q5 and Q6 change from 0 becomes high level, NMOS tubes Q2, Q3, Q4, Q5 and Q6 are turned on, bias resistor R14, bias resistor R13, bias resistor R12, bias resistor R11, bias resistor R10 and basic resistor R8 are connected in parallel with The first resistor R6 forms a voltage divider. At this time, the three-terminal adjustable parallel regulator D1 provides a bias voltage of 16.5V for the voltage stabilizing circuit. At the same time, the OFFSET_16.5V bias signal changes from the default 0 to a high voltage. Flat, for the sampling control module to read and judge.

When the voltage to be sampled exceeds 19.8V and is lower than 23.1V: Zener diodes D2, D3, D4, D5, D6 and D7 are turned on, and the gate pins of NMOS tubes Q1, Q2, Q3, Q4, Q5 and Q6 The level changes from 0 to high level, NMOS tubes Q1, Q2, Q3, Q4, Q5 and Q6 are turned on, bias resistor R14, bias resistor R13, bias resistor R12, bias resistor R11, bias resistor R10, The bias resistor R9 and the basic resistor R8 are connected in parallel to form a voltage divider with the first resistor R6. At this time, the three-terminal adjustable shunt regulator D1 provides a bias voltage of 19.8V for the main voltage stabilizing circuit; at the same time, OFFSET_19.8V The bias signal changes from the default 0 to high level for the sampling control module to read and judge.

When measuring voltage, the voltage is divided into two parts: the bias voltage and the sampling voltage obtained after the analog-to-digital converter collects the floating voltage. When the forward amplification coefficient and the inverting amplification coefficient of the differential amplifier circuit are both 1, and if the sampling The voltage is U0, the bias voltage is U3, and when the voltage to be sampled is Vcc,

The actual voltage to be sampled Vcc should be expressed as:

Vcc＝U3+U0

The bias voltage is obtained by judging the corresponding OFFSET signal through the GPIO of the sampling control module. The corresponding table is as follows:

Table: Corresponding relationship between bias voltage, bias voltage indication and VCC

Among them, L represents low voltage and H represents high voltage.

This solution can provide up to 6 bias voltage levels of 3.3V, 6.6V, 9.9V, 13.2V, 16.5V and 19.8V, and can measure voltages within VCC<23.1V. It should be noted that the bias voltage of other gears can also be set based on actual conditions, which will not be described too much here. The final bias signal obtained by the sampling control module in the above process shall be based on the bias signal representing the highest bias voltage.

In another example, since the power rail allows a 10% error range during normal operation, the variation range of the 12V voltage to be sampled is 12V-10% ~ 12V + 10% (10.8V ~ 13.2V). In order to improve the sampling accuracy, the voltage bias module in the analog-to-digital converter sampling bias circuit according to the embodiment of the present invention can be set to provide a bias voltage of 10V. At this time, the floating voltage ranges from 0.8V to 3.2V; at this time, the proportion is 73%, which is a 4-fold increase in the voltage variation range compared to the existing resistor voltage dividing method for sampling. At this time, the analog-to-digital converter only needs to sample the floating voltage part, and its resolution is 3mV; finally, the true voltage value of the voltage to be sampled can be obtained by summing the bias voltage and floating voltage (both types of differential amplification coefficients are 1) . In practical applications, the greater the difference between the voltage that needs to be sampled and the sampling range, the more obvious the resolution improvement effect will be.

The analog-to-digital converter sampling bias circuit provided by the embodiment of the present invention obtains the bias voltage corresponding to the voltage to be sampled through the voltage bias module, and limits the voltage to be sampled within the sampling range of the analog-to-digital converter through the floating voltage generation module. The analog-to-digital converter only collects the floating voltage value, and the voltage value of the voltage to be sampled can be obtained based on the floating voltage value and the bias voltage, which solves the problem when the existing analog-to-digital converter collects voltages outside the sampling range. The voltage variation range is small and the accuracy is low, and the sampling coverage of the analog-to-digital converter is expanded. Furthermore, the basic voltage in the voltage to be sampled is removed by setting the bias voltage, and only the variation range is sampled, which greatly improves the sampling accuracy and resolution of the analog-to-digital converter. In addition, this solution has the advantages of multiple adjustable bias voltages and output range amplification.

Embodiment 2

In order to solve the technical problems existing in the prior art, embodiments of the present invention provide an analog-to-digital converter sampling method.

The analog-to-digital converter sampling method in the embodiment of the present invention is implemented based on the analog-to-digital converter sampling bias circuit described in the first embodiment. FIG. 3 shows a schematic flow chart of the analog-to-digital converter sampling method according to the second embodiment of the present invention. Referring to FIG. 3 , the analog-to-digital converter sampling method according to the embodiment of the present invention includes the following steps.

Step S201: Input the voltage to be sampled into the analog-to-digital converter sampling bias circuit.

Specifically, the analog-to-digital converter is connected to the analog-to-digital converter sampling bias circuit, and the voltage to be sampled is input into the analog-to-digital converter and the analog-to-digital converter sampling bias circuit. The voltage bias module of the analog-to-digital converter sampling bias circuit is automatically triggered to generate the corresponding bias voltage based on the voltage to be sampled. The floating voltage generation module of the analog-to-digital converter sampling bias circuit generates a floating voltage based on the voltage to be sampled and the bias voltage. .

Step S202, the analog-to-digital converter collects the floating voltage output by the floating voltage generation module in the analog-to-digital converter sampling bias circuit, obtains the sampling voltage, and inputs the sampling voltage into the sampling control in the analog-to-digital converter sampling bias circuit. module.

Specifically, the analog-to-digital converter collects the floating voltage output by the measurement floating voltage generation module, obtains the sampling voltage, and transmits the sampling voltage to the sampling control module of the sampling bias circuit of the analog-to-digital converter.

Step S203, the sampling control module outputs the voltage value of the voltage to be sampled.

Specifically, the sampling control module generates the voltage value of the voltage to be sampled based on the obtained bias signal and floating voltage. When the differential amplifier circuit in the floating voltage generation module of the analog-to-digital converter sampling bias circuit has both a positive-phase amplification coefficient and an inverse-phase amplification coefficient of 1, the voltage value of the voltage to be sampled is the analog-to-digital converter sampling bias The sum of the bias voltage generated by the circuit's voltage bias module and the sampled voltage.

The analog-to-digital converter sampling method provided by the embodiment of the present invention uses the analog-to-digital converter sampling bias circuit to divide the voltage to be sampled into two parts: the bias voltage and the floating voltage, and at the same time limits the floating voltage to be sampled by the analog-to-digital converter. Within the range, it solves the problems of small voltage variation range and low accuracy when the existing analog-to-digital converter collects voltages outside the sampling range, expands the sampling coverage of the analog-to-digital converter, and greatly improves Sampling accuracy and resolution of the analog-to-digital converter.

Although the disclosed embodiments of the present invention are as above, the described contents are only used to facilitate understanding of the present invention and are not intended to limit the present invention. Any person skilled in the technical field to which the present invention belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure of the present invention. However, the protection scope of the present invention remains The scope defined by the appended claims shall prevail.

Claims (9)

1. An analog-to-digital converter sampling bias circuit, characterized in that it includes a voltage bias module, a floating voltage generation module and a sampling control module connected in sequence in a ring; The voltage bias module is used to bias the voltage to be sampled to generate a bias voltage, and send a bias signal corresponding to the bias voltage to the sampling control module; The floating voltage generation module is configured to generate a floating voltage based on the voltage to be sampled and the bias voltage, so that the floating voltage value is within the sampling range of the analog-to-digital converter; The sampling control module is used to obtain the sampling voltage obtained after the analog-to-digital converter collects the floating voltage, and obtain the voltage value of the voltage to be sampled based on the bias signal and the sampling voltage; Wherein, the voltage bias module includes a connected bias trigger unit and a voltage bias unit; The bias triggering unit is configured to provide different bias parameters for the voltage bias unit based on the voltage to be sampled within different threshold ranges; The voltage bias unit is used to generate bias voltages of different voltage values based on different bias parameters. 2. The bias circuit according to claim 1, wherein the bias triggering unit includes a basic resistor and at least one set of bias components connected in parallel to both ends of the basic resistor; The bias component includes a bias resistor and a bias control switch connected in series, and a trigger switch connected to the bias control switch. The trigger switch is used to control the bias control switch based on the voltage to be sampled. opening and closing; the bias control switch is used to control whether to connect the bias resistor in parallel to both ends of the basic resistor; Among them, the trigger switches in different bias components have different trigger voltage values. 3. The bias circuit according to claim 2, wherein the trigger switch is a Zener diode, and the bias control switch is an NMOS tube. 4. The bias circuit according to claim 2, wherein the voltage bias unit includes a three-terminal adjustable shunt regulator, connected in parallel between the cathode and the reference terminal of the three-terminal adjustable shunt regulator. The first resistor between the three-terminal adjustable shunt regulator, and the second resistor connected to the cathode of the three-terminal adjustable shunt regulator, the basic resistor is connected in parallel between the anode and the reference terminal of the three-terminal adjustable shunt regulator, the The voltage to be sampled is input to the cathode of the three-terminal adjustable shunt regulator through the second resistor. 5. The bias circuit according to claim 1, characterized in that the floating voltage generation module includes a differential amplifier circuit, a positive input terminal of the differential amplifier circuit inputs the voltage to be sampled, and the differential amplifier circuit The inverting input terminal of the differential amplifier circuit inputs the bias voltage, and the output terminal of the differential amplifier circuit outputs a floating voltage. 6. The bias circuit according to claim 5, wherein the positive-phase amplification coefficient and the inverse-phase amplification coefficient of the differential amplifier circuit are the same. 7. The bias circuit according to claim 5, characterized in that when the positive-phase amplification coefficient and the inverse-phase amplification coefficient of the differential amplifier circuit are both 1, the voltage value of the voltage to be sampled is the voltage value of the bias circuit. The sum of the set voltage and the sampled voltage. 8. An analog-to-digital converter sampling method based on the analog-to-digital converter sampling bias circuit of any one of claims 1 to 7, characterized in that it includes: Input the voltage to be sampled into the analog-to-digital converter sampling bias circuit; The analog-to-digital converter collects the floating voltage output by the floating voltage generation module in the analog-to-digital converter sampling bias circuit, obtains the sampling voltage, and inputs the sampling voltage into the analog-to-digital converter sampling bias circuit. Sampling control module; The sampling control module outputs the voltage value of the voltage to be sampled. 9. The sampling method according to claim 8, characterized in that when the differential amplifier circuit in the floating voltage generation module of the analog-to-digital converter samples the bias circuit, its positive-phase amplification coefficient and inverse-phase amplification coefficient are both 1, the voltage value of the voltage to be sampled is the sum of the bias voltage generated by the voltage bias module of the analog-to-digital converter sampling bias circuit and the sampled voltage.