CN116760664B - Low-power LVDS transmitter - Google Patents
Low-power LVDS transmitterInfo
- Publication number
- CN116760664B CN116760664B CN202310713719.9A CN202310713719A CN116760664B CN 116760664 B CN116760664 B CN 116760664B CN 202310713719 A CN202310713719 A CN 202310713719A CN 116760664 B CN116760664 B CN 116760664B
- Authority
- CN
- China
- Prior art keywords
- transistor
- circuit
- transistors
- current
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/028—Arrangements specific to the transmitter end
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Amplifiers (AREA)
Abstract
本申请揭示一种低功耗LVDS发送器，该方案设置开关电路和镜像电流源，使开关电路连接镜像电流源中的至少一晶体管，能够选择性控制镜像电流源中的多个晶体管导通或关断，从而导通或者关断镜像电流源，当镜像电流源导通时，可以通过镜像电流源输出电流至主体驱动电路，使主体驱动电路能够产生差分信号，从而实现数据传输，当镜像电流源关断时，由于无输入电流，主体驱动电路也被关断，实现了在无需通过LVDS发送器进行数据传输时，关断镜像电流源和主体驱动电路，从而降低LVDS发送器的功耗，同时，也不会影响电路中其他功能模块的正常工作。
The present application discloses a low-power LVDS transmitter, which provides a switching circuit and a mirror current source, so that the switching circuit is connected to at least one transistor in the mirror current source, and can selectively control multiple transistors in the mirror current source to be turned on or off, thereby turning on or off the mirror current source. When the mirror current source is turned on, the mirror current source can output current to the main drive circuit, so that the main drive circuit can generate a differential signal, thereby realizing data transmission. When the mirror current source is turned off, the main drive circuit is also turned off due to the lack of input current. This realizes that when data transmission does not need to be performed through the LVDS transmitter, the mirror current source and the main drive circuit are turned off, thereby reducing the power consumption of the LVDS transmitter, and at the same time, it will not affect the normal operation of other functional modules in the circuit.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a low-power-consumption LVDS transmitter.
Background
LVDS (Low Voltage DIFFERENTIAL SIGNALING) adopts extremely Low Voltage swing to realize high-speed differential transmission data, can realize point-to-point or point-to-multipoint connection, and has the characteristics of Low power consumption, low error rate, low crosstalk, low radiation and the like.
In the prior art, whether the differential signal is output by the main body driving circuit of the LVDS transmitter to realize data transmission or not is required, the main body driving circuit is kept in a working state, so that the power consumption of the LVDS transmitter is high.
Disclosure of Invention
In order to solve the above problems, the present application provides a low power LVDS transmitter capable of selectively turning off a main body driving circuit.
According to an aspect of an embodiment of the present application, a low power LVDS transmitter is disclosed, the low power LVDS transmitter includes a mirror current source configured to convert an input first current into a second current output, the mirror current source including a plurality of transistors, a body driving circuit connected to the mirror current source, the body driving circuit configured to generate a differential signal based on the second current, and a switching circuit connected to at least one of the transistors in the mirror current source and configured to selectively control the at least one of the transistors to be turned on or off to control the plurality of transistors in the mirror current source to be turned on or off, wherein when the plurality of transistors are turned off, the mirror current source is turned off.
In one exemplary embodiment, the mirrored current source comprises a first current mirror circuit configured to receive the first current as input and a second current mirror circuit configured to output the second current to the body drive circuit, wherein the first current mirror circuit is a cascode current mirror circuit.
In an exemplary embodiment, the first current mirror circuit includes a first resistor, a first front-end transistor, a plurality of first back-end transistors, a second front-end transistor, and a plurality of second back-end transistors, wherein a first end of the first resistor is connected to a control end of the first front-end transistor and a control end of the plurality of first back-end transistors, a second end of the first resistor is connected to a first end of the first front-end transistor, the first current is input through the first end of the first resistor, and a second end of the first front-end transistor is connected to a first end of the second front-end transistor; the control terminal of the second front-end transistor is connected with the control terminal of the plurality of second back-end transistors, the first terminal of one of the plurality of first back-end transistors is connected with the main body driving circuit, the first terminal of the first back-end transistor except one of the plurality of first back-end transistors is connected with the second current mirror circuit, the second terminal of each first back-end transistor is connected with the first terminal of the second back-end transistor, the second terminal of the plurality of second back-end transistors is connected with the ground terminal, the switching circuit comprises a first switching transistor and a second switching transistor, the control terminal of the first switching transistor is configured to receive a first signal, the first terminal of the first switching transistor is connected with the first terminal of the first front-end transistor, the second terminal of the first switching transistor is connected with the control terminal of the second front-end transistor, the control terminal of the second switching transistor is configured to receive a second signal, the second signal is opposite to the first signal level, the second end of the second switch transistor is connected with the ground end.
In an exemplary embodiment, the plurality of first back-end transistors includes three first back-end transistors, the plurality of second back-end transistors includes three second back-end transistors, the second current mirror circuit includes three third back-end transistors, control ends of the three third back-end transistors are connected together, wherein first ends of two third back-end transistors are respectively connected with a first end of the first back-end transistor, a first end of one third back-end transistor is connected with a current input end of the main body driving circuit, a first end of one third back-end transistor of the two third back-end transistors is connected with a control end of the one third back-end transistor, and second ends of the three third back-end transistors are connected with a voltage source.
In an exemplary embodiment, the first front-end transistor, the first back-end transistor, the second front-end transistor, the second back-end transistor, the first switching transistor, and the second switching transistor are P-type field effect transistors, and the second current mirror circuit includes a plurality of N-type field effect transistors.
In one exemplary embodiment, the low power LVDS transmitter further includes a voltage source capable of providing a 1.8V voltage output to turn on the respective transistors.
In an exemplary embodiment, the low power LVDS transmitter further includes a common-mode feedback circuit, the common-mode feedback circuit includes a first feedback amplifying circuit and a second feedback amplifying circuit, the first feedback amplifying circuit is connected to an output end of the main body driving circuit, and is configured to detect a common-mode voltage of a differential signal output by the main body driving circuit, amplify a voltage difference between the common-mode voltage and a reference voltage, and output the amplified common-mode voltage, the input end of the second feedback amplifying circuit is connected to an output end of the first feedback amplifying circuit, so as to receive and amplify the voltage difference amplified by the first feedback amplifying circuit, and the output end of the second feedback amplifying circuit is connected to a current input end of the main body driving circuit, so as to adjust the common-mode voltage of the differential signal output by the main body driving circuit.
In an exemplary embodiment, the second feedback amplifying circuit includes an amplifying transistor, the amplifying transistor has a control terminal, a first terminal and a second terminal, the control terminal of the amplifying transistor is used as an input terminal of the second feedback amplifying circuit, the first terminal of the amplifying transistor is used as an output terminal of the second feedback amplifying circuit, and the second terminal of the amplifying transistor is connected to a voltage source.
In an exemplary embodiment, the common mode feedback circuit further includes a miller compensation circuit, the miller compensation circuit includes a miller compensation capacitor and a zeroing resistor, one end of the miller compensation capacitor is connected to the output end of the first feedback amplifying circuit, the other end of the miller compensation capacitor is connected to one end of the zeroing resistor, and the other end of the zeroing resistor is connected to the current input end of the main body driving circuit.
In an exemplary embodiment, the low power LVDS transmitter further includes a single-ended to differential circuit and a pre-driver circuit, wherein the single-ended to differential circuit is configured to convert an input signal into a differential signal output, an input terminal of the pre-driver circuit is connected to an output terminal of the single-ended to differential circuit, and an output terminal of the pre-driver circuit is connected to the main body driver circuit.
The technical scheme provided by the embodiment of the application at least comprises the following beneficial effects:
The low-power-consumption LVDS transmitter disclosed by the application is provided with the switch circuit and the mirror current source, so that the switch circuit is connected with at least one transistor in the mirror current source, and a plurality of transistors in the mirror current source can be selectively controlled to be turned on or off, so that the mirror current source is turned on or off, when the mirror current source is turned on, the mirror current source can output current to the main body driving circuit, so that the main body driving circuit can generate differential signals, thereby realizing data transmission, and when the mirror current source is turned off, because no input current exists, the main body driving circuit is also turned off, and when the data transmission is not needed through the LVDS transmitter, the mirror current source and the main body driving circuit are turned off, thereby reducing the power consumption of the LVDS transmitter, and meanwhile, the normal operation of other functional modules in the circuit is not influenced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 shows a block diagram of a low power LVDS transmitter according to an embodiment of the application.
Fig. 2 is a schematic circuit diagram of a portion of a low power LVDS transmitter according to an embodiment of the application.
Fig. 3 is a schematic diagram illustrating a part of a circuit and a receiving end of a low power LVDS transmitter according to an embodiment of the application.
Fig. 4 shows a schematic circuit diagram of a comparison amplifier according to a first embodiment of the present application.
Fig. 5 shows an output eye diagram of a low power LVDS transmitter according to an embodiment of the application.
The reference numerals are explained as follows:
100. A low power LVDS transmitter; 101, a single-ended differential circuit; 102, a pre-driving circuit; 103, a transmitting end circuit, 1031, a mirror current source, 10311, a first current mirror circuit, R1, a first resistor, M3, a first front end transistor, M5/M7/M9, a first back end transistor, M4, a second front end transistor, M6/M8/M10, a second back end transistor, 10312, a second current mirror circuit, M11/M12/M13, a third back end transistor, 1032, a main driving circuit, M14, a first transistor, M15, a second transistor, M16, a third transistor, M17, a fourth transistor, I1, a tail current source, R load, a load resistor, 1033, a switching circuit, M1, a first switching transistor, M2, a second switching transistor, 104, a common mode feedback circuit, 1041, a first feedback amplifying circuit, 10411, a voltage detecting circuit, R2, a first voltage dividing resistor, R3, a second dividing resistor, 10412, a comparison amplifier, M19, a fifth transistor, M20, M21, a fourth transistor, I1, a tail current source, R load, a load resistor, 1033, a switching circuit, M1, a first feedback amplifying circuit, a first feedback circuit, a third feedback circuit, a fourth transistor, a feedback circuit, a third transistor, a fourth transistor, a capacitor, and a capacitor.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many different forms and should not be construed as limited to the examples set forth herein, but rather, the exemplary embodiments are provided so that the description of the present application will be more complete and thorough, and will fully convey the concept of the exemplary embodiments to those skilled in the art.
In the description of the present application, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining ordinal numbers such as "first," "second," "third," etc., may explicitly or implicitly include one or more features.
In the related art, an LVDS transmitter generally includes a current source and a body driving circuit, an input current is supplied to the body driving circuit through the current source, and the body driving circuit generates a differential signal based on the input current, thereby implementing data transmission. However, in the prior art, whether the differential signal is output through the main body driving circuit to realize data transmission or not, the main body driving circuit and the current source are kept in the working state, so that the power consumption of the LVDS transmitter is high. Therefore, the application provides a low-power-consumption LVDS transmitter, which can turn off a current source and a main body driving circuit when data transmission through the LVDS transmitter is not needed, so that the power consumption of the LVDS transmitter is reduced.
Fig. 1 shows a block diagram of a low power LVDS transmitter according to an embodiment of the application, and fig. 2 shows a schematic diagram of a part of a circuit of the low power LVDS transmitter according to the embodiment of the application.
Referring to fig. 1, the low power LVDS transmitter 100 mainly includes a single-ended differential circuit 101, a pre-driving circuit 102, a transmitting-end circuit 103, and a common-mode feedback circuit 104.
The input end of the single-ended to differential circuit 101 receives a single-ended input signal tx_datain, the output end of the single-ended to differential circuit 101 is connected to the input end of the pre-driving circuit 102, and the single-ended to differential circuit 101 is configured to convert the single-ended input signal tx_datain into a differential signal and output the differential signal to the pre-driving circuit 102.
The single-ended to differential circuit 101 may be any conventional single-ended to differential circuit, so long as it can convert a single-ended input signal into a differential signal for output, and therefore will not be described here.
As described above, the input terminal of the pre-driving circuit 102 is connected to the output terminal of the single-ended differential circuit 101, and the output terminal of the pre-driving circuit 102 is connected to the transmitting terminal circuit 103. The pre-driving circuit 102 is configured to drive and convert the differential signal input by the single-ended differential circuit 101, and output the differential signal to the transmitting end circuit 103, so that the transmission rate of the signal can be increased, and high-speed transmission of the signal is ensured.
Note that, the pre-driving circuit 102 may be any pre-driving circuit in the prior art, as long as the signal transmission rate of the LVDS transmitter 100 can be improved, and thus will not be described here. In an embodiment of the present application, the LVDS transmitter 100 can transmit 1Gbps data signals, and the signal transmission rate is greatly improved compared to the conventional LVDS technology.
Of course, in some embodiments, the pre-drive circuit 102 and/or the single-ended differential circuit 101 may not be provided.
Referring to fig. 2, the transmitting-side circuit 103 mainly includes a mirror current source 1031, a main body driving circuit 1032, a switching circuit 1033, and the like.
The current input terminal of the mirror current source 1031 is connected to a current output circuit (not shown in the figure) to receive the first current. The current output circuit may include a bandgap circuit and a current calibration circuit, and outputs a bandgap reference through the bandgap circuit, performs current calibration on the bandgap reference through the current calibration circuit, and outputs a precise current ibias_drv (first current) independent of temperature and voltage to the image current source 1031. The current output terminal of the current mirror 1031 is connected to the current input terminal of the body driving circuit 1032, and the current mirror 1031 is configured to convert the input first current ibias_drv into the second current Iload and output the second current Iload to the current input terminal of the body driving circuit 1032.
In one embodiment of the application, the mirrored current source 1031 includes a first current mirror circuit 10311 and a second current mirror circuit 10312.
The first current mirror circuit 10311 is configured to receive an input first current ibias_drv, and the first current mirror circuit 10311 is a cascode current mirror circuit. In this embodiment, the first current mirror circuit 10311 is configured as a cascode current mirror circuit (cascode current mirror), which has a large output impedance and more accurate mirror current, so that the mirror current source 1031 can accurately convert to the required second current Iload based on the first current ibias_drv.
In one embodiment of the present application, as shown in fig. 2, the first current mirror circuit 10311 includes a first resistor R1, a first front-end transistor M3, three first back-end transistors (respectively labeled M5, M7, and M9), a second front-end transistor M4, and three second back-end transistors (respectively labeled M6, M8, and M10).
The first end of the first resistor R1 is connected to the control end of the first front-end transistor M3 and the control ends of the first back-end transistors M5, M7, and M9, the second end of the first resistor R1 is connected to the first end of the first front-end transistor M3, and the first end of the first resistor R1 is used as the current input end of the mirror current source 1031, and is connected to the aforementioned current output circuit, that is, the first current ibias_drv is input through the first end of the first resistor R1. The second end of the first front-end transistor M3 is connected to the first end of the second front-end transistor M4, the control end of the second front-end transistor M4 is connected to the control ends of the second back-end transistors M6, M8, M10, and the second end of the second front-end transistor M4 is connected to the ground. The first end of the first back-end transistor M5 and the first end of the first back-end transistor M7 are connected to the second current mirror circuit 10312, the first end of the first back-end transistor M9 is connected to the main body driving circuit 1032, the second end of the first back-end transistor M5 is connected to the first end of the second back-end transistor M6, the second end of the first back-end transistor M7 is connected to the first end of the second back-end transistor M8, the second end of the first back-end transistor M9 is connected to the first end of the second back-end transistor M10, and the second ends of the second back-end transistors M6, M8, M10 are connected to the ground.
In the embodiment shown in fig. 2, the first front-end transistor M3, the first back-end transistor M5, the first back-end transistor M7, the first back-end transistor M9, the second front-end transistor M4, the second back-end transistor M6, the second front-end transistor M8, and the second front-end transistor M10 are P-type field effect transistors, the control end of the transistor is the gate of the transistor, the first end of the transistor is the drain of the transistor, and the second end of the transistor is the source of the transistor. Of course, transistors other than field effect transistors may be used instead.
The second current mirror circuit 10312 is connected to the first current mirror circuit 10311 and the current input terminal of the body driving circuit 1032, and the second current mirror circuit 10312 is configured to output the second current Iload to the current input terminal of the body driving circuit 1032.
In one embodiment of the application, the second current mirror circuit 10312 includes three third back-end transistors (labeled M11, M12, M13, respectively). The control terminals of the three third back-end transistors M11, M12, M13 are connected together, wherein the first terminal of the third back-end transistor M11 is connected to the first terminal of the first back-end transistor M5, the first terminal of the third back-end transistor M12 is connected to the first terminal of the first back-end transistor M7, and the first terminal of the third back-end transistor M13 is connected to the current input terminal of the main body driving circuit 1032, that is, the first terminal of the third back-end transistor M13 serves as the current output terminal of the mirror current source 1031 to output the second current Iload to the main body driving circuit 1032. The control terminal of the third back-end transistor M11 is connected to the first terminal thereof, so that the control terminal of the third back-end transistor M11 is connected to the first terminal of the first back-end transistor M5. The second terminals of the third back-end transistors M11, M12, M13 are connected to the voltage source VDD.
In the embodiment shown in fig. 2, the third back-end transistor M11, the third back-end transistor M12, and the third back-end transistor M13 are all N-type field effect transistors, the control end of the transistor is the gate of the transistor, the first end of the transistor is the drain of the transistor, and the second end of the transistor is the source of the transistor. Of course, transistors other than field effect transistors may be used instead.
When the first front-end transistor M3 is turned on, the first current ibias_drv reaches the first front-end transistor M3 through the first resistor R1, the control terminal of the first front-end transistor M3 generates the voltage vbn1, and since the control terminals of the first front-end transistor M3, the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 are connected together, the control terminals of the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 generate the same voltage vbn1 as the control terminal of the first front-end transistor M3, and the first front-end transistor M3, the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 are all turned on. If the second front-end transistor M4 is also turned on at this time, the control terminal of the second front-end transistor M4 generates a voltage vbn2, and since the control terminals of the second front-end transistor M4, the second back-end transistor M6, the second back-end transistor M8, and the second back-end transistor M10 are connected together, the control terminals of the second back-end transistor M6, the second back-end transistor M8, and the second back-end transistor M10 generate the same voltage vbn2 as the control terminal of the second front-end transistor M4, and the second back-end transistor M6, the second back-end transistor M8, and the second back-end transistor M10 are turned on. Since the first terminal of the third back-end transistor M11 is connected to the first terminal of the first back-end transistor M5 and the control terminal of the third back-end transistor M11 is connected to the first terminal thereof, a voltage vbp is generated at the control terminal of the third back-end transistor M11, and since the control terminals of the third back-end transistor M11, the third back-end transistor M12, and the third back-end transistor M13 are connected together, the control terminals of the third back-end transistor M12, and the third back-end transistor M13 generate the same voltage vbp as the control terminal of the third back-end transistor M11, and the third back-end transistor M11, the third back-end transistor M12, and the third back-end transistor M13 are all turned on. At this time, the mirrored current source 1031 can convert the first current ibias_drv into the second current Iload output.
Wherein the second current Iload is determined based on the first current ibias_drv and parameters of the respective transistors M3-M13 in the mirrored current source 1031. In one embodiment of the present application, the mirror current source 1031 mirrors and amplifies the first current ibias_drv by 14 times to obtain the second current Iload and outputs the second current Iload, and the first current ibias_drv is 17.5ua to 35ua, and correspondingly, the second current Iload is 2.45ma to 4.90ma.
On the contrary, when the first front-end transistor M3 is turned off, the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 are all turned off, and if the control terminal voltage of the second front-end transistor M4 is at a low level at this time, the second front-end transistor M4, the second back-end transistor M6, the second back-end transistor M8, and the second back-end transistor M10 are turned off, and further, because the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 are turned off at this time, the third back-end transistor M11, the third back-end transistor M12, and the third back-end transistor M13 are also turned off. At this time, the mirror current source 1031 is turned off, and the mirror current source 1031 outputs no current.
Referring again to fig. 2, the switching circuit 1033 is coupled to at least one transistor in the mirrored current source 1031 and is configured to selectively control the at least one transistor in the mirrored current source 1031 to be turned on or off, thereby controlling all transistors in the mirrored current source 1031 to be turned on or off.
In one embodiment of the present application, the switching circuit 1033 includes a first switching transistor M1 and a second switching transistor M2, wherein the control terminal of the first switching transistor M1 is configured to receive the first signal pwd_b, the first terminal of the first switching transistor M1 is connected to the first terminal of the first front-end transistor M3, the second terminal of the first switching transistor M1 is connected to the control terminal of the second front-end transistor M4, the control terminal of the second switching transistor M2 is configured to receive the second signal pwd, the second signal pwd is opposite to the first signal pwd_b, the first terminal of the second switching transistor M2 is connected to the control terminal of the second front-end transistor M4, and the second terminal of the second switching transistor M2 is connected to the ground.
When the second signal pwd is low, the first switching transistor M1 is turned on, the second switching transistor M2 is turned off, the first current ibias_drv can be input through the first resistor R1, the first front-end transistor M3, the first back-end transistor M5, the first back-end transistor M7, the first back-end transistor M9 generate the gate voltage to be turned on, the second front-end transistor M4, the second back-end transistor M6, the second back-end transistor M8, the second back-end transistor M10 generate the gate voltage to be turned on, and the third back-end transistor M11, the third back-end transistor M12, the third back-end transistor M13 generate the gate voltage to be turned on, and at this time, the whole mirror current source 1031 can convert the first current ibias_drv into the second current Iload to be output.
On the contrary, when the second signal pwd is at a high level, the first switch transistor pwd_b is at a low level, at this time, the first switch transistor M1 is turned off, the first current ibias_drv cannot be input through the first resistor R1, the first front-end transistor M3, the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 are turned off, at the same time, the second switch transistor M2 is turned on, the gate voltage thereof is the ground voltage, so that the second front-end transistor M4, the second back-end transistor M6, the second back-end transistor M8, and the second back-end transistor M10 are turned off, and the third back-end transistor M11, the third back-end transistor M12, and the third back-end transistor M13 are also turned off, at this time, the entire mirror current source 1031 is turned off, and no current is output.
In the embodiment shown in fig. 2, the first switching transistor M1 and the second switching transistor M2 are P-type field effect transistors, the control end of the transistor is the gate of the transistor, the first end of the transistor is the drain of the transistor, and the second end of the transistor is the source of the transistor. Of course, transistors other than field effect transistors may be used instead.
In the embodiment shown in fig. 2, the switching circuit 1033 includes the first switching transistor M1 and the second switching transistor M2, and the first signal pwd_b received by the control terminal of the first switching transistor M1 is configured to be opposite to the second signal pwd received by the control terminal of the second switching transistor M2, so that the mirror current source 1031 can be reliably controlled to be turned on or off.
The main body driving circuit 1032 is connected to the mirror current source 1031, specifically, to the current output terminal of the second current mirror circuit 1031, that is, the drain of the third back-end transistor M13. The body driving circuit 1032 is configured to generate a differential signal based on the second current Iload output from the mirror current source 1031.
In one embodiment of the present application, as shown in fig. 3, the body driving circuit 1032 includes a first transistor M14, a second transistor M15, a third transistor M16, a fourth transistor M17, and a tail current source I1.
The control terminals of the first transistor M14 and the third transistor M16 are connected to the positive signal input terminal vin+, the control terminals of the second transistor M15 and the fourth transistor M17 are connected to the negative signal input terminal Vin-, and the first transistor M14, the second transistor M15, the third transistor M16 and the fourth transistor M17 are controlled to be turned on or off by the control signal input to the signal input terminal vin+, the signal input terminal Vin-.
The first transistor M14, the second transistor M15, the third transistor M16, and the fourth transistor M17 are all linear switching transistors, the first terminal of the first transistor M14 is connected to the first terminal of the third transistor M16, the first terminal of the second transistor M15 is connected to the first terminal of the fourth transistor M17, the second terminal of the first transistor M14 and the second terminal of the second transistor M15 are used as current input terminals of the body driving circuit 1032, are connected to the mirror current source 1031, input a constant second current Iload through the mirror current source 1031, and the second terminal of the third transistor M16 and the second terminal of the fourth transistor M17 are connected to the tail current source I1, and are connected to the ground terminal through the tail current source I1.
Meanwhile, the current input end of the main body driving circuit 1032, that is, the second end of the first transistor M14 and the second end of the second transistor M15 are further connected to the output end of the common mode feedback circuit 104, so as to receive the adjustment current I CM output by the common mode feedback circuit 104, and the second current Iload input by the mirror current source 1031 and the adjustment current I CM are overlapped to be used as the supply current of the main body driving circuit 1032. When the supply current changes, the common mode voltage V out,cm of the differential signal output by the main body driving circuit 1032 changes accordingly.
The connection node of the first end of the first transistor M14 and the first end of the third transistor M16 is connected to one end of the load resistor R load, the other end of the load resistor R load is connected to the connection node of the first end of the second transistor M15 and the first end of the fourth transistor M17, two ends of the load resistor R load respectively correspond to one differential output end of the main body driving circuit 1032, and the voltage at two ends of the load resistor R load is the differential signal voltage swing output by the main body driving circuit 1032. The load resistor R load is used as a matching impedance of the main body driving circuit 1032, and the load resistor R load is connected in parallel to the differential signal receiving terminal.
When the second transistor M15 and the third transistor M16 are turned on and the first transistor M14 and the fourth transistor M17 are turned off, the power supply flows through the second transistor M15 to the load resistor R load, passes through the load resistor R load and returns to the third transistor M16, and finally goes to the ground through the third transistor M16, so that the power supply generates a corresponding voltage drop across the load resistor R load. When the second transistor M15 and the third transistor M16 are turned off and the first transistor M14 and the fourth transistor M17 are turned on, the power supply flows through the first transistor M14 to the load resistor R load, passes through the load resistor R load and returns to the fourth transistor M17, and finally flows through the fourth transistor M17 to the ground, so that the power supply current also generates a corresponding voltage drop across the load resistor R load. At this time, the voltage drop generated across the load resistor R load is opposite to the direction when the second transistor M15 and the third transistor M16 are turned on and the first transistor M14 and the fourth transistor M17 are turned off. That is, if the output of the main body driving circuit 1032 is at the high level, the outputs of the second transistor M15 and the third transistor M16 are on and the outputs of the first transistor M14 and the fourth transistor M17 are off, and if the output of the main body driving circuit 1032 is at the low level, the outputs of the second transistor M15 and the third transistor M16 are on and the outputs of the main body driving circuit 1032 are at the high level, when the first transistor M14 and the fourth transistor M17 are off. The main body driving circuit 1032 utilizes voltage swing to perform high-speed differential transmission.
In one embodiment of the present application, the resistance of the load resistor R load is 100deg.C, and the voltage drop generated by the supply current on the load resistor R load is the product of the supply current and 100deg.C. For example, the first current ibias_drv is 17.5ua to 35ua, the mirror current source 1031 mirrors and amplifies the first current ibias_drv by 14 times, and correspondingly, the second current Iload is 2.45ma to 4.90ma, so that the voltage swing range outputted by the main body driving circuit 1032 is V OD =490 mv to 480 mv.
It should be noted that the tail current source I1 may be any current source structure, for example, the tail current source I1 is composed of two field effect transistors.
Note that the main body driving circuit 1032 is not limited to the configuration shown in fig. 3, and in other embodiments, the main body driving circuit 1032 may have any configuration as long as generation and output of a differential signal can be achieved.
In the embodiment shown in fig. 3, the first transistor M14, the second transistor M15, the third transistor M16, and the fourth transistor M17 are all field effect transistors, the control end is the gate of the transistor, the first end is the drain of the transistor, and the second end is the source of the transistor. The first transistor M14 and the second transistor M15 are N-type field effect transistors, the third transistor M16 and the fourth transistor M17 are P-type field effect transistors, and of course, other transistors other than field effect transistors may be used instead.
Referring to fig. 3, the common mode feedback circuit 104 includes a first feedback amplifying circuit 1041 and a second feedback amplifying circuit 1042. The first feedback amplifying circuit 1041 is connected to an output end of the main body driving circuit 1032, and is configured to detect a common-mode voltage V out,cm of the differential signal output by the main body driving circuit 1032, amplify a voltage difference between the common-mode voltage V out,cm and the reference voltage V cm,ref, and output the amplified voltage difference. The reference voltage V cm,ref may be generated by a bandgap circuit (not shown).
The first feedback amplifying circuit 1041 includes a voltage detecting circuit 10411 and a comparing amplifier 10412.
The voltage detection circuit 10411 is connected between two differential output terminals of the main body driving circuit 1032, that is, the voltage detection circuit 10411 is connected in parallel to two ends of the load resistor R load, and the voltage detection circuit 10411 is used for detecting the common mode voltage V out,cm of the differential signal output by the main body driving circuit 1032.
In an embodiment of the present application, the voltage detection circuit 10411 includes a first voltage dividing resistor R2 and a second voltage dividing resistor R3, wherein one end of the first voltage dividing resistor R2 is connected to one differential output end of the main body driving circuit 1032, that is, one end of the first voltage dividing resistor R2 is connected to one end of the load resistor R load, the other end of the first voltage dividing resistor R2 is connected to one end of the second voltage dividing resistor R3, and the other end of the second voltage dividing resistor R3 is connected to the other differential output end of the main body driving circuit 1032, that is, the other end of the second voltage dividing resistor R3 is connected to the other end of the load resistor R load.
In this embodiment, the voltage detection circuit 10411 is provided to include the first voltage dividing resistor R2 and the second voltage dividing resistor R3, and the circuit structure of the voltage detection circuit 10411 is simple.
The first voltage dividing resistor R2 and the second voltage dividing resistor R3 are resistors with large resistance values, so that the supply current entirely flows through the load resistor R load.
The comparison amplifier 10412 has a first input end, a second input end and an output end, the first input end of the comparison amplifier 10412 is connected to the voltage detection circuit 10411 to receive the common mode voltage V out,cm detected by the voltage detection circuit 10411, the second input end of the comparison amplifier 10412 is used for receiving the reference voltage V cm,ref, and the output end of the comparison amplifier 10412 is connected to the input end of the second feedback amplification circuit 1042. The comparison amplifier 10412 compares the voltage difference between the common-mode voltage V out,cm and the reference voltage V cm,ref, amplifies the voltage difference between the common-mode voltage V out,cm and the reference voltage V cm,ref, and outputs the amplified voltage difference to the second feedback amplifying circuit 1042.
In the embodiment in which the voltage detection circuit 10411 includes the first voltage dividing resistor R2 and the second voltage dividing resistor R3, the first input terminal of the comparison amplifier 10412 is connected to the phase connection node of the first voltage dividing resistor R2 and the second voltage dividing resistor R3, and the common mode voltage V out,cm of the differential signal output by the main body driving circuit 1032 is obtained by detecting the voltage division of the resistors.
In this embodiment, the first feedback amplifying circuit 1041 includes a voltage detecting circuit 10411 and a comparing amplifier 10412, the common-mode voltage V out,cm of the differential signal output by the main driving circuit 1032 is detected by the voltage detecting circuit 10411, the voltage difference between the common-mode voltage V out,cm and the reference voltage V cm,ref is compared by the comparing amplifier 10412, and the voltage difference between the common-mode voltage V out,cm and the reference voltage V cm,ref is amplified and then output to the second feedback amplifying circuit 1042.
Fig. 4 shows a schematic circuit diagram of a comparison amplifier according to a first embodiment of the present application.
Referring to fig. 4, in one embodiment of the present application, the comparison amplifier 10412 includes a fifth transistor M19, a sixth transistor M20, a seventh transistor M21, an eighth transistor M22, and a ninth transistor M23.
The control terminal of the fifth transistor M19 is used as the first input terminal of the comparison amplifier 10412, receives the common-mode voltage V out,cm obtained by the voltage detection circuit 10411, the first terminal of the fifth transistor M19 is connected to the second terminal of the seventh transistor M21, and the second terminal of the fifth transistor M19 is connected to the first terminal of the ninth transistor M23.
The control terminal of the sixth transistor M20 is used as the second input terminal of the comparison amplifier 10412, receives the reference voltage B cm,, the first terminal of the sixth transistor M20 is connected to the second terminal of the eighth transistor M22, the connection node between the first terminal of the sixth transistor M20 and the second terminal of the eighth transistor M22 is used as the output terminal of the comparison amplifier 10412, the amplified voltage difference V fb is output, and the second terminal of the sixth transistor M20 is connected to the first terminal of the ninth transistor M23.
The control terminal of the seventh transistor M21 is connected to the control terminal of the eighth transistor M22, and the connection node of the control terminal of the seventh transistor M21 and the control terminal of the eighth transistor M22 and the connection node of the first terminal of the fifth transistor M19 and the second terminal of the seventh transistor M21 are connected, the first terminal of the seventh transistor M21 and the first terminal of the eighth transistor M22 are connected to the voltage source VDD, and the voltage source VDD is used to supply voltages to the respective transistors in the comparison amplifier 10412, so that the respective transistors in the comparison amplifier 10412 can be turned on.
The ninth transistor M23 serves as a tail current source, a first terminal of the ninth transistor M23 is connected to the second terminals of the fifth transistor M19 and the sixth transistor M20, a second terminal of the ninth transistor M23 is connected to the ground terminal, and a control terminal of the ninth transistor M23 receives the input voltage Vb.
In the embodiment shown in fig. 4, the comparison amplifier 10412 adopts a simple five-tube operational amplifier, which has a simple structure and a high output swing, and facilitates the introduction of the output voltage into the body driving circuit 1032.
In the embodiment shown in fig. 4, the fifth transistor M19, the sixth transistor M20, the seventh transistor M21, the eighth transistor M22, and the ninth transistor M23 are all field effect transistors, the control end is the gate of the transistor, the first end is the drain of the transistor, and the second end is the source of the transistor. The seventh transistor M21 and the eighth transistor M22 are P-type field effect transistors, the fifth transistor M19, the sixth transistor M20 and the ninth transistor M23 are N-type field effect transistors, and of course, other transistors than field effect transistors may be used instead.
Referring to fig. 3 again, an input end of the second feedback amplifying circuit 1042 is connected to an output end of the first feedback amplifying circuit 1041 to receive and amplify the voltage difference amplified by the first feedback amplifying circuit 1041, and an output end of the second feedback amplifying circuit 1042 is connected to a current input end of the main body driving circuit 1032 to adjust a common mode voltage of the differential signal output by the main body driving circuit 1032.
In an embodiment of the application, the second feedback amplifying circuit 1042 includes an amplifying transistor M18, the amplifying transistor M18 has a control end, a first end and a second end, wherein the control end of the amplifying transistor M18 is used as an input end of the second feedback amplifying circuit 1042 for receiving the voltage difference V fb, the first end of the amplifying transistor M18 is used as an output end of the second feedback amplifying circuit 1042 and is connected to the current input end of the main driving circuit 1032, the second end of the amplifying transistor M18 is connected to a voltage source VDD, and the voltage source VDD is used to provide a voltage to the amplifying transistor M18, so that the amplifying transistor M18 can be turned on.
In this embodiment, the amplifying transistor M18 is adopted as the second feedback amplifying circuit 1042, and the second feedback amplifying circuit 1042 has a simple structure. Of course, in other embodiments, the second feedback amplifying circuit 1042 may have other structures.
In detail, the amplifying transistor M18 is an N-type field effect transistor, the control end of the amplifying transistor M18 is a gate of the amplifying transistor M18, the first end of the amplifying transistor M18 is a drain of the amplifying transistor M18, and the second end of the amplifying transistor M18 is a source of the amplifying transistor M18.
When the common mode voltage V out,cm is higher than the reference voltage V cm,ref, the voltage difference V fb outputted by the first feedback amplifying circuit 1041 increases, the gate voltage V G of the amplifying transistor M18 increases, and the source of the amplifying transistor M18 is connected to the voltage source VDD, that is, the source voltage of the amplifying transistor M18 is VDD, and when the gate voltage V G increases, V Gs decreases, the output current of the amplifying transistor M18 decreases (the relationship between the output current of the transistor and V Gs is that V Gs decreases, the output current is small, and the output current is large as V GS increases), that is, the adjustment current I CM decreases, and thus the supply current of the main body driving circuit 1032 decreases, thereby decreasing the common mode level V out,cm. similarly, when the common mode voltage V out,cm is lower than the reference voltage V cm,ref, the voltage difference V fb outputted by the first feedback amplifying circuit 1041 decreases, the gate voltage V G of the amplifying transistor M18 decreases, V GS increases, so that the output current of the amplifying transistor M18 increases, that is, the adjustment current I CM increases, and the supply current of the body driving circuit 1032 increases, thereby increasing the common mode level V out,cm. That is, the common mode level V out,cm is adjusted by adjusting the output current I CM of the amplifying transistor M18.
In an embodiment of the present application, the common mode feedback circuit 104 further includes a miller compensation circuit 1043, wherein the miller compensation circuit 1043 is connected between the output terminal of the first feedback amplifying circuit 1041 and the current input terminal of the main body driving circuit 1032. The phase margin of the common mode feedback circuit 104 is improved by the miller compensation circuit 1043.
In an embodiment of the present application, the miller compensation circuit 1043 includes a miller compensation capacitor Cc and a zeroing resistor Rc, one end of the miller compensation capacitor Cc is connected to the output end of the first feedback amplifying circuit 1041, the other end of the miller compensation capacitor Cc is connected to one end of the zeroing resistor Rc, and the other end of the zeroing resistor Rc is connected to the current input end of the main body driving circuit 1032.
Of course, other configurations of the miller compensation circuit 1043 are also possible, for example, in some embodiments, the miller compensation circuit 1043 includes only a miller compensation capacitor Cc, two ends of the miller compensation capacitor Cc are respectively connected to the output end of the first feedback amplifying circuit 1041 and the current input end of the main body driving circuit 1032, and for example, in other embodiments, the miller compensation circuit 1043 includes two miller compensation capacitors and a zero-setting resistor, and the zero-setting resistor is connected in series between the two miller compensation capacitors.
In an embodiment, the miller compensation capacitor Cc is realized by the MOM capacitor and the MOS transistor together, that is, the MOM capacitor and the MOS transistor are stacked together, and a metal layer structure is provided by using the MOS transistor, so that a partial capacitance is provided, and the occupied area of the miller compensation capacitor Cc can be reduced.
In the foregoing embodiment, the first feedback amplifying circuit 1041 detects the common-mode voltage V out,cm of the differential signal output by the main body driving circuit 1032, compares the common-mode voltage V out,cm with the reference voltage V cm,ref, obtains the voltage difference between the common-mode voltage V out,cm and the reference voltage V cm,ref, amplifies the voltage difference, and outputs the amplified voltage difference, and the second feedback amplifying circuit 1042 amplifies the voltage difference amplified by the first feedback amplifying circuit 1041 and feeds back the amplified voltage difference to the main body driving circuit 1032, specifically, adjusts the adjusting current I CM, thereby adjusting the current size of the input main body driving circuit 1032, and further adjusting the common-mode voltage V out,cm of the differential signal output by the main body driving circuit 1032, so as to stabilize the common-mode voltage and reduce the signal jitter. By adopting the two-stage feedback amplifying circuit, the loop gain of the whole common mode feedback circuit 104 is higher, and meanwhile, the phase margin of the common mode feedback circuit 104 is improved through the miller compensating circuit 1043, so that the stability of the common mode feedback circuit 104 is improved, the output waveform is not greatly deviated when the whole low-power LVDS transmitter 100 transmits high-rate signals, and the accuracy of the output signals is improved.
In one embodiment of the present application, the voltage source VDD provides a 1.8V voltage output to turn on the various transistors in the LVDS transmitter 100 so that the various transistors can operate properly. Compared with the existing mode of adopting a 3.3V voltage source, the power consumption of the whole circuit can be saved.
In this embodiment, each transistor used can be normally turned on at a voltage of 1.8V.
The applicant has also verified, based on an embodiment of the present application, that during the simulation, a pseudo-random code generator is used to generate a random signal, and considering a series of parasitic effects of the entire LVDS transmitter 100 and transmission loss, the differential signal amplitude of 1Gbps will have a certain attenuation during transmission, so that it is assumed that the output load capacitance is 2.5pF, and the obtained output eye diagram is shown in fig. 5. In fig. 5, (a) is an output eye diagram corresponding to the case where the first current ibias_drv is the minimum value (i.e., 17.5 uA), and (b) is an output eye diagram corresponding to the case where the first current ibias_drv is the maximum value (i.e., 35 uA).
As shown in fig. 5 (a), when the first current ibias_drv is 17.5uA, the output eye height of the LVDS transmitter 100 is 463.8mV, the peak-to-peak jitter is 21ps, and as shown in fig. 5 (b), when the first current ibias_drv is 35uA, the output eye height of the LVDS transmitter 100 is 813.8mV, and the peak-to-peak jitter is 23ps. Finally, the overall power consumption of the LVDS transmitter is less than 12mW. That is, through practical simulation verification, when the output load capacitance of the LVDS transmitter 100 is 2.5pF under different process angles, power supply voltages and temperatures, the data transmission rate can reach 1Gbps, the LVDS transmitter can be suitable for signal transmission under the requirement of high transmission rate, the output differential signal eye height is 490mV-980mV, the output swing amplitude is high, the peak-to-peak jitter is less than 23ps, the highest static power consumption is 12mW, and the high-speed low-power transmission of data can be effectively realized.
The technical scheme of the application is compared with the prior art scheme parameters as shown in the following table 1:
List one
In summary, in the low power LVDS transmitter 100 disclosed by the application, the switch circuit 1033 and the mirror current source 1031 are provided, so that the switch circuit 1033 is connected with at least one transistor in the mirror current source 1031, and can selectively control a plurality of transistors in the mirror current source 1031 to be turned on or off, so that the mirror current source 1031 is turned on or off, when the mirror current source 1031 is turned on, a current can be output to the main body driving circuit 1032 through the mirror current source 1031, so that the main body driving circuit 1032 can generate a differential signal, and data transmission is realized, when the mirror current source 1031 is turned off, because no input current exists, the main body driving circuit 1032 is also turned off, and when the LVDS transmitter 100 is not required to transmit data, the power consumption of the LVDS transmitter 100 is reduced, and finally, the highest static power consumption can reach below 12mW, and meanwhile, the normal operation of other functional modules in the circuit is not influenced.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310713719.9A CN116760664B (en) | 2023-06-15 | 2023-06-15 | Low-power LVDS transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310713719.9A CN116760664B (en) | 2023-06-15 | 2023-06-15 | Low-power LVDS transmitter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116760664A CN116760664A (en) | 2023-09-15 |
| CN116760664B true CN116760664B (en) | 2025-08-26 |
Family
ID=87956580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310713719.9A Active CN116760664B (en) | 2023-06-15 | 2023-06-15 | Low-power LVDS transmitter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116760664B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119154854B (en) * | 2024-09-04 | 2025-04-25 | 慷智集成电路(上海)有限公司 | Self-biased LVDS drive circuit, serial circuit chip and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101087139A (en) * | 2007-07-10 | 2007-12-12 | 中国人民解放军国防科学技术大学 | LVDS drive circuit for correcting signal swing rate |
| CN102457455A (en) * | 2010-10-26 | 2012-05-16 | 珠海全志科技股份有限公司 | Low-voltage differential signal transmitter |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011209489A (en) * | 2010-03-30 | 2011-10-20 | Renesas Electronics Corp | Display device, differential amplifier circuit, and data line drive method for display device |
| US9362915B1 (en) * | 2014-12-12 | 2016-06-07 | Freescale Semiconductor, Inc. | LVDS with idle state |
-
2023
- 2023-06-15 CN CN202310713719.9A patent/CN116760664B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101087139A (en) * | 2007-07-10 | 2007-12-12 | 中国人民解放军国防科学技术大学 | LVDS drive circuit for correcting signal swing rate |
| CN102457455A (en) * | 2010-10-26 | 2012-05-16 | 珠海全志科技股份有限公司 | Low-voltage differential signal transmitter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116760664A (en) | 2023-09-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7750738B2 (en) | Process, voltage and temperature control for high-speed, low-power fixed and variable gain amplifiers based on MOSFET resistors | |
| US7053712B2 (en) | Method and apparatus for controlling common-mode output voltage in fully differential amplifiers | |
| US6504404B2 (en) | Semiconductor integrated circuit | |
| JP5022789B2 (en) | Signal conversion circuit and rail-to-rail circuit | |
| US6611157B2 (en) | Differential signal output circuit | |
| US20090091389A1 (en) | Lvds receiver circuit | |
| CN116488596A (en) | LVDS receiving circuit and chip with wide input common mode range | |
| CN116760664B (en) | Low-power LVDS transmitter | |
| US11899485B2 (en) | Line driver having adjustable current mirror array | |
| US7023367B1 (en) | Current steering digital to analog converter with improved dynamic linearity | |
| US7795944B2 (en) | Low-offset input circuit including amplifier circuit to correct circuit characteristics to cancel offset of the input circuit | |
| US7403041B2 (en) | Techniques for enabling a 10BT active output impedance line driver using a low power supply | |
| US7642810B2 (en) | Input circuit for semiconductor integrated circuit | |
| US7701284B2 (en) | Line driver capable of automatically adjusting output impedance | |
| CN113507270A (en) | Variable gain amplifier | |
| US20080157847A1 (en) | Dc offset calibration apparatus and method for differential signals | |
| WO2001041301A1 (en) | Differential amplifier | |
| US7612600B2 (en) | DC offset calibration apparatus and method | |
| CN116805874A (en) | Low-voltage differential signal driving circuit and chip with same | |
| US20120193518A1 (en) | Photoreceptor circuit and photocoupler | |
| JP4886725B2 (en) | Transimpedance amplifier circuit | |
| US6300833B1 (en) | DC gain enhancement for operational amplifiers | |
| US8115550B2 (en) | Transmitter | |
| KR102813465B1 (en) | Differential amplifier circuit | |
| TWI747430B (en) | Signal receiving device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |