CN116782697B - Display panel and preparation method thereof - Google Patents
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- CN116782697B CN116782697B CN202310741419.1A CN202310741419A CN116782697B CN 116782697 B CN116782697 B CN 116782697B CN 202310741419 A CN202310741419 A CN 202310741419A CN 116782697 B CN116782697 B CN 116782697B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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Abstract
The application provides a display panel and a preparation method thereof, wherein the method comprises the following steps: providing a lining plate, wherein the lining plate comprises a base plate, an anode and a pixel limiting layer, the anode and the pixel limiting layer are arranged on the base plate, and the pixel limiting layer is provided with a partition structure; the pixel defining layer includes a first pixel bit, a second pixel bit, and a third pixel bit; forming a first buffer layer at the second pixel position and forming a second buffer layer with a thickness larger than that of the first buffer layer at the third pixel position; disposing and patterning a first pixel layer at the pixel defining layer; removing the first pixel layer and the first buffer layer except the first pixel bit; disposing and patterning a second pixel layer at the pixel defining layer; removing the second pixel layer and the second buffer layer except the second pixel bit; disposing and patterning a third pixel layer at the pixel defining layer; and removing the third pixel layer except the third pixel bit. The application solves the problems that the prior display panel is easy to damage the anode when the pixels are patterned or cause display defects to the pixels after the patterning.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a preparation method thereof.
Background
Currently, OLEDs (Organic Light-Emitting Diode), also known as Organic laser display, organic Light Emitting semiconductors, are used to form display devices in many electronic devices. The organic luminescent material of the OLED is deposited by adopting a fine metal mask plate (FINE METAL MASK, FMM), but the manufacturing mode has the defects that the cost is high due to the high price of the FMM, and the resolution is limited to a certain extent. In order to improve resolution and reduce cost, the industry has begun to use photolithography to pattern and manufacture the organic luminescent material layer, but this method needs to deposit and photolithography to pattern the organic luminescent material three times, and each time the organic luminescent material is patterned, the organic luminescent material on the anode needs to be etched cleanly, which can damage the surface of the anode, or leave small particles on the surface of the anode to cause larger display defects when other sub-pixels are evaporated, thereby affecting yield and display effect.
Disclosure of Invention
The embodiment of the application provides a display panel and a preparation method thereof, wherein a buffer layer is arranged on an anode, a pixel layer is manufactured on the buffer layer, and the anode is not directly contacted when the pixel layer is removed, so that the problem that the anode is easily damaged when the pixel is patterned or display defects are caused to the pixel after the patterning of the conventional display panel is solved.
The invention is realized in that a method for manufacturing a display panel comprises the following steps:
Providing a lining plate, wherein the lining plate comprises a base plate with a driving circuit, a plurality of anodes arranged on the base plate at intervals, a pixel limiting layer positioned around the anodes, and a partition structure arranged on the pixel limiting layer; the pixel defining layer includes first, second and third pixel bits spaced apart from each other;
Forming a first buffer layer on the anode corresponding to the second pixel position, and forming a second buffer layer on the anode corresponding to the third pixel position, wherein the thickness of the second buffer layer is larger than that of the first buffer layer;
disposing and patterning a first pixel layer at the pixel defining layer;
removing the first pixel layer and the first buffer layer corresponding to the second pixel bit and the third pixel bit;
Disposing and patterning a second pixel layer at the pixel defining layer;
removing the second pixel layer and the second buffer layer corresponding to the first pixel bit and the third pixel bit;
disposing and patterning a third pixel layer at the pixel defining layer;
And removing the third pixel layer corresponding to the first pixel bit and the second pixel bit.
In one embodiment, the difference in thickness of the second buffer layer and the first buffer layer is greater than or equal to one-fourth of the thickness of the first buffer layer and less than or equal to the thickness of the first buffer layer.
In one embodiment, the disposing and patterning the first pixel layer in the pixel defining layer includes:
a first pixel layer is arranged on the pixel limiting layer, so that the anode, the partition structure, the first buffer layer and the second buffer layer are covered by the first pixel layer;
and patterning the first pixel layer to form a first pixel positioned at the first pixel position.
In one embodiment, the removing the first pixel layer corresponding to the second pixel bit and the third pixel bit, and the first buffer layer, includes:
forming a first resist layer at the first pixel;
Removing the first pixel layer corresponding to the second pixel bit and the third pixel bit;
removing the first buffer layer;
removing the first resist layer; wherein the first resist layer and the second buffer layer are different in material.
In one embodiment, the disposing and patterning the second pixel layer in the pixel defining layer includes:
Providing a second pixel layer on the pixel defining layer, such that the second pixel layer covers the anode, the partition structure, the first pixel, and the second buffer layer;
and patterning the second pixel layer to form a second pixel positioned at the second pixel position.
In one embodiment, the removing the second pixel layer corresponding to the first pixel bit and the third pixel bit, and the second buffer layer, includes:
forming a second resist layer on the second pixel;
Removing the second pixel layer corresponding to the first pixel bit and the third pixel bit;
removing the second buffer layer;
and removing the second resist layer.
In one embodiment, the disposing and patterning the third pixel layer in the pixel defining layer includes:
providing a third pixel layer on the pixel defining layer, such that the third pixel layer covers the anode, the partition structure, the first pixel, and the second pixel;
And patterning the third pixel layer to form a third pixel positioned at the third pixel position.
In one embodiment, the removing the third pixel layer corresponding to the first pixel bit and the second pixel bit includes:
forming a third resist layer at the third pixel;
removing the third pixel layer corresponding to the first pixel bit and the second pixel bit;
and removing the third resist layer.
In one embodiment, after the removing the third resist layer, the method further includes:
Providing a filling layer, wherein the filling layer covers the first pixel, the second pixel and the third pixel;
And attaching a cover plate on the filling layer or forming a film packaging layer.
The preparation method of the display panel provided by the application has the beneficial effects that: compared with the prior art, the first buffer layer is arranged on the anode corresponding to the second pixel position, the second buffer layer is arranged on the anode corresponding to the third pixel position, and the thickness of the second buffer layer is larger than that of the first buffer layer, so that the anode is not directly scraped when the first pixel layer corresponding to the second pixel position and the third pixel position is removed after the first pixel layer is formed and patterned, and the anode is not directly scraped when the second pixel layer corresponding to the first pixel position and the third pixel position is removed after the second pixel layer is formed and patterned, thereby effectively avoiding damage to the anode during pixel patterning, or display defects are caused to the pixels after the pixel patterning, and greatly improving the yield and the display effect of the display panel.
The embodiment of the application also provides a display panel, which is prepared by the method according to any embodiment, and comprises a substrate, a pixel limiting layer and a partition structure, wherein the substrate is provided with a driving circuit; the pixel limiting layer is arranged on the substrate and comprises a plurality of pixel positions which are mutually spaced, and each pixel position is provided with a pixel; the partition structure includes a first partition layer which is provided in the pixel defining layer and is conductive and a second partition layer which is not conductive; the pixel comprises an organic light-emitting layer, a cathode and an encapsulating layer which are stacked, wherein the organic light-emitting layer and the partition structure are mutually spaced, and the cathode is connected with the first partition layer of the adjacent partition structure; the pixel bits are three, namely a first pixel bit, a second pixel bit and a third pixel bit, and the luminous colors of the organic luminous layers of the pixels arranged on the first pixel bit, the second pixel bit and the third pixel bit are different.
The display panel provided by the application has the beneficial effects that: compared with the prior art, the method has the advantages that the first buffer layer is arranged on the anode corresponding to the second pixel position, the second buffer layer is arranged on the anode corresponding to the third pixel position, and the thickness of the second buffer layer is larger than that of the first buffer layer, so that the anode is not directly scraped when the first pixel layer corresponding to the second pixel position and the third pixel position is removed after the first pixel layer is formed and patterned, the anode is not directly scraped when the second pixel layer corresponding to the first pixel position and the third pixel position is removed after the second pixel layer is formed and patterned, damage to the anode is effectively avoided when the pixels are patterned, or display defects are caused to the pixels after the pixels are patterned, and the yield and the display effect of the display panel can be greatly improved.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present application;
fig. 2 is a device diagram after the operation of step S101 is completed;
fig. 3 is a device diagram after the operation of step S102 is completed;
fig. 4 is a schematic flowchart of step S101 in fig. 1;
fig. 5 is a schematic diagram of a specific flow of step S103 in fig. 1;
fig. 6 is a device diagram after the operation of step S1032 is completed;
fig. 7 is a schematic diagram of a specific flow of step S104 in fig. 1;
fig. 8-1 is a device diagram after the operation of step S1041 is completed;
fig. 8-2 is a device diagram after the completion of the operation of step S1042;
Fig. 8-3 are device diagrams after the completion of the operation of step S1043;
Fig. 8-4 are device diagrams after the completion of the operation of step S1044;
Fig. 9 is a schematic diagram of a specific flow of step S105 in fig. 1;
fig. 10 is a device diagram after the operation of step S1052 is completed;
fig. 11 is a schematic diagram of a specific flow of step S106 in fig. 1;
Fig. 12-1 is a device diagram after the operation of step S1061 is completed;
fig. 12-2 is a device diagram after the completion of the operation of step S1062;
Fig. 12-3 is a device diagram after the completion of the operation of step S1063;
fig. 12-4 are device diagrams after the completion of the operation of step S1064;
Fig. 13 is a schematic diagram of a specific flow of step S107 in fig. 1;
Fig. 14 is a device diagram after the operation of step S1072 is completed;
Fig. 15 is a schematic flowchart of step S108 in fig. 1;
FIG. 16-1 is a device diagram after the completion of the operation of step S1081;
FIG. 16-2 is a device diagram after the completion of the operation of step S1082;
FIG. 16-3 is a device diagram after the completion of the operation of step S1083;
fig. 17 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Reference numerals: 100. a lining plate; 1. a substrate; 10. a driving circuit;
2. an anode; 701. an organic light emitting layer; 702. a cathode; 703. an encapsulation layer;
3. a pixel defining layer; 31. a first pixel bit; 32. a second pixel bit; 33. a third pixel bit;
4.a partition structure; 41. a first barrier layer; 42. a second barrier layer;
5. A first buffer layer; 6. a second buffer layer;
7. A first pixel layer; 70. a first pixel; 71. a first resist layer;
8. a second pixel layer; 80. a second pixel; 81. a second resist layer;
9. a third pixel layer; 90. a third pixel; 91. a third resist layer;
200. A filling layer; 300. and a cover plate.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
It should be further noted that, in the embodiments of the present application, the same reference numerals denote the same components or the same parts, and for the same parts in the embodiments of the present application, reference numerals may be given to only one of the parts or the parts in the drawings, and it should be understood that, for other same parts or parts, the reference numerals are equally applicable.
The embodiment of the application provides a display panel and a preparation method thereof, which solve the problems that the prior display panel is easy to damage an anode when pixels are patterned or cause display defects to the pixels after patterning.
Referring to fig. 1, the method for manufacturing a display panel according to an embodiment of the present application includes the following steps:
S101, providing a backing plate 100, wherein the backing plate 100 comprises a substrate 1 with a driving circuit 10, a plurality of anodes 2 arranged on the substrate 1 at intervals, a pixel limiting layer 3 positioned around the anodes 2, and a partition structure 4 arranged on the pixel limiting layer 3; the pixel defining layer 3 comprises first 31, second 32 and third 33 pixel bits spaced apart from each other.
Fig. 2 is a device diagram after the operation of step S101 is completed.
S102, forming a first buffer layer 5 on the anode 2 corresponding to the second pixel position 32, forming a second buffer layer 6 on the anode 2 corresponding to the third pixel position 33, wherein the thickness of the second buffer layer 6 is larger than that of the first buffer layer 5.
Fig. 3 is a device diagram after the operation of step S102 is completed. The first buffer layer 5 and the second buffer layer 6 can be made of the same material, so that material replacement can be avoided, and the manufacturing efficiency of the first buffer layer 5 and the second buffer layer 6 is improved. Specifically, the first buffer layer 5 and the second buffer layer 6 may be made of materials similar to photoresist, the materials are easy to remove, dry etching or wet etching can be adopted during the removal, and the etching process conditions are milder, so that the anode 2 is not easy to be damaged or remain, and the original form of the surface of the anode 2 is ensured to be unchanged.
The first buffer layer 5 and the second buffer layer 6 may be prepared in various manners, for example, deposition manner or spraying manner, and the embodiment of the present application is not limited specifically. The first buffer layer 5 and the second buffer layer 6 need to be prepared by taking care that the anodes 2 corresponding to the second pixel locations 32 and the third pixel locations 33 should be completely covered, so as to ensure that the anodes 2 are not etched when the organic luminescent material is removed after patterning the pixels, and damage is not caused to the anodes 2. The first buffer layer 5 and the second buffer layer 6 in the embodiment of the application are formed on the anode 2 and extend to be in contact with the adjacent partition structure 4, so that the area of the first buffer layer 5 and the area of the second buffer layer 6 are far greater than the corresponding area of the anode 2, the anode 2 can be better protected from being damaged when the organic luminescent material is removed after the pixels are patterned, and the problem that the display defect is caused by the fact that the organic luminescent material is not completely removed and remains on the anode 2 can be avoided.
S103, the first pixel layer 7 is disposed and patterned on the pixel defining layer 3.
S104, removing the first pixel layer 7 corresponding to the second pixel bit 32 and the third pixel bit 33 and the first buffer layer 5.
S105, the second pixel layer 8 is disposed and patterned on the pixel defining layer 3.
S106, removing the second pixel layer 8 corresponding to the first pixel bit 31 and the third pixel bit 33, and the second buffer layer 6.
S107, the third pixel layer 9 is disposed and patterned on the pixel defining layer 3.
S108, removing the third pixel layer 9 corresponding to the first pixel bit 31 and the second pixel bit 32.
In the preparation method of the embodiment of the application, after patterning the first pixel layer 7 in the process of preparing the display panel, when the first pixel layer 7 corresponding to the second pixel bit 32 and the third pixel bit 33 is removed, the first pixel bit 32 is provided with the first buffer layer 5, and the third pixel bit 33 is provided with the second buffer layer 6, so that the anode 2 is not damaged, and the first pixel layer 7 to be removed is contacted with the first buffer layer 5 and the second buffer layer 6, so that the first pixel layer 7 can be removed more cleanly. After patterning the second pixel layer 8, when the second pixel layer 8 corresponding to the first pixel bit 31 and the third pixel bit 33 is removed, the second pixel layer 8 to be removed is in contact with the second buffer layer 6 because the third pixel bit 33 is provided with the second buffer layer 6, so that the second pixel layer 8 can be removed more cleanly.
It should be noted that, in the embodiment of the present application, after removing the first pixel layer 7 corresponding to the second pixel bit 32 and the third pixel bit 33, before setting the second pixel layer 8, the first buffer layer 5 set at the second pixel bit 32 needs to be removed to expose the anode 2 at the second pixel bit 32, and since the materials of the first buffer layer 5 and the second buffer layer 6 are the same, a part of the second buffer layer 6 is removed at the same time when the first buffer layer 5 is removed, and in order to avoid that the anode 2 at the third pixel bit 33 cannot be well protected after the second buffer layer 6 is removed, the thickness of the second buffer layer 6 needs to be set to be greater than the thickness of the first buffer layer 5, so that when a part of the second buffer layer 6 is removed, the remaining part still can play a role in protecting the anode 2. However, the difference between the thickness of the second buffer layer 6 and the thickness of the first buffer layer 5 is particularly important in view of the material cost for manufacturing the buffer layer and the difficulty in removing the buffer layer.
If the difference between the thickness of the second buffer layer 6 and the thickness of the first buffer layer 5 is too large, that is, the thickness of the second buffer layer 6 exceeds the thickness of the first buffer layer 5 by too much, for example, the thickness of the second buffer layer 6 is twice the thickness of the first buffer layer 5, more materials are required for manufacturing the first buffer layer 5 and the second buffer layer 6, the setting time period is also prolonged, the overall manufacturing cost is increased, and the time period and difficulty required for removing the second buffer layer 6 are also greater, thereby reducing the manufacturing efficiency of the display panel.
If the difference between the thickness of the second buffer layer 6 and the thickness of the first buffer layer 5 is too small, that is, the thickness of the second buffer layer 6 exceeds the thickness of the first buffer layer 5 by too small, for example, the thickness of the second buffer layer 6 exceeds the thickness of the first buffer layer 5 by a distance of one fifth of the thickness of the first buffer layer 5, the thickness of the remaining portion of the second buffer layer 6 is only one fifth of the thickness of the first buffer layer 5 after the first buffer layer 5 is removed, and the second buffer layer 6 may be etched to the anode 2 due to too small thickness or the etching difficulty may be increased due to too small thickness of the second buffer layer 6, thereby reducing the manufacturing efficiency of the display panel.
Therefore, referring to fig. 3, the difference between the thicknesses of the second buffer layer 6 and the first buffer layer 5 in the embodiment of the present application is greater than or equal to one-fourth of the thickness of the first buffer layer 5 and less than or equal to the thickness of the first buffer layer 5. Therefore, the manufacturing cost of the buffer layer is not excessively increased, the anode 2 can be well protected by the residual part of the second buffer layer 6 after the first buffer layer 5 is removed, and meanwhile, the difficulty of the residual part of the second buffer layer 6 in removing is not increased, so that the manufacturing efficiency of the display panel is not adversely affected.
Further, referring to fig. 4, the step S101 may specifically include the following steps:
s1011, the substrate 1 with the driving circuit 10 is provided.
S1012, a plurality of anodes 2 spaced apart from each other and a pixel defining layer 3 located around the anodes 2 are formed on the substrate 1.
Wherein the pixel defining layer 3 comprises a first pixel bit 31, a second pixel bit 32 and a third pixel bit 33 spaced apart from each other.
S1013, a first barrier layer 41 is deposited on the substrate 1 such that the first barrier layer 41 covers the pixel defining layer 3 and the anode 2.
S1014, depositing a second isolation layer 42 on the first isolation layer 41.
S1015, a resist is disposed and patterned on the second barrier layer 42.
A resist is disposed over the second barrier layer 42. The resist is a positive resist or a negative resist. Positive resists include portions of the resist that, when exposed to actinic radiation, after a pattern is written into the resist using the actinic radiation, the irradiated portions are soluble in a resist developer applied to the resist, leaving portions that were not irradiated to form a resist pattern. The negative resist includes a portion of the resist that, when exposed to light radiation, after a pattern is written into the resist using the light radiation, the portion not irradiated with the light will be dissolved in a resist developer applied to the resist, and the portion irradiated with the light will be insoluble in the resist developer applied to the resist to form a resist pattern. The chemical composition of the resist determines whether the resist is a positive resist or a negative resist. The resist is patterned to form pixel openings corresponding to the first pixel bit 31, the second pixel bit 32, and the third pixel bit 33. Patterning is one of a photolithographic, digital lithographic process, or laser ablation process.
S1016, the pixel opening portions of the second barrier layer 42 and the first barrier layer 41 corresponding to the anode 2 are removed.
The second barrier layer 42 exposed by the pixel opening may be removed by a dry etching process, and the first barrier layer 41 exposed by the pixel opening may be removed by a wet etching process.
S1017, removing the resist to obtain the partition structure 4.
After removing the pixel opening portions of the second barrier layer 42 and the first barrier layer 41 corresponding to the anode 2, the second barrier layer 42 and the first barrier layer 41 of the portion covered with the resist form the barrier structure 4, and therefore, the resist remaining on the second barrier layer 42 can be removed to obtain the barrier structure 4.
Specifically, the specific implementation steps of the step S102 may be: the first buffer layer 5 is formed on the anode 2 corresponding to the second pixel position 32 by using one mask plate, and the second buffer layer 6 is formed on the anode 2 corresponding to the third pixel position 33 by using the other mask plate.
The specific implementation steps of the step S102 may also be: setting buffer materials on the anode 2 corresponding to the second pixel position 32 and the anode 2 corresponding to the third pixel position 33 simultaneously by using a mask plate so as to form a first buffer layer 5 on the anode 2 corresponding to the second pixel position 32 and form a part of a second buffer layer 6 on the anode 2 corresponding to the third pixel position 33; and then, a buffer material is continuously arranged on a part of the second buffer layer 6 by using another mask plate so as to form the second buffer layer 6 on the anode 2 corresponding to the third pixel position 33.
Further, referring to fig. 5, the step S103 may specifically include the following steps:
s1031, the first pixel layer 7 is provided on the pixel defining layer 3, and the first pixel layer 7 covers the anode 2, the partition structure 4, the first buffer layer 5, and the second buffer layer 6.
The first pixel layer 7 includes an organic light emitting layer 701, a cathode 702, and an encapsulation layer 703 which are stacked, and the light emitting color of the organic light emitting layer 701 of the first pixel layer 7 may be red. Specifically, the specific operation manner of setting the first pixel layer 7 is as follows: firstly, forming an organic light emitting layer 701 on a pixel defining layer 3, wherein the organic light emitting layer 701 covers an anode 2, a partition structure 4, a first buffer layer 5 and a second buffer layer 6, and the organic light emitting layer 701 and the partition structure 4 at the corresponding position of the anode 2 are mutually separated; forming a cathode 702 on the organic light emitting layer 701, wherein the cathode 702 at the position corresponding to the anode 2 is connected with the partition structure 4; finally, an encapsulation layer 703 is formed on the cathode 702, and the encapsulation layer 703 extends along the sidewalls of the partition structure 4.
Among them, the organic light emitting layer 701 is formed by evaporation deposition, specifically, deposition of an OLED material including a Hole Injection (HIL), a Hole Transport (HTL), an emission layer (EML), and an Electron Transport Layer (ETL).
The cathode 702 is formed by means of evaporation deposition, the partition structures 4 defining a deposition angle for each of the OLED material and the cathode 702, i.e. a shadow effect (shadowing effect) is provided during evaporation deposition, such that the OLED material does not contact the partition structures 4 and the cathode 702 contacts the partition structures 4.
S1032, patterning the first pixel layer 7 to form the first pixel 70 located in the first pixel bit 31.
Fig. 6 is a device diagram after the operation of step S1032 is completed. Wherein the first pixel 70 is a red pixel.
Referring to fig. 7, the step S104 may specifically include the steps of:
s1041, a first resist layer 71 is formed on the first pixel 70.
Fig. 8-1 is a device diagram after the operation of step S1041 is completed. The first resist layer 71 is made of resist. The first resist layer 71 is formed on the encapsulation layer 703 of the first pixel 70.
S1042, removing the first pixel layer 7 corresponding to the second pixel bit 32 and the third pixel bit 33.
Fig. 8-2 is a device diagram after the operation of step S1042 is completed. The first pixel layer 7 corresponding to the second pixel bit 32 and the third pixel bit 33 may be removed by a dry etching process. Since the first resist layer 71 is formed on the first pixel 70, the first pixel 70 is not damaged when the first pixel layer 7 corresponding to the second pixel bit 32 and the third pixel bit 33 is etched.
S1043, removing the first buffer layer 5.
Fig. 8-3 are device diagrams after the operation of step S1043 is completed. The second pixel 80 needs to be continuously fabricated after the fabrication of the first pixel 70 is completed, and thus the first buffer layer 5 needs to be removed to expose the anode 2 corresponding to the second pixel bit 32 in order to be ready for fabricating the second pixel 80.
S1044, removing the first resist layer 71; wherein the first resist layer 71 and the second buffer layer 6 are different in material.
Fig. 8-4 are device diagrams after the completion of the operation of step S1044.
It should be noted that, if the first resist layer 71 and the first buffer layer 5 and the second buffer layer 6 are made of the same material, the second buffer layer 6 is removed together when the first resist layer 71 is removed, so that the anode 2 corresponding to the third pixel position 33 cannot be protected by the second buffer layer 6, the second pixel layer 8 directly covers the anode 2 corresponding to the third pixel position 33, the anode 2 must be etched when the second pixel layer 8 corresponding to the third pixel position 33 is removed, damage is caused to the anode 2, and an organic luminescent material which is not removed is still easily remained on the anode 2 in some cases, which causes display defects of the pixel disposed at the third pixel position 33. Therefore, the first resist layer 71 and the second buffer layer 6 need to be made of different materials to perform the operation of step S1044.
In some embodiments, after the step S1043 is completed, step S1044 may not be performed, that is, the first resist layer 71 is left at the first pixel bit 31, and when the second pixel layer 8 is disposed again, the second pixel layer 8 corresponding to the first pixel bit 31 is disposed on the first resist layer 71, and the first resist layer 71 is removed together when the second buffer layer 6 is removed. In this case, the first resist layer 71, the first buffer layer 5, and the second buffer layer 6 may be made of the same material.
Referring to fig. 9, the step S105 may specifically include the following steps:
S1051, disposing the second pixel layer 8 on the pixel defining layer 3, so that the second pixel layer 8 covers the anode 2, the partition structure 4, the first pixel 70, and the second buffer layer 6.
The second pixel layer 8 includes an organic light emitting layer 701, a cathode 702, and an encapsulation layer 703 which are stacked, and the light emitting color of the organic light emitting layer 701 of the second pixel layer 8 may be green. Specifically, the specific operation manner of disposing the second pixel layer 8 is as follows: firstly, forming an organic light emitting layer 701 on a pixel defining layer 3, wherein the organic light emitting layer 701 covers an anode 2, a partition structure 4, a first pixel 70 and a second buffer layer 6, and the organic light emitting layer 701 and the partition structure 4 at the corresponding position of the anode 2 are mutually separated; forming a cathode 702 on the organic light emitting layer 701, wherein the cathode 702 at the position corresponding to the anode 2 is connected with the partition structure 4; finally, an encapsulation layer 703 is formed on the cathode 702, and the encapsulation layer 703 extends along the sidewalls of the partition structure 4.
S1052, patterning the second pixel layer 8, forming the second pixel 80 at the second pixel bit 32.
Fig. 10 is a device diagram after the operation of step S1052 is completed. Wherein the second pixel 80 is a green pixel.
Referring to fig. 11, the step S106 may specifically include the steps of:
S1061, a second resist layer 81 is formed on the second pixel 80.
Fig. 12-1 is a device diagram after the operation of step S1061 is completed. The second resist layer 81 is made of a resist. A second resist layer 81 is fabricated on the encapsulation layer 703 of the second pixel 80.
S1062, removing the second pixel layer 8 corresponding to the first pixel bit 31 and the third pixel bit 33.
Fig. 12-2 is a device diagram after the operation of step S1062 is completed. The second pixel layer 8 corresponding to the first pixel bit 31 and the third pixel bit 33 may be removed by a dry etching process. Since the second pixel 80 is formed with the second resist layer 81, the second pixel 80 is not damaged when the second pixel layer 8 corresponding to the first pixel bit 31 and the third pixel bit 33 is etched.
S1063, removing the second buffer layer 6.
Fig. 12-3 is a device diagram after the operation of step S1063 is completed. The fabrication of the third pixel 90 needs to be continued after the fabrication of the second pixel 80 is completed, and thus the second buffer layer 6 needs to be removed to expose the anode 2 corresponding to the third pixel bit 33 in order to be ready for the fabrication of the third pixel 90.
S1064, removing the second resist layer 81.
Fig. 12-4 are device diagrams after the completion of the operation of step S1064.
Referring to fig. 13, the step S107 may specifically include the steps of:
s1071, a third pixel layer 9 is provided on the pixel defining layer 3, and the third pixel layer 9 covers the anode 2, the partition structure 4, the first pixel 70, and the second pixel 80.
The third pixel layer 9 includes an organic light emitting layer 701, a cathode 702, and an encapsulation layer 703 that are stacked, and the light emitting color of the organic light emitting layer 701 of the third pixel layer 9 may be blue. Specifically, the specific operation manner of setting the third pixel layer 9 is as follows: forming an organic light emitting layer 701 on the pixel defining layer 3, wherein the organic light emitting layer 701 covers the anode 2, the partition structure 4, the first pixel 70 and the second pixel 80, and the organic light emitting layer 701 and the partition structure 4 at the corresponding position of the anode 2 are mutually spaced; forming a cathode 702 on the organic light emitting layer 701, wherein the cathode 702 at the position corresponding to the anode 2 is connected with the partition structure 4; finally, an encapsulation layer 703 is formed on the cathode 702, and the encapsulation layer 703 extends along the sidewalls of the partition structure 4.
S1072, patterning the third pixel layer 9 to form a third pixel 90 located at the third pixel position 33.
Fig. 14 is a device diagram after the operation of step S1072 is completed. Wherein the third pixel 90 is a blue pixel.
Referring to fig. 15, the step S108 may specifically include the steps of:
s1081, a third resist layer 91 is formed on the third pixel 90.
Fig. 16-1 is a device diagram after the operation of step S1081 is completed. The third resist layer 91 is made of resist. A third resist layer 91 is fabricated on the encapsulation layer 703 of the third pixel 90.
S1082, removing the third pixel layer 9 corresponding to the first pixel bit 31 and the second pixel bit 32.
Fig. 16-2 is a device diagram after the operation of step S1082 is completed. The third pixel layer 9 corresponding to the first pixel bit 31 and the second pixel bit 32 may be removed by a dry etching process. Since the third resist layer 91 is formed in the third pixel 90, the third pixel 90 is not damaged when the third pixel layer 9 corresponding to the first pixel bit 31 and the second pixel bit 32 is etched.
S1083, the third resist 91 is removed.
Fig. 16-3 is a device diagram after the operation of step S1083 is completed. After the steps of fabricating the first pixel 70, the second pixel 80 and the third pixel 90 are completed, the third resist layer 91 is removed, and the first pixel 70, the second pixel 80 and the third pixel 90 are exposed, thereby completing the fabrication of the display panel. Fig. 16 to 3 are schematic structural views of a display panel manufactured by the manufacturing method of a display panel according to an embodiment of the present application.
In some embodiments, the following steps may be further included after step S1083 is completed:
a filling layer 200 is provided, and the filling layer 200 covers the first pixel 70, the second pixel 80, and the third pixel 90; a cover plate 300 is attached to the filling layer 200 or a thin film encapsulation layer is formed.
Fig. 17 is a device diagram after the above-described operation of disposing the filler layer 200 and the cap plate 300 is completed. The final OLED complete device can be formed through the above-described steps of providing the filling layer 200 and the cap plate 300. The cover plate 300 may be a glass cover plate or a plastic film made of PET material.
Referring to fig. 16-3, an embodiment of the present application provides a display panel, prepared according to the method of the above embodiment, including a substrate 1, a pixel defining layer 3, and a partition structure 4, the substrate 1 having a driving circuit 10; the pixel limiting layer 3 is arranged on the substrate 1, and the pixel limiting layer 3 comprises a plurality of pixel positions which are mutually spaced, wherein each pixel position is provided with one pixel; the partition structure 4 includes a first partition layer 41 which is provided in a stacked manner on the pixel defining layer 3 and is electrically conductive, and a second partition layer 42 which is electrically non-conductive; the pixel includes an organic light emitting layer 701, a cathode 702, and an encapsulation layer 703 stacked, the organic light emitting layer 701 and the partition structure 4 are spaced apart from each other, and the cathode 702 is connected to the first partition layer 41 of the adjacent partition structure 4; the plurality of pixel bits are three, namely, the first pixel bit 31, the second pixel bit 32 and the third pixel bit 33, and the organic light emitting layers 701 of the pixels provided in the first pixel bit 31, the second pixel bit 32 and the third pixel bit 33 have different light emitting colors.
The display panel provided by the embodiment of the application is prepared by the preparation method of the display panel, and because the first buffer layer 5 and the second buffer layer 6 are arranged in the preparation process, the damage to the anode 2 caused by removing the organic luminescent materials on the anode 2 of other pixels after each pixel is patterned is effectively avoided, and the problem that the display defect occurs in the pixels because the organic luminescent materials on the anode 2 are not removed completely and residual small particles are avoided, so that the yield and the display effect of the display panel are greatly improved.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method for manufacturing a display panel, comprising:
Providing a lining plate (100), wherein the lining plate (100) comprises a substrate (1) with a driving circuit (10), a plurality of mutually-spaced anodes (2) arranged on the substrate (1), a pixel limiting layer (3) positioned around the anodes (2), and a partition structure (4) arranged on the pixel limiting layer (3); the pixel defining layer (3) comprises first pixel bits (31), second pixel bits (32) and third pixel bits (33) spaced apart from each other;
Forming a first buffer layer (5) on the anode (2) corresponding to the second pixel position (32), forming a second buffer layer (6) on the anode (2) corresponding to the third pixel position (33), wherein the thickness of the second buffer layer (6) is larger than that of the first buffer layer (5);
-providing and patterning a first pixel layer (7) at the pixel defining layer (3);
-removing the first pixel layer (7) and the first buffer layer (5) corresponding to the second pixel bit (32) and the third pixel bit (33);
-providing and patterning a second pixel layer (8) at the pixel defining layer (3);
-removing the second pixel layer (8) and the second buffer layer (6) corresponding to the first pixel bit (31) and the third pixel bit (33);
-providing and patterning a third pixel layer (9) at the pixel defining layer (3);
And removing the third pixel layer (9) corresponding to the first pixel bit (31) and the second pixel bit (32).
2. The method for manufacturing a display panel according to claim 1, wherein,
The difference in thickness between the second buffer layer (6) and the first buffer layer (5) is greater than or equal to one quarter of the thickness of the first buffer layer (5) and less than or equal to the thickness of the first buffer layer (5).
3. A method of manufacturing a display panel according to claim 1 or 2, characterized in that the arranging and patterning of the first pixel layer (7) at the pixel defining layer (3) comprises:
-providing a first pixel layer (7) on the pixel defining layer (3), such that the first pixel layer (7) covers the anode (2), the partition structure (4), the first buffer layer (5) and the second buffer layer (6);
The first pixel layer (7) is patterned to form first pixels (70) located at the first pixel locations (31).
4. A method of manufacturing a display panel according to claim 3, wherein said removing the first pixel layer (7) corresponding to the second pixel bit (32) and the third pixel bit (33), and the first buffer layer (5), comprises:
Forming a first resist layer (71) on the first pixel (70);
Removing the first pixel layer (7) corresponding to the second pixel bit (32) and the third pixel bit (33);
-removing the first buffer layer (5);
-removing the first resist layer (71); wherein the first resist layer (71) and the second buffer layer (6) are different in material.
5. A method of manufacturing a display panel according to claim 4, characterized in that the arranging and patterning of the second pixel layer (8) at the pixel defining layer (3) comprises:
-providing a second pixel layer (8) on the pixel defining layer (3), such that the second pixel layer (8) covers the anode (2), the partition structure (4), the first pixels (70) and the second buffer layer (6);
patterning the second pixel layer (8) to form second pixels (80) located at the second pixel locations (32).
6. The method of manufacturing a display panel according to claim 5, wherein said removing the second pixel layer (8) corresponding to the first pixel bit (31) and the third pixel bit (33), and the second buffer layer (6), comprises:
forming a second resist layer (81) on the second pixel (80);
removing the second pixel layer (8) corresponding to the first pixel bit (31) and the third pixel bit (33);
-removing the second buffer layer (6);
The second resist layer (81) is removed.
7. A method of manufacturing a display panel according to claim 6, characterized in that the providing and patterning of the third pixel layer (9) at the pixel defining layer (3) comprises:
Providing a third pixel layer (9) on the pixel defining layer (3), such that the third pixel layer (9) covers the anode (2), the partition structure (4), the first pixels (70) and the second pixels (80);
-patterning the third pixel layer (9) forming third pixels (90) located at the third pixel bits (33).
8. The method of manufacturing a display panel according to claim 7, wherein said removing the third pixel layer (9) corresponding to the first pixel bit (31) and the second pixel bit (32) comprises:
forming a third resist layer (91) on the third pixel (90);
removing the third pixel layer (9) corresponding to the first pixel bit (31) and the second pixel bit (32);
the third resist layer (91) is removed.
9. The method of manufacturing a display panel according to claim 8, wherein after the removing the third resist layer (91), further comprising:
-providing a filling layer (200), the filling layer (200) covering the first pixel (70), the second pixel (80) and the third pixel (90);
and attaching a cover plate (300) on the filling layer (200) or forming a film packaging layer.
10. A display panel prepared according to the method of any one of claims 1-9, comprising:
A substrate (1) having a drive circuit (10);
a pixel defining layer (3) disposed on the substrate (1), the pixel defining layer (3) including a plurality of pixel bits spaced apart from each other, each pixel bit having a pixel;
A partition structure (4) including a first partition layer (41) which is provided in a stacked manner on the pixel defining layer (3) and is electrically conductive, and a second partition layer (42) which is electrically non-conductive;
The pixel comprises an organic light emitting layer (701), a cathode (702) and an encapsulating layer (703) which are stacked, wherein the organic light emitting layer (701) and the partition structure (4) are mutually separated, and the cathode (702) is connected with the first partition layer (41) of the adjacent partition structure (4);
The plurality of pixel bits are three, namely a first pixel bit (31), a second pixel bit (32) and a third pixel bit (33), and the light emitting colors of the organic light emitting layers (701) of the pixels arranged on the first pixel bit (31), the second pixel bit (32) and the third pixel bit (33) are different.
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