CN116805879A - ADC chip testing method and device - Google Patents
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Abstract
The invention provides an ADC chip testing method and device, which relate to the technical field of chip testing, and the method comprises the following steps: scaling and superposing at least two identical chips with the identical number of the ADC chips to be tested to generate a target waveform signal; and testing the ADC chip to be tested by utilizing the target waveform signal to obtain a chip test result. According to the invention, scaling and superposition processing are carried out by utilizing at least two co-located chips with the same number as the ADC chip to be tested, so that a target waveform signal is generated, the high-order chip is simulated by utilizing the generated target waveform signal, and then the simulated high-order chip is utilized to test the ADC chip to be tested, so that the effect of testing the low-order chip by utilizing the high-order chip is achieved, and the test precision is improved.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to an ADC chip testing method and device.
Background
Chip testing is an important ring in the chip industry chain, and the method for testing the chip is different according to different types of chips. The ADC chip is known as Analog-to-Digital Converter (Analog-to-digital converter), which is a converter chip that converts an Analog signal into a digital signal. In general, an ADC chip with a certain number of bits is tested by using a signal source with a DAC chip with a higher number of bits to transmit signals to the ADC chip.
Currently, since the highest number of bits of ADC/DAC chips is 24 bits, testing for 24 bits of ADC/DAC chips is mainly performed by a snapshot test and a sine wave mode. However, the number of samples that can be selected for the snapshot test is small due to the large number of tests, so that the accuracy is not high; sine wave testing is because the number of bits of the ADC/DAC chip is insufficient, and a perfect waveform cannot be generated, so that more accurate chip testing is realized.
Disclosure of Invention
The invention provides an ADC chip testing method and device, which are used for solving the defect of poor testing precision of a high-order ADC chip in the prior art, adjusting the testing waveform, realizing the effect of testing a low-order chip by using the high-order chip and improving the testing precision.
The invention provides an ADC chip testing method, which comprises the following steps: scaling and superposing at least two identical chips with the identical number of the ADC chips to be tested to generate a target waveform signal; and testing the ADC chip to be tested by utilizing the target waveform signal to obtain a chip test result.
According to the method for testing the ADC chip provided by the invention, scaling and superposition processing are carried out by utilizing at least two co-located chips with the same number of bits as the ADC chip to be tested, so as to generate a target waveform signal, and the method comprises the following steps: scaling the waveform signals output by at least one co-located chip with the same number as the ADC chip to be measured to obtain corresponding scaling signals; and superposing the constant voltage signal output by at least one co-located chip with the same number as the ADC chip to be tested and the scaling signal to generate a target waveform signal.
According to the ADC chip testing method provided by the invention, the constant voltage signals output by the parity chips are sent out according to the preset period and the preset voltage output rule, the preset voltage output rule is that the voltage difference between the constant voltage signals at adjacent time intervals accords with the preset voltage difference, and the constant voltage signals sent out later are larger than the constant voltage signals sent out earlier.
According to the method for testing the ADC chip provided by the invention, before the superposition processing is carried out on the constant voltage signal output by at least one co-located chip with the same number of the ADC chips to be tested and the scaling signal, the method comprises the following steps: judging whether the constant voltage signal output by the parity chip accords with a preset voltage value or not, wherein the preset voltage value is determined according to the constant voltage signal sent previously and a preset voltage output rule; the preset voltage output rule is that the voltage difference value between constant voltage signals of adjacent time intervals accords with the preset voltage difference value, and the constant voltage signal sent later is larger than the constant voltage signal sent earlier; based on that the constant voltage signal output by the parity chip does not accord with a preset voltage value, determining an error value according to the constant voltage signal output by the parity chip and the preset voltage value, and sending the error value and the preset voltage value to the corresponding parity chip to adjust the constant voltage signal to be output
According to the method for testing the ADC chip provided by the invention, the step of judging whether the constant voltage signal output by the parity chip accords with the preset voltage value comprises the following steps: and based on the fact that the constant voltage signal output by the co-located chip accords with a preset voltage value, superposing at least one constant voltage signal output by the co-located chip with the same number of the ADC chips to be tested with the scaling signal.
According to the method for testing the ADC chip provided by the invention, the target waveform signal is utilized to test the ADC chip to be tested, and the method comprises the following steps: performing signal conversion on the target waveform signal to obtain an analog signal; inputting the analog signal to the ADC chip to be tested to obtain a digital signal output by the ADC chip to be tested; and analyzing the digital signal to obtain a chip test result.
According to the method for testing the ADC chip provided by the invention, before the analog signal is input to the ADC chip to be tested, the method comprises the following steps: the analog signal is filtered using a filter.
The invention also provides an ADC chip testing device, which comprises: the signal generating module is used for performing scaling and superposition processing by utilizing at least two co-located chips with the same number of bits as the ADC chips to be detected to generate a target waveform signal; and the chip testing module is used for testing the ADC chip to be tested by utilizing the target waveform signal to obtain a chip testing result.
The invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the steps of the ADC chip testing method are realized by the processor when the program is executed.
The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the ADC chip testing method as described in any of the above.
The invention also provides a computer program product comprising a computer program which when executed by a processor implements the steps of the ADC chip testing method as described in any one of the above.
According to the ADC chip testing method and device, scaling and superposition processing are carried out by utilizing at least two co-located chips with the same number of bits as the ADC chip to be tested, so that a target waveform signal is generated, the high-level chip is simulated by utilizing the generated target waveform signal, the simulated high-level chip is used for testing the ADC chip to be tested, the effect of testing the low-level chip by utilizing the high-level chip is achieved, and the testing precision is improved.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of an ADC chip testing method provided by the invention;
FIG. 2 is a schematic diagram of waveform signals output by the parity chip according to the present invention;
FIG. 3 is a schematic diagram of a compressed signal provided by the present invention;
FIG. 4 is a schematic diagram of a constant voltage signal method provided by the present invention;
FIG. 5 is a schematic diagram of a constant voltage signal superimposed with a compressed signal provided by the present invention;
FIG. 6 is a schematic diagram of a method for providing a target waveform signal according to the present invention;
FIG. 7 is a schematic diagram of an ADC chip testing apparatus according to the present invention;
FIG. 8 is a schematic diagram of a signal generation module according to the present invention;
fig. 9 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 shows a schematic flow chart of an ADC chip testing method, which includes:
s11, scaling and superposition processing are carried out by utilizing at least two co-located chips with the same number of bits as the ADC chips to be tested, and a target waveform signal is generated;
s12, testing the ADC chip to be tested by utilizing the target waveform signal to obtain a chip test result.
It should be noted that S1N in the present specification does not represent the sequence of the ADC chip testing method, and the ADC chip testing method of the present invention is described below with reference to fig. 2-6.
And S11, performing scaling and superposition processing by using at least two co-located chips with the same number of bits as the ADC chip to be tested, and generating a target waveform signal.
In this embodiment, scaling and superposition are performed by using at least two co-located chips having the same number of bits as the ADC chip to be tested, to generate a target waveform signal, including:
step S111, scaling the waveform signal output by at least one co-located chip with the same number as the ADC chip to be tested to obtain a corresponding scaled signal.
In this embodiment, scaling the waveform signal output by at least one co-located chip having the same number of bits as the ADC chip to be measured includes: the waveform signal outputted from the parity chip is scaled by using a preset resistor network.
The preset resistance network is realized through the voltage division effect of the resistors, a plurality of resistors with fixed size proportion are connected in series in the preset resistance network, and the reduction of the waveform signal is realized through consuming fixed current and voltage; the resistor group selected by the resistor network is a resistor with the resistance changing in proportion to the environmental change. The specific preset resistor network may need to be adjusted according to actual requirements and scaling, and is not further limited herein.
In addition, when the scaling processing is performed on the waveform signal, the scaling ratio needs to be determined according to the number of times that the generated target waveform signal is to be simulated and the parity chip sending out the constant voltage signal sends out the constant voltage signal, for example, when the ADC chip to be tested is 24 bits, the generated target waveform signal needs to simulate the 27 bits chip, and the number of times that the parity chip sending out the constant voltage signal sends out the constant voltage signal is ten times, so that the scaling ratio can be determined to be 10:1, that is, the waveform signal output by the parity chip is compressed into one tenth of the number of times.
For example, as shown in fig. 2, the parity chip outputs a waveform signal, and the signal output by the waveform signal output by the parity chip is compressed to one tenth thereof to obtain a scaled signal as shown in fig. 3, wherein the voltage value at the point a is-8V, the original voltage amplitude is 20V, and the compressed voltage becomes 2V.
Step S112, the constant voltage signal output by at least one co-located chip with the same number of bits as the ADC chip to be tested is overlapped with the scaling signal to generate a target waveform signal.
It should be noted that, the superposition processing of the constant voltage signal and the scaling signal output by the parity chip includes: and superposing the constant voltage signal and the scaling signal by using an adder to generate a target waveform signal. Further, the adder may be an adder with higher precision, such as an op-amp adder, which is not further limited herein.
It should be noted that the constant voltage signals output by the parity chip are sent out according to a preset period and a preset voltage output rule, wherein the preset voltage output rule is that the voltage difference between the constant voltage signals of adjacent time intervals accords with the preset voltage difference, and the constant voltage signal sent out later is larger than the constant voltage signal sent out earlier. In addition, the constant voltage signal and the preset voltage difference value output by the parity chip are determined according to the actual design requirement and the scaling, for example, when the scaling is ten times smaller, the preset voltage difference value can be 1.9-2.1V when the constant voltage signal is-10V to 10V, and when the preset voltage difference value is 2V, the effect is better; when the constant voltage signal is-5V to 5V, the preset voltage difference may be 0.9V to 1.1V, and when the preset voltage difference is 1V, the effect is better, which will not be described here too much.
For example, the constant voltage signal output from the parity chip is shown in FIG. 4, and the voltage signal of-8V is added to the compressed signal by the adder, as shown in FIG. 5, assuming that the voltage signal is first sent out. And so on, the co-located chip continuously shifts, continuously sends out constant voltage signals of 6V, -4V, -2V, 0V, 2V, 4V, 6V and 8V in sequence, and continuously overlaps the constant voltage signals by an adder to obtain a target waveform signal shown in figure 6, thus the target waveform signal is equivalent to duplicating 10 original waveforms, and the bit number at the moment becomes
Namely, if the generated target waveform signal is regarded as a whole, the target waveform signal is equivalent to a 27-bit DAC chip, and the 24-bit ADC chip to be tested is tested by using the signal source, so that the test accuracy is high.
After this "27 bit DAC chip" is obtained, the resulting target waveform signal (as shown in fig. 6) is sent to the tester for data acquisition and analyzed INL using harmonic generation histogram. If INL of the original waveform signal is B, INL of the target waveform signal after adjustment is 0.1B, that is, if INL measured last by the ADC chip to be measured is 4 LSB, then INL may be (4±1) LSB in practice, and INL is (4±0.1) LSB in practice at the time of testing with the adjusted signal source, thereby improving the test accuracy to some extent.
In an alternative embodiment, before the superimposing process is performed on the constant voltage signal output by at least one parity chip having the same number of bits as the ADC chip to be tested and the scaling signal, the method includes: judging whether the constant voltage signal output by the parity chip accords with a preset voltage value or not, wherein the preset voltage value is determined according to the previously sent constant voltage signal and a preset voltage output rule; the preset voltage output rule is that the voltage difference between constant voltage signals of adjacent time intervals accords with the preset voltage difference, and the constant voltage signal sent later is larger than the constant voltage signal sent earlier; based on that the constant voltage signal output by the co-located chip does not accord with the preset voltage value, determining an error value according to the constant voltage signal output by the co-located chip and the preset voltage value, and sending the error value and the preset voltage value to the corresponding co-located chip so as to adjust the constant voltage signal to be output. It should be noted that, whether the constant voltage signal output by the co-located chip accords with the preset voltage value is determined by judging whether the constant voltage signal output by the co-located chip accords with the preset voltage value, so that the constant voltage signal output by the co-located chip is ensured to accord with the preset voltage value, and the stability and the accuracy of the constant voltage are further ensured.
Further, determining whether the constant voltage signal output by the parity chip meets a preset voltage value includes: and based on the fact that the constant voltage signal output by the co-located chip accords with a preset voltage value, superposing the constant voltage signal output by at least one co-located chip with the same number of the ADC chips to be tested with the scaling signal.
In an alternative embodiment, before determining whether the constant voltage signal output by the parity chip meets the preset voltage value, the method includes: and detecting a constant voltage signal output by the parity chip. It should be noted that, the constant voltage signal output by the co-located chip can be detected by using a universal meter, and the constant voltage signal output by the co-located chip is detected by using the universal meter, so as to ensure the accuracy of the constant voltage output by the co-located chip.
And step S12, testing the ADC chip to be tested by utilizing the target waveform signal to obtain a chip test result.
In this embodiment, using the target waveform signal, the ADC chip to be tested is tested, including: performing signal conversion on the target waveform signal to obtain an analog signal; inputting the analog signal to an ADC chip to be tested to obtain a digital signal output by the ADC chip to be tested; and analyzing the digital signal to obtain a chip test result.
In an alternative embodiment, before inputting the analog signal to the ADC chip under test, it comprises: the analog signal is filtered using a filter. The analog signal input to the ADC chip to be tested is filtered through a filter so as to isolate useless signals and noise in the analog signal, thereby improving the anti-interference performance and the signal-to-noise ratio of the signal; in addition, the filter is used for further filtering frequency components which are not interested in the ADC chip to be detected, so that the analysis precision of the subsequent analysis step is further improved.
In summary, in the embodiment of the invention, the scaling and superposition processes are performed by using at least two parity chips with the same number as the ADC chip to be tested, so as to generate the target waveform signal, so that the high-order chip is simulated by using the generated target waveform signal, and then the simulated high-order chip is used for testing the ADC chip to be tested, thereby achieving the effect of testing the low-order chip by using the high-order chip, and improving the testing precision.
The ADC chip testing apparatus provided by the present invention is described below, and the ADC chip testing apparatus described below and the ADC chip testing method described above may be referred to correspondingly.
Fig. 7 shows a schematic structural diagram of an ADC chip testing apparatus, which includes:
the signal generating module 71 performs scaling and superposition processing by using at least two co-located chips with the same number of bits as the ADC chip to be tested, and generates a target waveform signal;
the chip test module 72 tests the ADC chip to be tested using the target waveform signal to obtain a chip test result.
In the present embodiment, referring to fig. 8, the signal generating module includes a first signal generator 81, a second signal generator 82, a preset resistance network unit 83, and an adder 84, wherein: the first signal generator 81 is internally provided with a co-located chip with the same number of bits as the ADC chip to be tested, and the first signal generator 81 outputs a waveform signal to a preset resistor network 83 for scaling treatment; the preset resistance network unit 83 outputs the scaling signal obtained by the scaling process to the adder 84; the second signal generator 82 is internally provided with a co-located chip with the same number of bits as the ADC chip to be tested, and the second signal generator 82 outputs a constant voltage signal to the adder 84; the adder 84 performs a superimposition process based on the received scaling signal and the constant voltage signal, and generates a target waveform signal.
In an alternative embodiment, with continued reference to fig. 8, the signal generating module further includes an automation program 85, where the automation program 85 specifically includes: the judging subunit is used for judging whether the constant voltage signal output by the parity chip accords with a preset voltage value or not, and the preset voltage value is determined according to the previously sent constant voltage signal and a preset voltage output rule; the preset voltage output rule is that the voltage difference between constant voltage signals of adjacent time intervals accords with the preset voltage difference, and the constant voltage signal sent later is larger than the constant voltage signal sent earlier; an error determination subunit, configured to determine an error value according to the constant voltage signal output by the parity chip and the preset voltage value, based on the constant voltage signal output by the parity chip not conforming to the preset voltage value; the data transmitting subunit transmits the error value and the preset voltage value to the corresponding parity chip so as to adjust the constant voltage signal to be output; and based on the fact that the constant voltage signal output by the co-located chip accords with a preset voltage value, superposing the constant voltage signal output by at least one co-located chip with the same number of the ADC chips to be tested with the scaling signal.
In an alternative embodiment, with continued reference to fig. 8, the signal generation module further includes: the detecting unit 86 detects the constant voltage signal output by the parity chip before determining whether the constant voltage signal output by the parity chip meets the preset voltage value. It should be noted that, the constant voltage signal output by the co-located chip can be detected by using a universal meter, and the constant voltage signal output by the co-located chip is detected by using the universal meter, so as to ensure the accuracy of the constant voltage output by the co-located chip.
Chip test module 72 includes: the signal conversion unit is used for carrying out signal conversion on the target waveform signal to obtain an analog signal; the testing unit inputs the analog signals to the ADC chip to be tested to obtain digital signals output by the ADC chip to be tested; and the analysis unit is used for analyzing the digital signals to obtain chip test results.
In an alternative embodiment, the chip test module 72 further includes: and the filtering unit is used for filtering the analog signal by using a filter before the analog signal is input to the ADC chip to be tested. The analog signal input to the ADC chip to be tested is filtered through a filter so as to isolate useless signals and noise in the analog signal, thereby improving the anti-interference performance and the signal-to-noise ratio of the signal; in addition, the filter is used for further filtering frequency components which are not interested in the ADC chip to be detected, so that the analysis precision of the subsequent analysis step is further improved.
In summary, in the embodiment of the invention, the signal generating module performs scaling and superposition processing by using at least two parity chips with the same number of bits as the ADC chip to be tested, so as to generate the target waveform signal, so that the high-order chip is simulated by using the generated target waveform signal, and then the simulated high-order chip is used for testing the ADC chip to be tested by the chip testing module, thereby achieving the effect of testing the low-order chip by using the high-order chip, and improving the testing precision.
Fig. 9 illustrates a physical schematic diagram of an electronic device, as shown in fig. 9, which may include: processor 91, communication interface (Communications Interface) 92, memory 93 and communication bus 94, wherein processor 91, communication interface 92, memory 93 accomplish the communication between each other through communication bus 94. The processor 91 may invoke logic instructions in the memory 93 to perform an ADC chip test method comprising: scaling and superposing at least two identical chips with the identical number of the ADC chips to be tested to generate a target waveform signal; and testing the ADC chip to be tested by utilizing the target waveform signal to obtain a chip test result.
Further, the logic instructions in the memory 93 described above may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product, where the computer program product includes a computer program, where the computer program can be stored on a non-transitory computer readable storage medium, and when the computer program is executed by a processor, the computer can execute the ADC chip testing method provided by the above methods, and the method includes: scaling and superposing at least two identical chips with the identical number of the ADC chips to be tested to generate a target waveform signal; and testing the ADC chip to be tested by utilizing the target waveform signal to obtain a chip test result.
In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the ADC chip testing method provided by the above methods, the method comprising: scaling and superposing at least two identical chips with the identical number of the ADC chips to be tested to generate a target waveform signal; and testing the ADC chip to be tested by utilizing the target waveform signal to obtain a chip test result.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. An ADC chip testing method, comprising:
scaling and superposing at least two identical chips with the identical number of the ADC chips to be tested to generate a target waveform signal;
and testing the ADC chip to be tested by utilizing the target waveform signal to obtain a chip test result.
2. The method for testing an ADC chip according to claim 1, wherein the scaling and stacking at least two co-located chips having the same number of bits as the ADC chip to be tested to generate the target waveform signal includes:
scaling the waveform signals output by at least one co-located chip with the same number as the ADC chip to be measured to obtain corresponding scaling signals;
and superposing the constant voltage signal output by at least one co-located chip with the same number as the ADC chip to be tested and the scaling signal to generate a target waveform signal.
3. The ADC chip testing method according to claim 2, wherein the constant voltage signals output by the co-located chips are sent out according to a preset period and a preset voltage output rule, the preset voltage output rule is that a voltage difference between constant voltage signals of adjacent time intervals corresponds to a preset voltage difference, and the constant voltage signal sent out later is larger than the constant voltage signal sent out earlier.
4. The ADC chip testing method according to claim 2, wherein before the superimposing process is performed on the constant voltage signal output from the at least one parity chip having the same number of bits as the ADC chip to be tested and the scaling signal, comprising:
judging whether the constant voltage signal output by the parity chip accords with a preset voltage value or not, wherein the preset voltage value is determined according to the constant voltage signal sent previously and a preset voltage output rule; the preset voltage output rule is that the voltage difference value between constant voltage signals of adjacent time intervals accords with the preset voltage difference value, and the constant voltage signal sent later is larger than the constant voltage signal sent earlier;
and determining an error value according to the constant voltage signal output by the parity chip and the preset voltage value based on the fact that the constant voltage signal output by the parity chip does not accord with the preset voltage value, and sending the error value and the preset voltage value to the corresponding parity chip so as to adjust the constant voltage signal to be output.
5. The ADC chip testing method according to claim 4, wherein the determining whether the constant voltage signal output by the parity chip meets a preset voltage value includes:
and based on the fact that the constant voltage signal output by the co-located chip accords with a preset voltage value, superposing at least one constant voltage signal output by the co-located chip with the same number of the ADC chips to be tested with the scaling signal.
6. The ADC chip testing method according to claim 1, wherein the testing the ADC chip to be tested using the target waveform signal includes:
performing signal conversion on the target waveform signal to obtain an analog signal;
inputting the analog signal to the ADC chip to be tested to obtain a digital signal output by the ADC chip to be tested;
and analyzing the digital signal to obtain a chip test result.
7. The ADC chip testing method according to claim 6, comprising, before the inputting the analog signal to the ADC chip under test:
the analog signal is filtered using a filter.
8. An ADC chip testing apparatus, comprising:
the signal generating module is used for performing scaling and superposition processing by utilizing at least two co-located chips with the same number of bits as the ADC chips to be detected to generate a target waveform signal;
and the chip testing module is used for testing the ADC chip to be tested by utilizing the target waveform signal to obtain a chip testing result.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the ADC chip testing method according to any one of claims 1 to 7 when the program is executed.
10. A non-transitory computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor implements the steps of the ADC chip testing method according to any one of claims 1 to 7.
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