CN116880121A - Manufacturing method and structure of array substrate shared by photomasks - Google Patents

Abstract

The invention provides an array substrate manufacturing method and a structure shared by photomasks, which includes the following steps: using a first photomask and a second photomask to sequentially prepare a gate metal layer, a gate insulating layer and a semiconductor active layer, using The third photomask removes the gate insulating layer located above the gate metal layer in the GIP driving area, and forms a DC hole in the AA display area. The fourth photomask is used to prepare a source and drain metal layer above the semiconductor active layer. The fifth photomask is used to form a PV hole on the passivation layer at the position corresponding to the drain electrode. The sixth photomask is used to form the pixel electrode and overlap with the source and drain metal layers. The third photomask is again used to drive the GIP above the corresponding DC hole. Two CH holes are formed above the gate metal layer in the area, and a seventh photomask is used to prepare a common electrode layer on the insulating layer. The present invention provides an array substrate manufacturing method with shared photomasks, which can reduce the number of photomasks and reduce production costs by sharing the same photomask.

Description

A photomask-shared array substrate manufacturing method and its structure

Technical field

The present invention relates to the technical field of manufacturing display devices, and in particular, to an array substrate manufacturing method and structure using a common photomask.

Background technique

With the development of LCD technology, more and more panel manufacturers have joined the market. LCD panel manufacturers continue to invest in building high-generation lines and increase production scale. Market competition pressure on various panel manufacturers continues to increase. Under the market pressure of intensified competition and continued price plunge, panel manufacturers must improve cost control capabilities and production efficiency while ensuring product quality, and continuously optimize corporate management, in order to ensure or even improve corporate profitability. Among them, the main means of reducing costs are: 1. Reduce the cost of various raw materials and replace expensive materials while ensuring quality; 2. Reduce the process flow. As shown in Figure 1, the structure of an existing array substrate includes a GIP driving area 200 and an AA display area 100. The AA display area also includes a TFT non-display area. The structure of the array substrate is from bottom to top. They are: glass substrate 1', gate metal layer 2', gate insulating layer 3', semiconductor active layer 4', source and drain metal layer 5', passivation layer 6', flat layer 7', pixel electrode layer 8 ', the insulating layer 9' and the common electrode layer 10', the manufacturing method is as follows: using the first photomask to prepare the gate metal layer 2' on the glass substrate 1', and using the second photomask to prepare the semiconductor active layer 4 ', use a third photomask (DC photomask) to remove the gate insulating layer 3' above the gate metal layer 2' in the GIP driving area 200, and use a fourth photomask to prepare the source and drain metal layers 5', so that the The source-drain metal layer 5' is overlapped with the semiconductor active layer 4', and the source-drain metal layer 5' is connected with the gate metal layer 2' in the GIP driving area 200, using a fifth photomask. PV holes are etched on the passivation layer 6' and the flat layer 7', and then the sixth to eighth photomasks are used to prepare the pixel electrode layer 8', the insulating layer 9' and the common electrode layer 10' respectively. The existing production process is cumbersome and requires the use of eight photomasks with different structures to complete the production, and the cost of the photomasks is high.

Contents of the invention

The technical problem to be solved by the present invention is to provide an array substrate manufacturing method with shared photomasks, which can reduce the number of photomasks and reduce production costs by sharing the same photomask.

The present invention is implemented as follows: a photomask-shared array substrate manufacturing method. The manufacturing method includes the following steps:

Step S1: Provide a glass substrate. The glass substrate is divided into a GIP driving area and an AA display area. A first photomask is used to prepare a gate metal layer in the GIP driving area and AA display area of the glass substrate. A gate insulating layer is prepared above the gate metal layer, and the gate insulating layer covers the gate metal layer and the glass substrate.

Step S2: Use a second photomask to prepare a semiconductor active layer above the gate insulating layer. The semiconductor active layer is located above the gate metal layer in the AA display area.

Step S3: Use a third photomask to remove the gate insulating layer located above the gate metal layer in the GIP driving area to expose the gate metal layer, and form a DC hole in the AA display area.

Step S4: Use a fourth photomask to prepare a source and drain metal layer above the semiconductor active layer. Part of the source and drain metal layer is located in the GIP driving area and covers the gate metal layer. Part of the source and drain metal layer is The drain metal layer is located in the DC hole and covers the DC hole to form a touch line. Part of the source and drain metal layer overlaps the semiconductor active layer to form a source electrode and a drain electrode.

Step S5: Prepare a passivation layer on the source and drain metal layer, the passivation layer covers the source and drain metal layer, the glass substrate and the semiconductor active layer, and use a fifth photomask on the passivation layer A PV hole is formed by etching at the position corresponding to the drain electrode.

Step S6: Use a sixth photomask to prepare a pixel electrode layer above the passivation layer, and the pixel electrode layer is connected to the drain electrode through the PV hole.

Step S7: Prepare an insulating layer above the pixel electrode layer, the insulating layer covers the passivation layer and the pixel electrode layer, and again use a third photomask above the corresponding DC hole and in the GIP driving area. Two CH holes are formed above the gate metal layer, and the CH holes expose the source and drain metal layers in the GIP driving area and the touch lines in the AA display area.

Step S8: Use a seventh photomask to prepare a common electrode layer on the insulating layer. The common electrode layer is connected to the source and drain metal layers and touch lines through CH holes.

Further, the third mask is a half-tone mask, and the position of the third mask corresponding to the DC hole and the position of the gate metal layer in the GIP driving area are light-transmitting parts, corresponding to the PV The position of the hole is a semi-transmissive part, and other positions are light-shielding parts. In step S3, when using a third photomask to prepare a pattern, a first PR is first coated on the gate insulating layer and the semiconductor active layer. The photoresist layer is then exposed and developed to remove the first PR photoresist corresponding to the light-transmitting part, and finally the pattern is etched; in step S5, the fifth photomask is the same as the third photomask, and a fifth photomask is used When preparing the pattern, first coat a second PR photoresist layer on the passivation layer, remove the second PR photoresist corresponding to the transparent part and the semi-transparent part through exposure and development, and finally etch the corresponding touch Three PV holes above the line, above the drain and above the gate metal layer in the GIP driving area; in step S7, when using the third photomask to prepare patterns, first place the insulating layer on the A third PR photoresist layer is coated on the top, and then the third PR photoresist corresponding to the light-transmitting part is removed through exposure and development, and finally the pattern is etched. The third mask is a half-tone mask. Different patterns are prepared through the difference in transmittance of the PR photoresist at different positions. Three mask processes can be realized by using the third mask together, thereby achieving the purpose of reducing the number of masks. Thereby reducing production costs.

Embodiments of the present application also provide a new type of array substrate, which is manufactured using a photomask-shared array substrate manufacturing method as described in any one of the above.

The advantage of the present invention is that the present invention uses a third photomask to expose the gate metal layer located in the GIP driving area on the gate insulating layer, and forms a DC hole in the AA display area, and at the same time Use a third photomask to form two CH holes above the corresponding DC holes and above the gate metal layer in the GIP driving area. By using the third photomask for both mask processes, the number of photomasks can be reduced. The purpose is to reduce production costs; and the present invention eliminates the preparation of the flat layer, reduces the preparation of a Mask process, saves costs, simplifies the process, and reduces the thickness of the overall insulation layer.

Description of the drawings

The present invention will be further described below with reference to the accompanying drawings and embodiments.

Figure 1 is a schematic structural diagram of an array substrate in the prior art.

Figure 2 is a schematic structural diagram of an array substrate of the present invention.

FIG. 3 is a schematic diagram of the manufacturing process structure of an array substrate manufacturing method with shared photomask according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of the manufacturing process structure of an array substrate manufacturing method for a common photomask according to Embodiment 2 of the present invention.

Explanation of reference numbers: GIP driving area 200, AA display area 100, glass substrate 1', gate metal layer 2', gate insulating layer 3', semiconductor active layer 4', source and drain metal layer 5', passivation Layer 6', flat layer 7', pixel electrode layer 8', insulating layer 9', common electrode layer 10', glass substrate 1, gate metal layer 2, gate insulating layer 3, DC hole 31, semiconductor active layer 4. Source and drain metal layer 5, passivation layer 6, PV hole 61, pixel electrode layer 7, insulation layer 8, CH hole 81, common electrode layer 9, first photomask 300, second photomask 400, third photon Cover 500, translucent part 501, semi-transmissive part 502, light shielding part 503, fourth photomask 600, fifth photomask 700, sixth photomask 800, seventh photomask 900, first PR photoresist layer A, The second PR photoresist layer B and the third PR photoresist layer C.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

Embodiment 1

As shown in Figures 2 to 3, the present invention provides a photomask-shared array substrate manufacturing method. The manufacturing method includes the following steps:

Step S1: Provide a glass substrate 1. The glass substrate 1 is divided into a GIP driving area 200 and an AA display area 100. The first photomask 300 is used to prepare the GIP driving area 200 and the AA display area 100 of the glass substrate 1. The gate metal layer 2 serves as the scanning signal metal electrode; a gate insulating layer 3 is prepared above the gate metal layer 2, and the gate insulating layer 3 covers the gate metal layer 2 and the glass substrate 1.

Step S2: Use the second photomask 400 to prepare a semiconductor active layer 4 above the gate insulating layer 3. The semiconductor active layer 4 is located above the gate metal layer 2 in the AA display area 100.

Step S3: Use the third photomask 500 to remove the gate insulating layer 3 located above the gate metal layer 2 in the GIP driving area 200 to expose the gate metal layer 2 and place it in the AA display area. DC hole 31 is formed by etching within 100 Å.

Step S4: Use a fourth photomask 600 to prepare a source and drain metal layer 5 above the semiconductor active layer 4. Part of the source and drain metal layer 5 is located in the GIP driving area 200 and covers the gate metal layer. 2. To achieve signal transmission, part of the source-drain metal layer 5 is located in the DC hole 31 and covers the DC hole 31 to form a touch line, and part of the source-drain metal layer 5 overlaps the semiconductor active layer 4 to form a source. pole and drain.

Step S5: Prepare a passivation layer 6 on the source and drain metal layer 5. The passivation layer 6 covers the source and drain metal layer 5, the glass substrate 1 and the semiconductor active layer 4, and a fifth photomask 700 is used. A PV hole 61 is formed by etching on the passivation layer 6 at a position corresponding to the drain electrode.

Step S6: Use the sixth photomask 800 to prepare a pixel electrode layer 7 above the passivation layer 6. The pixel electrode layer 7 is connected to the drain electrode through the PV hole 61.

Step S7: Prepare an insulating layer 8 above the pixel electrode layer 7. The insulating layer 8 covers the passivation layer 6 and the pixel electrode layer 7. Again, a third photomask 500 is used above the corresponding DC hole 31 and Two CH holes 81 are formed above the gate metal layer 2 in the GIP driving area 200. The CH holes 81 expose the source and drain metal layers 5 in the GIP driving area 200 and all the elements in the AA display area 100. The touch line.

Step S8: Use the seventh photomask 900 to prepare a common electrode layer 9 on the insulating layer. The common electrode layer 9 is connected to the source-drain metal layer 5 and the touch line through the CH hole 81.

The present invention uses a third photomask 500 to expose the gate metal layer 2 located in the GIP driving area 200 on the gate insulating layer 3, and forms a DC hole 31 in the AA display area 100, and at the same time Use the third photomask 500 to form two CH holes 81 above the corresponding DC holes 31 and above the gate metal layer 2 in the GIP driving area 200. The CH holes 81 in the GIP driving area 200 pass through The subsequent deposition of the common electrode layer 9 can protect the source and drain metal layer 5, and the CH hole 81 in the AA display area 100 is to connect the touch line to the common electrode layer 9. By using the two Mask processes together, the The three masks 500 can achieve the purpose of reducing the number of masks. When the number of film layers remains unchanged, the production can be completed by using only 7 different structures of masks, thereby reducing production costs; and the present invention cancels In the preparation of the flat layer, the flat layer is an insulating material. Removing the flat layer not only reduces the stress on the device, but also enhances the transmittance of the film layer, which will not affect the display, reduces the preparation of a Mask process, saves costs, and simplifies the process. , the overall insulation layer thickness is reduced.

Embodiment 2

As shown in FIG. 3 , the second embodiment is basically the same as the first embodiment. The difference is that the third mask 500 is a half-tone mask. The third mask 500 corresponds to the position of the DC hole 31 and the position of the DC hole 31 . The position of the gate metal layer 2 in the GIP driving area 200 is the light-transmitting part 501, the position corresponding to the PV hole 61 is the semi-transparent part 502, and the other positions are the light-shielding parts 503. In step S3, the third photomask 500 is used When preparing a pattern, first coat a first PR photoresist layer A on the gate insulating layer 3 and the semiconductor active layer 4, and then remove the first PR photoresist corresponding to the light-transmitting part through exposure and development. Finally, the pattern is etched, and the gate insulating layer 3 located above the gate metal layer 2 in the GIP driving area 200 is removed corresponding to the light-transmitting portion 501 of the third photomask 500 to expose the gate metal layer 2. And the DC hole 31 is formed in the AA display area 100; in step S5, the structure of the fifth photomask 700 is the same as the third photomask 500, so the third photomask can be used where the fifth photomask 700 is used. Mask 500. In this embodiment, when the fifth photomask 700 is used to prepare patterns, a second PR photoresist layer B is first coated on the passivation layer 6, and the corresponding light-transmitting portion and semi-transparent light are removed through exposure and development. In the second PR photoresist of the fifth mask 700 , the positions of the transparent portion 501 and the semi-transparent portion 502 of the fifth mask 700 correspond to above the DC hole 31 , above the drain electrode, and the gate electrode in the GIP driving area 200 The second PR photoresist above the metal layer 2 is removed, and finally three holes with the same depth and one-to-one correspondence are etched above the DC hole 31, above the drain, and above the gate metal layer in the GIP driving area. PV hole 61, finally remove the photoresist through photoresist stripping, leaving the pattern; in step S7, when using the third photomask 500 to prepare the pattern, first coat a third PR photoresist layer on the insulating layer 8 C, then remove the third PR photoresist at the position of the light-transmitting part 501 of the third photomask 500 through exposure and development, and finally etch the CH hole 81 corresponding to the light-transmitting part 501. The CH81 coincides with the PV hole 61. The source and drain metal layers 5 in the GIP driving area 200 and the touch lines in the AA display area 100 are exposed. The third photomask 500 is a half-tone mask, and the structure of the fifth photomask 700 is consistent with that of the third photomask, so the fifth photomask 700 can directly use the fifth photomask 500 to pass PR light at different positions. Preparing different patterns based on differences in light transmittance can realize three mask processes using the third photomask 500 together to achieve the purpose of reducing the number of photomasks. When the number of film layers remains unchanged, only 6 types of photomasks with different structures need to be used. The production can be completed with only a few covers, thereby reducing production costs.

Embodiment 3

Embodiments of the present application also provide a new array substrate structure, which is manufactured using a photomask-shared array substrate manufacturing method as described in any one of the above.

Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we have described are only illustrative and are not used to limit the scope of the present invention. Those skilled in the art Equivalent modifications and changes made by skilled persons in accordance with the spirit of the present invention shall be covered by the scope of protection of the claims of the present invention.

Claims (3)

1. A manufacturing method of an array substrate shared by photomasks is characterized in that: the manufacturing method comprises the following steps:

step S1: providing a glass substrate, wherein the glass substrate is divided into a GIP driving area and an AA display area, a first photomask is adopted to prepare a gate metal layer in the GIP driving area and the AA display area of the glass substrate, a gate insulating layer is prepared above the gate metal layer, and the gate insulating layer covers the gate metal layer and the glass substrate;

step S2: preparing a semiconductor active layer above the gate insulating layer by adopting a second photomask, wherein the semiconductor active layer is positioned above the gate metal layer of the AA display area;

step S3: removing the gate insulating layer above the gate metal layer in the GIP driving region by using a third photomask to expose the gate metal layer, and etching to form a DC hole in the AA display region;

step S4: preparing a source-drain metal layer above the semiconductor active layer by adopting a fourth photomask, wherein part of the source-drain metal layer is positioned in the GIP driving region and covers the gate metal layer, part of the source-drain metal layer is positioned in the DC hole and covers the DC hole to form a touch line, and part of the source-drain metal layer is overlapped with the semiconductor active layer to form a source electrode and a drain electrode;

step S5: preparing a passivation layer on the source-drain metal layer, wherein the passivation layer covers the source-drain metal layer, the glass substrate and the semiconductor active layer, and etching a position, corresponding to a drain electrode, on the passivation layer by adopting a fifth photomask to form a PV hole;

step S6: preparing a pixel electrode layer above the passivation layer by adopting a sixth photomask, wherein the pixel electrode layer is connected with the drain electrode through the PV hole;

step S7: preparing an insulating layer above the pixel electrode layer, wherein the insulating layer covers the passivation layer and the pixel electrode layer, and a third photomask is adopted again to form two CH holes above the corresponding DC holes and above the gate metal layer in the GIP driving region, and the CH holes expose the source-drain metal layer in the GIP driving region and the touch control line in the AA display region;

step S8: and preparing a public electrode layer on the insulating layer by adopting a seventh photomask, wherein the public electrode layer is connected with the source-drain metal layer and the touch control line through CH holes.

2. The method for manufacturing an array substrate for mask sharing according to claim 1, wherein: the third photomask is a half-tone mask photomask, the position of the third photomask corresponding to the DC hole and the position of the grid metal layer in the GIP driving region are light-transmitting parts, the position corresponding to the PV hole is a semi-transmitting part, and the other positions are light-shielding parts, in the step S3, when the third photomask is adopted to prepare patterns, a first PR photoresist layer is coated on the grid insulating layer and the semiconductor active layer, then the first PR photoresist corresponding to the light-transmitting part is removed through exposure and development, and finally the patterns are etched; in step S5, the structure of the fifth photomask is the same as that of the third photomask, when the fifth photomask is used for preparing a pattern, a second PR photoresist layer is coated on the passivation layer, the second PR photoresist corresponding to the light transmitting part and the semi-light transmitting part is removed through exposure and development, and finally three PV holes corresponding to the upper part of the touch line, the upper part of the drain electrode and the upper part of the gate metal layer in the GIP driving region are etched; in step S7, when a third photomask is used to prepare a pattern, a third PR photoresist layer is coated on the insulating layer, then the third PR photoresist corresponding to the light transmitting portion is removed through exposure and development, and finally the pattern is etched.

3. The utility model provides a novel array substrate which characterized in that: the array substrate is manufactured by adopting the manufacturing method of the array substrate shared by the photomasks according to any one of claims 1 to 3.