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CN116916691B - Pixel structure, pixel driving circuit and display panel - Google Patents

Pixel structure, pixel driving circuit and display panel Download PDF

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Publication number
CN116916691B
CN116916691B CN202310953076.5A CN202310953076A CN116916691B CN 116916691 B CN116916691 B CN 116916691B CN 202310953076 A CN202310953076 A CN 202310953076A CN 116916691 B CN116916691 B CN 116916691B
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light
emitting device
light emitting
anode
circuit
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CN116916691A (en
Inventor
卢昭阳
叶利丹
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HKC Co Ltd
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HKC Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The application provides a pixel structure, a pixel driving circuit and a display panel, wherein the pixel structure comprises: a plurality of sub-pixels, each sub-pixel including a first anode, a second anode, a pixel defining layer, a first light emitting device, and a second light emitting device; the first anode and the second anode are arranged at intervals, the first light-emitting device is positioned above the first anode, the second light-emitting device is positioned above the second anode, and the first light-emitting device and the second light-emitting device are alternately conducted in different light-emitting stages; the pixel defining layer is disposed around the first light emitting device and the second light emitting device. The technical scheme provided by the application can delay the aging of the image light-emitting device.

Description

Pixel structure, pixel driving circuit and display panel
Technical Field
The present application relates to the field of display technologies, and in particular, to a pixel structure, a pixel driving circuit, and a display panel.
Background
Light emitting devices such as Organic LIGHT EMITTING Diode (OLED) have been increasingly used in products such as televisions and mobile phones because of their light and thin properties, energy saving properties, wide color gamut, and high contrast.
The OLED is a current driving device, driving current is provided by an OLED driving circuit in operation, when current flows through the OLED, the OLED emits light, and the light emitting brightness is determined by the current flowing through the OLED.
In the application process of the light emitting devices such as the OLED, the materials are gradually aged, so that the driving current of the light emitting devices is changed, and the image quality of the display panel is affected.
Disclosure of Invention
In view of the above, the present application provides a pixel structure, a pixel driving circuit and a display panel for delaying the aging of a light emitting device.
In order to achieve the above object, in a first aspect, an embodiment of the present application provides a pixel structure, including: a plurality of sub-pixels, the sub-pixels including, for each sub-pixel, a first anode, a second anode, a pixel defining layer, a first light emitting device, and a second light emitting device;
The first anode and the second anode are arranged at intervals, the first light-emitting device is positioned above the first anode, the second light-emitting device is positioned above the second anode, and the first light-emitting device and the second light-emitting device are alternately conducted in different light-emitting stages;
The pixel defining layer is disposed around the first light emitting device and the second light emitting device.
As an alternative implementation manner of the embodiment of the present application, the first light emitting device and the second light emitting device are disposed at intervals.
As an alternative implementation manner of the embodiment of the present application, the first light emitting device and the second light emitting device share a plurality of functional structural layers.
As an optional implementation manner of the embodiment of the present application, the functional structural layer includes: the thickness of the first area of the light-emitting layer is larger than that of the second area and the third area, the first area is located between the first anode and the second anode, the second area is located above the first anode, and the third area is located above the second anode.
As an alternative implementation of the embodiment of the present application, the sub-pixel further includes an auxiliary cathode layer, which is located at a spaced area of the first anode and the second anode and is located under a side of the first anode and the second anode.
As an alternative implementation manner of the embodiment of the present application, the light emitting colors of the first light emitting device and the second light emitting device are the same.
In a second aspect, an embodiment of the present application provides a pixel driving circuit for driving the pixel structure according to any one of the first aspect, including: the device comprises a data input circuit, a first energy storage circuit, a first switch circuit, a first light emitting control circuit, a second energy storage circuit, a second switch circuit, a second light emitting control circuit and a third switch circuit;
The first output end of the data input circuit is electrically connected with the control end of the first light-emitting control circuit, the second output end of the data input circuit is electrically connected with the control end of the second light-emitting control circuit, and the data input circuit is used for alternately outputting data voltages to the control end of the first light-emitting control circuit and the control end of the second light-emitting control circuit in non-light-emitting phases of different light-emitting periods;
the first energy storage circuit is connected between the control end and the output end of the first light-emitting control circuit, and the second energy storage circuit is connected between the control end and the output end of the second light-emitting control circuit;
The input ends of the first light-emitting control circuit and the second light-emitting control circuit are electrically connected with a first power supply through the third switch circuit, the output end of the first light-emitting control circuit is electrically connected with the anode of a first light-emitting device through the first switch circuit, the output end of the second light-emitting control circuit is electrically connected with the anode of a second light-emitting device through the second switch circuit, the cathode of the first light-emitting device and the cathode of the second light-emitting device are electrically connected with a second power supply, the first light-emitting control circuit is used for outputting a first driving current to the first light-emitting device in a light-emitting stage, and the second light-emitting control circuit is used for outputting a second driving current to the second light-emitting device in a light-emitting stage;
the first switch circuit and the second switch circuit are turned off in a non-light-emitting stage and are alternately turned on in different light-emitting stages.
As an optional implementation manner of the embodiment of the present application, in each of the alternate on periods, the number of on frames of the first light emitting control circuit and the number of on frames of the second light emitting control circuit are both N frames, where N is a positive integer.
As an alternative implementation manner of the embodiment of the present application, the pixel driving circuit further includes: the first voltage stabilizing circuit is connected to the output end of the first light emitting control circuit and is electrically connected with the second power supply; the second voltage stabilizing circuit is connected with the output end of the second light-emitting control circuit and is electrically connected with the second power supply.
In a third aspect, an embodiment of the present application provides a display panel, including a substrate, a driving layer, and a plurality of pixel structures according to any one of the first aspect, where the driving layer is located above the substrate, and the pixel structure is located above the driving layer.
The technical scheme provided by the embodiment of the application comprises a plurality of sub-pixels, wherein each sub-pixel comprises a first anode, a second anode, a pixel definition layer, a first light emitting device and a second light emitting device. The first anode and the second anode are arranged at intervals, the first light emitting device is positioned above the first anode, the second light emitting device is positioned above the second anode, the first light emitting device and the second light emitting device are alternately conducted in different light emitting stages, and the pixel defining layer is arranged around the first light emitting device and the second light emitting device. In the above technical solution, for each sub-pixel of the display panel, since the first light emitting device and the second light emitting device are alternately turned on in different light emitting stages, that is, only the first light emitting device or the second light emitting device emits light in each light emitting stage, compared with the current light emitting device emitting light in each light emitting stage, the light emitting duration of the first light emitting device and the second light emitting device in the present solution is smaller than the light emitting duration of the current light emitting device in unit time, and the light emitting device gradually ages with the increase of the light emitting duration, that is, the shorter the light emitting duration of the light emitting device in unit time, the slower the aging speed of the light emitting device, so the solution can delay the aging of the light emitting device and prolong the service life of the light emitting device.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the application;
fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the present application;
FIG. 3 is a schematic structural diagram of another display panel according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of another display panel according to an embodiment of the present application;
fig. 5 is a schematic flow chart of a method for manufacturing a display panel according to an embodiment of the present application;
Fig. 6 is a schematic structural diagram of a sub-pixel of any one pixel structure in the display panel according to the embodiment of the present application;
FIG. 7 is a schematic diagram of a circuit structure of the pixel driving circuit in FIG. 6;
FIG. 8 is a timing diagram of a pixel driving circuit according to an embodiment of the present application;
fig. 9 to 16 are schematic diagrams of equivalent circuits of the pixel driving circuit provided in the embodiment of the application in the reset phase, the compensation phase, the writing phase and the light emitting phase.
Reference numerals illustrate:
11-a substrate base; 12-a light shielding layer;
13-a buffer layer; 14-an active layer;
15-a gate insulating layer; a 16-gate;
17-source; 18-drain electrode;
19-an interlayer dielectric layer; 20-an insulating layer;
21-a planar layer; 22-a pixel definition layer;
23-a first anode; 24-a second anode;
25-a first light emitting device; 26-a second light emitting device;
A 111-hole transport layer; 112-a light emitting layer;
113-an electron transport layer; 114-cathode;
115-an auxiliary cathode;
1121-a first region; 1122-a second region;
1123-third region.
Detailed Description
Embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. The terminology used in the description of the embodiments of the application is for the purpose of describing particular embodiments of the application only and is not intended to be limiting of the application. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
The light emitting device in the embodiment of the application can be any one of an OLED (organic light emitting diode), a Quantum Dot LIGHT EMITTING Diodes (QLED) and a sub-millimeter light emitting diode (MINI LIGHT EMITTING Diodes, mini LED); the present embodiment will be described by taking an OLED as an example.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application, and as shown in fig. 1, the display panel according to the embodiment of the present application may include a substrate 11, a driving layer, and a pixel structure sequentially disposed from bottom to top.
The substrate 11 may be a rigid substrate or a flexible substrate, the material of the rigid substrate may be glass, and the material of the flexible substrate may be a polymer material such as polyimide.
The driving layer is disposed above the substrate 11 and may include a plurality of thin film transistors (ThinFilmTransistor, TFT) for driving the pixel structure to emit light.
Specifically, the driving layer may include a light shielding layer 12, a buffer layer 13, an active layer 14, a gate insulating layer 15, a gate electrode 16, a source electrode 17, a drain electrode 18, an interlayer dielectric layer 19, an insulating layer 20, and a planarization layer 21.
The substrate 11 may be a rigid substrate or a flexible substrate, the material of the rigid substrate may be glass, and the material of the flexible substrate may be a polymer material such as polyimide.
The light shielding layer 12 is disposed above the substrate 11, the light shielding layer 12 may include a plurality of light shielding units disposed at intervals, and the material of the light shielding layer 12 may be a metal such as molybdenum, titanium, copper, or an oxide thereof, or a black resin.
The buffer layer 13 is located above the light shielding layer 12 and the substrate 11, and the buffer layer 13 plays a role in buffering when the display screen is impacted by extrusion or falling, so that the probability of breakage of the display screen is reduced, and the buffer layer 13 can be made of silicon dioxide, so that the IGZO electron mobility is improved.
The active layer 14 is located above the buffer layer 13, and a material of the active layer 14 may be indium zinc oxide (Indium Gallium Zinc Oxide, IGZO), so that higher accuracy and lower power consumption can be provided to the display screen.
A gate insulating layer 15 is located over the active layer 14, and the material of the gate insulating layer 15 may be one or a combination of silicon oxide and silicon nitride.
The gate electrode 16 is located above the gate insulating layer 15, the interlayer dielectric layer 19 is located above the buffer layer 13, the active layer 14, the gate insulating layer 15 and the gate electrode 16, a plurality of vias are arranged in the interlayer dielectric layer 19, and the source electrode 17 and the drain electrode 18 are located above the interlayer dielectric layer 19 and are in contact with two ends of the active layer 14 through different vias.
The active layer 14, the gate insulating layer 15, the gate electrode 16, the source electrode 17, and the drain electrode 18 together constitute a thin film transistor.
An insulating layer 20 is disposed over the interlayer dielectric layer 19, the source electrode 17, and the drain electrode 18, and a material of the insulating layer 20 may be silicon oxide, silicon nitride, or a combination thereof for interlayer electrical isolation and protection of the thin film transistor.
The planarization layer 21 is located above the insulating layer 20 to improve flatness and sealability of the internal structure of the display screen.
The pixel structure is located above the driving layer, and the display panel includes a plurality of pixel structures, each of which may include a plurality of sub-pixels, for example, one pixel structure may include red, green, and blue 3 sub-pixels.
Each sub-pixel structure may include a first anode 23, a second anode 24, a pixel defining layer 22, a first light emitting device 25, and a second light emitting device 26.
The first anode 23 and the second anode 24 may be positioned above the planarization layer 21 and spaced apart.
The first light emitting device 25 is located above the first anode 23, the second light emitting device 26 is located above the second anode 24, and the first light emitting device 25 and the second light emitting device can be alternately turned on in different light emitting stages, so that only the first light emitting device 25 or the second light emitting device 26 emits light in each light emitting stage, and the light emitting duration of the first light emitting device 25 and the second light emitting device 26 in unit time is smaller than the light emitting duration of the current light emitting device (the current light emitting device emits light in each light emitting stage), and the light emitting device can be gradually aged along with the increase of the light emitting duration, namely, the shorter the light emitting duration of the light emitting device in unit time is, the aging speed of the light emitting device is slower, so that the aging of the light emitting device can be delayed, and the service life of the light emitting device is prolonged.
The light emission colors of the first light emitting device 25 and the second light emitting device 26 may be the same or different, and the present embodiment will be described below by taking the same light emission colors of the first light emitting device 25 and the second light emitting device 26 as an example.
The first light emitting device 25 and the second light emitting device 26 may be disposed at intervals to reduce the influence of one light emitting device on the other light emitting device that does not emit light when the other light emitting device emits light.
The pixel defining layer 22 may be disposed around the first and second light emitting devices 25 and 26.
Fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the present application, as shown in fig. 2, the first light emitting device 25 and the second light emitting device 26 may also share a group of functional structural layers sequentially disposed from bottom to top, so as to reduce complexity during manufacturing and reduce cost. The functional structure layer may include a hole transport layer 111, a light emitting layer 112, an electron transport layer 113, a cathode 114, and the like. The present embodiment will be described by taking the example in which the first light emitting device 25 and the second light emitting device 26 share a group of the hole transport layer 111, the light emitting layer 112, the electron transport layer 113, and the cathode 114, which are sequentially disposed from bottom to top.
In the case where the first light emitting device 25 and the second light emitting device 26 are co-layered, when the first light emitting device 25 or the second light emitting device 26 emits light, the light emitting layer 112 located in the spaced region between the first anode 23 and the second anode 24 emits light slightly, so that the lifetime of the light emitting layer 112 located in the spaced region (i.e., the first region 1121) is shorter than the lifetime of the other regions of the light emitting layer 112 (including the second region 1122 above the first anode 23 and the third region 1123 above the second anode 24), and the other light emitting device is affected, so that the other non-emitting light emitting device emits weak light.
In order to make the life of each region of the light emitting layer 112 more uniform, the life of the first region 1121 of the light emitting layer 112 may be increased by increasing the thickness of the first region 1121 of the light emitting layer 112, so that the life of each region of the light emitting layer 112 more uniform. For example, as shown in fig. 3, the hole transport layer 111 may be formed as a downward groove in the spaced region of the first anode 23 and the second anode 24, the upper end surface of the light emitting layer 112 may be parallel to the upper end surface of the first anode 23, and the lower end surface of the light emitting layer 112 may be recessed in the spaced region of the first light emitting device 25 and the second light emitting device 26 to increase the thickness of the light emitting layer 112 in the spaced region of the first anode 23 and the second anode 24, thereby increasing the lifetime of the light emitting layer 112 in the spaced region of the first anode 23 and the second anode 24, so that the lifetimes of the respective regions of the light emitting layer 112 may be more uniform.
It is to be understood that the thickness of the first region 1121 of the light emitting layer 112 may also be increased by arranging the lower end surface of the light emitting layer 112 to be parallel to the upper end surface of the first anode 23, arranging the upper end surface of the light emitting layer 112 located in the first region 1121 to be convex upward, or the like.
Further, as shown in fig. 4, an auxiliary cathode 115 may be disposed below the interval region between the first anode 23 and the second anode 24, the auxiliary cathode 115 may be disposed below the sides of the first anode 23 and the second anode 24, and the auxiliary cathode 115 may be made of the same material as the cathode 114.
The auxiliary cathode 115 forms an electric field with the first anode 23 and the second anode 24, respectively, so that the number of holes transferred from the hole transport layer 111 to the light emitting layer 112 at the interval region of the first anode 23 and the second anode 24 can be reduced, thereby reducing the brightness of the light emitting layer 112 at the interval region, and further increasing the lifetime of the light emitting layer 112 at the interval region. Meanwhile, since the number of holes transported from the hole transport layer 111 located in the spaced region to the light emitting layer 112 is reduced, the number of holes in the hole transport layer 111 moving from the spaced region to the side of the light emitting device that does not emit light is also reduced, so that the influence on the light emitting device that does not emit light can be reduced, and the luminance of the light emitting device that does not emit light can be reduced.
Fig. 5 is a schematic flow chart of a method for manufacturing a display panel according to an embodiment of the present application, and as shown in fig. 5, the method for manufacturing a display panel according to an embodiment of the present application may include the following steps:
s110, forming a shading layer on the substrate.
Specifically, the light shielding layer 12 may be formed over the substrate 11 by a plasma enhanced chemical vapor deposition process, and when the light shielding layer 12 is formed, the light shielding layer 12 may be subjected to patterning treatment, specifically, the light shielding layer 12 may be subjected to patterning treatment by a method including a process of coating photoresist, exposing, developing, wet etching, removing photoresist, or the like.
The material of the light shielding layer 12 may be a metal such as molybdenum, titanium, copper, or the like, an oxide thereof, a black resin, or the like.
S120, forming a buffer layer above the light shielding layer.
Specifically, the buffer layer 13 may be formed over the light shielding layer 12 using a plasma enhanced chemical vapor deposition process. The material of the buffer layer 13 may be silicon dioxide or the like.
And S130, forming a thin film transistor, an interlayer dielectric layer, an insulating layer and a flat layer above the buffer layer.
The thin film transistor may include an active layer 14, a gate insulating layer 15, a gate electrode 16, a source electrode 17, and a drain electrode 18.
Specifically, the active layer 14, the gate insulating layer 15, and the gate electrode 16 may be sequentially formed over the buffer layer 13 by combining a plasma enhanced chemical vapor deposition process with a patterning process, then the interlayer dielectric layer 19 may be formed over the buffer layer 13, the active layer 14, the gate insulating layer 15, and the gate electrode 16, then the plurality of vias may be formed in the interlayer dielectric layer 19, and the source electrode 17 and the drain electrode 18 may be formed in the vias and over the interlayer dielectric layer 19. The source electrode 17 and the drain electrode 18 are in contact with the active layer 14 through different vias.
Next, an insulating layer 20 and a planarization layer 21 may be sequentially formed over the interlayer dielectric layer 19, the source electrode 17 and the drain electrode 18 using a plasma enhanced chemical vapor deposition process.
And S140, forming each sub-pixel structure above the flat layer.
Specifically, the cathode 114 auxiliary layer may be formed at first in the corresponding region of each sub-pixel within the planarization layer 21, then a metal thin film may be formed over the planarization layer 21 by a sputtering process, and the metal thin film may be patterned, a first anode 23 and a second anode 24 are formed in the corresponding region of each sub-pixel, a first light emitting device 25 is formed over the first anode 23, a second light emitting device 26 is formed over the second anode 24, and then a pixel defining layer 22 is formed around each first anode 23 and each second anode 24.
Fig. 6 is a schematic structural diagram of a sub-pixel of any one of the pixel structures in the display panel according to the embodiment of the present application, and as shown in fig. 6, the sub-pixel may include a first power supply VDD, a second power supply VSS, a first light emitting device OLED1, a second light emitting device OLED2, and a pixel driving circuit.
The first power supply VDD may output a high potential voltage and the second power supply VSS may output a low potential voltage.
The pixel driving circuit may include: a data input circuit 101, a first tank circuit 102, a first switch circuit 103, a first light emission control circuit 104, a second tank circuit 105, a second switch circuit 106, a second light emission control circuit 107, and a third switch circuit 108.
The first output terminal of the data input circuit 101 is electrically connected to the control terminal of the first light emitting control circuit 104, the second output terminal is electrically connected to the control terminal of the second light emitting control circuit 107, and the data input circuit 101 is configured to alternately output data voltages to the control terminal of the first light emitting control circuit 104 and the control terminal of the second light emitting control circuit 107 in non-light emitting phases of different light emitting periods. The non-light emitting phase may include a reset phase, a compensation phase, and a write phase.
One end of the first tank circuit 102 may be electrically connected to the control end of the first light emitting control circuit 104, the other end of the first tank circuit 102 may be electrically connected to the output end of the first light emitting control circuit 104, one end of the second tank circuit 105 may be electrically connected to the control end of the second light emitting control circuit 107, the other end of the second tank circuit 105 may be electrically connected to the output end of the second light emitting control circuit 107, and both the first tank circuit 102 and the second tank circuit 105 are used for storing electric energy.
The input ends of the first light emitting control circuit 104 and the second light emitting control circuit 107 may be electrically connected to the first power supply VDD through the third switch circuit 108, the output end of the first light emitting control circuit 104 is electrically connected to the anode of the first light emitting device OLED1 through the first switch circuit 103, the output end of the second light emitting control circuit 107 is electrically connected to the anode of the second light emitting device OLED2 through the second switch circuit 106, the cathode of the first light emitting device OLED1 and the cathode of the second light emitting device OLED2 are electrically connected to the second power supply VSS, the first light emitting control circuit 104 is configured to output a first driving current to the first light emitting device OLED1 in a light emitting stage, and the second light emitting control circuit 107 is configured to output a second driving current to the second light emitting device OLED2 in a light emitting stage.
The first switch circuit 103 and the second switch circuit 106 are turned off in a reset phase, a compensation phase, and a writing phase, and are alternately turned on in different light emitting phases. Therefore, only the first light-emitting device OLED1 or the second light-emitting device OLED2 emits light correspondingly in each light-emitting stage, compared with the current light-emitting device emitting light in each light-emitting stage, the light-emitting time of the first light-emitting device OLED1 and the second light-emitting device OLED2 is smaller than the light-emitting time of the current light-emitting device in unit time, and the light-emitting device can be gradually aged along with the increase of the light-emitting time, namely the shorter the light-emitting time of the light-emitting device in unit time is, the slower the aging speed of the light-emitting device is, so that the aging of the light-emitting device in the pixel driving circuit can be delayed, and the service life of the light-emitting device is prolonged.
In each of the alternate on periods, the number of on frames of the first light emission control circuit 104 and the number of on frames of the second light emission control circuit 107 may be N frames, N being a positive integer. In this way, in each alternate on period, the light emitting periods of the first light emitting device OLED1 and the second light emitting device OLED2 are substantially the same (the light emitting period of each frame may have a slight difference), so that the aging degree of the first light emitting device OLED1 and the second light emitting device OLED2 is substantially the same when in use, and the probability that one of the two light emitting devices ages due to the overlong use time and the other light emitting device is still newer when the use time is shorter is reduced. The present embodiment will be described by taking, as an example, a frame in which each of the first light emission control circuit 104 and the second light emission control circuit 107 is turned on in each of the alternate on periods.
The pixel driving circuit may further include a first voltage stabilizing circuit 109 and/or a second voltage stabilizing circuit 110, where one end of the first voltage stabilizing circuit 109 is electrically connected to the output end of the first light emitting control circuit 104, the other end of the first voltage stabilizing circuit 109 is electrically connected to the second power supply VSS, and the first voltage stabilizing circuit 109 is used for stabilizing the voltage of the output end of the first light emitting control circuit 104, so as to improve the display effect. One end of the second voltage stabilizing circuit 110 is electrically connected to the output end of the second light emitting control circuit 107, the other end of the second voltage stabilizing circuit 110 is electrically connected to the second power source VSS, and the second voltage stabilizing circuit 110 is used for stabilizing the voltage of the output end of the second light emitting control circuit 107 so as to improve the display effect.
It will be appreciated that the circuit blocks illustrated in the embodiments of the present application do not constitute a specific limitation on the pixel driving circuit. In other embodiments of the application, the pixel drive circuit may include more or less circuit blocks than shown, or some of the circuit blocks may be combined, or some of the circuit blocks may be split; each circuit module may include more or fewer devices than shown. The illustrated circuit modules may be implemented in hardware, software, or a combination of software and hardware.
Fig. 7 is a schematic circuit diagram of the pixel driving circuit in fig. 6, and as shown in fig. 7, the Data input circuit 101 may include a first switching tube T1-1, a second switching tube T1-2, a Data line Data and a first Scan line Scan1.
The first pole of the first switching tube T1-1 is electrically connected with the output end of the Data line Data, the second pole of the first switching tube T1-1 is electrically connected with the control end of the first light emitting control circuit 104, and the control pole of the first switching tube T1-1 is electrically connected with the output end of the first scanning line Scan 1.
The first pole of the second switching tube T1-2 is electrically connected with the output end of the Data line Data, the second pole of the second switching tube T1-2 is electrically connected with the control end of the second light-emitting control circuit 107, and the control pole of the second switching tube T1-2 is electrically connected with the output end of the first scanning line Scan 1.
The first switching tube T1-1 and the second switching tube T1-2 can be PMOS tubes or NMOS tubes, and when the first switching tube T1-1 is a PMOS tube, the second switching tube T1-2 is an NMOS tube; when the first switching tube T1-1 is an NMOS tube, the second switching tube T1-2 is a PMOS tube. In this embodiment, when the first switching tube T1-1 is an NMOS tube, the second switching tube T1-2 is a PMOS tube, which is described as an example.
The first switching circuit 103 may include a third switching tube T3 and a second scan line ODD, where a first pole of the third switching tube T3 is electrically connected to an output terminal of the first light emitting control circuit 104, a second pole of the third switching tube T3 is electrically connected to an anode of the first light emitting device OLED1, and a control pole of the third switching tube T3 is electrically connected to an output terminal of the second scan line ODD.
The second switching circuit 106 may include a fourth switching tube T4 and a third scan line EVEN, a first electrode of the fourth switching tube T4 is electrically connected to an output terminal of the second light emitting control circuit 107, a second electrode of the fourth switching tube T4 is electrically connected to an anode of the second light emitting device OLED2, and a control electrode of the fourth switching tube T4 is electrically connected to an output terminal of the third scan line EVEN.
The third switching circuit 108 may include a fifth switching tube T5 and a light emitting signal line EM, where a first pole of the fifth switching tube T5 is electrically connected to the first power supply VDD, a second pole of the fifth switching tube T5 is electrically connected to an input terminal of the first light emitting control circuit 104 and an input terminal of the second light emitting control circuit 107, and a control pole of the fifth switching tube T5 is electrically connected to an output terminal of the light emitting signal line EM.
The third switching tube T3, the fourth switching tube T4 and the fifth switching tube T5 may be PMOS tubes or NMOS tubes, and in this embodiment, the third switching tube T3, the fourth switching tube T4 and the fifth switching tube T5 are all NMOS tubes for example for performing an exemplary description.
The first light emitting control circuit 104 may include a first driving thin film transistor T2-1, a first electrode of the first driving thin film transistor T2-1 is electrically connected to a second electrode of the fifth switching transistor T5, a second electrode of the first driving thin film transistor T2-1 is electrically connected to an anode of the first light emitting device OLED1 through a third switching transistor T3, and a control electrode of the first driving thin film transistor T2-1 is electrically connected to a second electrode of the first switching transistor T1-1.
The second light emission control circuit 107 may include a second driving thin film transistor T2-2, a first electrode of the second driving thin film transistor T2-2 is electrically connected to a second electrode of the fifth switching transistor T5, a second electrode of the second driving thin film transistor T2-2 is electrically connected to an anode of the second light emitting device OLED2 through a fourth switching transistor T4, and a control electrode of the second driving thin film transistor T2-2 is electrically connected to a second electrode of the second switching transistor T1-2.
The first driving thin film transistor T2-1 and the second driving thin film transistor T2-2 may be NMOS transistors, and at this time, the first electrode of the first driving thin film transistor T2-1 and the second electrode of the second driving thin film transistor T2-2 are drain electrodes, the second electrode is a source electrode, and the control electrode is a gate electrode. The first driving thin film transistor T2-1 and the second driving thin film transistor T2-2 may be other types of MOS transistors, which are not particularly limited in this embodiment, and the first driving thin film transistor T2-1 and the second driving thin film transistor T2-2 are both NMOS transistors in the following exemplary embodiment.
The first tank circuit 102 may include a first capacitor C1, one end of the first capacitor C1 is electrically connected to the gate of the first driving thin film transistor T2-1, and the other end of the first capacitor C1 is electrically connected to the source of the first driving thin film transistor T2-1; the second tank circuit 105 may include a second capacitor C2, one end of the second capacitor C2 is electrically connected to the gate of the second driving thin film transistor T2-2, and the other end of the second capacitor C2 is electrically connected to the source of the second driving thin film transistor T2-2.
The first voltage stabilizing circuit 109 may include a third capacitor C3, one end of the third capacitor C3 is electrically connected to the source of the first driving thin film transistor T2-1, and the other end of the third capacitor C3 is electrically connected to the second power source VSS; the second voltage stabilizing circuit 110 may include a fourth capacitor C4, one end of the fourth capacitor C4 is electrically connected to the source of the second driving thin film transistor T2-2, and the other end of the fourth capacitor C4 is electrically connected to the second power source VSS.
Fig. 8 is a timing chart of the operation of the pixel driving circuit according to the embodiment of the application, as shown in fig. 8, each frame can be divided into a reset phase I, a compensation phase II, a writing phase III and a light emitting phase IV.
As shown in fig. 9, in the reset phase I of the nth frame, the first Scan line Scan1 outputs a high level signal, the first switching tube T1-1 is turned on, and the second switching tube T1-2 is turned off. The Data line Data outputs a first Data voltage Vref, resets the voltage of the first node G1, and turns on the first driving thin film transistor T2-1. The light emitting signal line EM outputs a high level signal, the fifth switching transistor T5 is turned on, the first power supply VDD writes a low voltage Vsus, and the voltage of the second node S1 is reset. The voltage vg1=vref at the first node G1 and vs1=vsus at the second node S1 at this stage. Meanwhile, the second scan line ODD and the third scan line EVEN output low-level scan signals, the third switching tube T3 and the fourth switching tube T4 are turned off, and the first light emitting device OLED1 and the second light emitting device OLED2 do not emit light.
As shown in fig. 10, in the compensation stage II of the nth frame, the potential output by each signal line is consistent with that of the reset stage, the first power supply VDD writes the high potential voltage VDD, and continuously charges the second node S1, and when the voltage at S1 rises to Vref-Vth1, the first driving thin film transistor T2-1 reaches the critical cut-off. The voltage vs1=vref-Vth 1 of the second node S1 in this stage, where Vth1 is the threshold voltage of the first driving thin film transistor T2-1. At this stage the first light emitting device OLED1 and the second light emitting device OLED2 still do not emit light.
As shown in fig. 11, in the writing period III of the nth frame, the Data line Data outputs the second Data voltage Vdata (Vdata is greater than Vref), and the potential of the first node G1 becomes Vdata, so that the first driving thin film transistor T2-1 is turned back on. The light emitting signal line EM outputs a low level signal, and the fifth switching transistor T5 is turned off. Due to the coupling between the capacitor C1 and the capacitor C2, the voltage of the second node S1 is affected by the potential change of the first node G1, and the voltage change amount of S1 is Δv1= (Vdata-Vref) ×c1/(c1+c2), where the potential VS1 of the second node S1=vref-Vth 1+Δv1. The first light emitting device OLED1 and the second light emitting device OLED2 still do not emit light at this stage.
As shown in fig. 12, in the light emitting period IV of the nth frame, the first Scan line Scan1 outputs a low level signal, the first switching tube T1-1 is turned off, and the second switching tube T1-2 is turned on. The Data line Data outputs the low potential voltage VL, and the second driving thin film transistor T2-2 remains in an off state. The light emitting signal line EM outputs a high level signal, the fifth switching transistor T5 is turned on, the capacitor C1 discharges to the gate electrode of the first driving thin film transistor T2-1, the first driving thin film transistor T2-1 is turned on, the second scan line ODD outputs a high level signal, the third switching transistor T3 is turned on, and the first light emitting device OLED1 emits light. At this time, the voltage of S1 is vss+vold1, the voltage variation of S1 is vss+vold1- (Vref-Vth 1+Δv1), and the voltage variation of G1 is equal to the voltage variation of S1 due to the coupling effect of the capacitor, and at this time, the voltage of G1 is vdata+vss+vold1- (Vref-Vth 1+Δv1).
The voltage vgs=vg1-vs1=vdata- (Vref-Vth 1+Δv1) of the gate electrode to the source electrode of the first driving thin film transistor T2-1. The driving current calculation formula is as follows:
IOLED1＝1/2μnCoxW/L(Vgs–Vth1)2
＝1/2μnCoxW/L(Vdata–Vref-ΔV1)2
＝1/2μnCoxW/L[(Vdata–Vref)*C2/(C1+C2)]2
Wherein I OLED1 is the driving current of the first light-emitting device OLED1, mu n is the electron mobility of the first driving thin film transistor T2-1, C ox is the capacitance per unit area of the gate oxide layer of the first driving thin film transistor T2-1, and W/L is the width-to-length ratio of the first driving thin film transistor T2-1.
According to the above formula, the driving current of the first light emitting device OLED1 is independent of the threshold voltage of the first driving thin film transistor T2-1 and the voltage of the first power supply VDD, so that the influence of the threshold voltage drift of the first driving thin film transistor T2-1 on the driving current of the first light emitting device OLED1 can be eliminated, the image quality of the display panel can be improved, the difference of the driving currents of the light emitting devices caused by the difference of the distances between the first power supply VDD and the light emitting devices can be reduced, and the uniformity of the brightness of the display screen can be improved.
As shown in fig. 13, in the reset phase I of the n+1th frame, the first Scan line Scan1 outputs a low level signal, the first switching tube T1-1 is turned off, and the second switching tube T1-2 is turned on. The Data line Data outputs the first Data voltage Vref, resets the voltage of the third node G2, and turns on the second driving thin film transistor T2-2. The light emitting signal line EM outputs a high level signal, the fifth switching transistor T5 is turned on, the first power supply VDD writes a low voltage Vsus, and the voltage of the fourth node S2 is reset. The voltage vg2=vref at the third node G2 and vs2=vsus at the fourth node S2 in this stage. Meanwhile, the second scan line ODD and the third scan line EVEN output low-level scan signals, the third switching tube T3 and the fourth switching tube T4 are turned off, and the first light emitting device OLED1 and the second light emitting device OLED2 do not emit light.
As shown in fig. 14, in the compensation stage II of the n+1th frame, the potential output by each signal line is consistent with that of the reset stage, the first power supply VDD writes the high potential voltage VDD, continuously charges the fourth node S2, and when the voltage at S2 rises to Vref-Vth2, the second driving thin film transistor T2-2 reaches the critical cut-off. The voltage vs2=vref-Vth 2 of the fourth node S2 in this stage, where Vth2 is the threshold voltage of the second driving thin film transistor T2-2. At this stage the first light emitting device OLED1 and the second light emitting device OLED2 still do not emit light.
As shown in fig. 15, in the writing period III of the n+1th frame, the Data line Data outputs the second Data voltage Vdata, the potential of the third node G2 becomes Vdata, and the second driving thin film transistor T2-2 is turned back on. The light emitting signal line EM outputs a low level signal, and the fifth switching transistor T5 is turned off. Due to the coupling between the capacitor C3 and the capacitor C4, the voltage of the fourth node S2 is affected by the potential change of the third node G2, and the voltage change amount of the fourth node S2 is Δv2= (Vdata-Vref) ×c3/(c3+c4), where the potential of the fourth node S2 is vs2=vref-Vth 2+Δv2. The first light emitting device OLED1 and the second light emitting device OLED2 still do not emit light at this stage.
As shown in fig. 16, in the light emitting period IV of the n+1th frame, the first Scan line Scan1 outputs a high level signal, the first switching tube T1-1 is turned on, and the second switching tube T1-2 is turned off. The Data line Data outputs the low potential voltage VL, and the first driving thin film transistor T2-1 remains in an off state. The light emitting signal line EM outputs a high level signal, the fifth switching transistor T5 is turned on, the capacitor C3 discharges to the gate electrode of the second driving thin film transistor T2-2, the second driving thin film transistor T2-2 is turned on, the third scanning line EVEN outputs a high level signal, the fourth switching transistor T4 is turned on, and the second light emitting device OLED2 emits light. At this time, the voltage of S2 is vss+vold2, the voltage variation of S2 is vss+vold2- (Vref-Vth 2+Δv2), and the voltage variation of G2 is equal to the voltage variation of S2 due to the coupling effect of the capacitor, and at this time, the voltage of G2 is vdata+vss+vold2- (Vref-Vth 2+Δv2).
The voltage vgs=vg2-vs2=vdata- (Vref-Vth 2+Δv2) of the gate electrode to the source electrode of the second driving thin film transistor T2-2. The driving current calculation formula is as follows:
IOLED1＝1/2μnCoxW/L(Vgs–Vth2)2
＝1/2μnCoxW/L(Vdata–Vref-ΔV2)2
＝1/2μnCoxW/L[(Vdata–Vref)*C3/(C3+C4)]2
wherein I OLED1 is the driving current of the second light-emitting device OLED2, μ n is the electron mobility of the second driving thin film transistor T2-2, C ox is the capacitance per unit area of the gate oxide layer of the second driving thin film transistor T2-2, and W/L is the aspect ratio of the second driving thin film transistor T2-2.
According to the above formula, the driving current of the second light emitting device OLED2 is independent of the threshold voltage of the second driving thin film transistor T2-2 and the voltage of the first power supply VDD, so that the influence of the threshold voltage drift of the second driving thin film transistor T2-2 on the driving current of the second light emitting device OLED2 can be eliminated, the image quality of the display panel can be improved, the difference of the driving currents of the light emitting devices caused by the difference of the distances between the first power supply VDD and the light emitting devices can be reduced, and the uniformity of the brightness of the display screen can be improved.
The technical scheme provided by the embodiment of the application comprises a plurality of sub-pixels, wherein each sub-pixel comprises a first anode, a second anode, a pixel definition layer, a first light emitting device and a second light emitting device. The first anode and the second anode are arranged at intervals, the first light emitting device is positioned above the first anode, the second light emitting device is positioned above the second anode, the first light emitting device and the second light emitting device are alternately conducted in different light emitting stages, and the pixel defining layer is arranged around the first light emitting device and the second light emitting device. In the above technical solution, for each sub-pixel of the display panel, since the first light emitting device and the second light emitting device are alternately turned on in different light emitting stages, that is, only the first light emitting device or the second light emitting device emits light in each light emitting stage, compared with the current light emitting device emitting light in each light emitting stage, the light emitting duration of the first light emitting device and the second light emitting device in the present solution is smaller than the light emitting duration of the current light emitting device in unit time, and the light emitting device gradually ages with the increase of the light emitting duration, that is, the shorter the light emitting duration of the light emitting device in unit time, the slower the aging speed of the light emitting device, so the solution can delay the aging of the light emitting device and prolong the service life of the light emitting device.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
In addition, the dimensional relationships between the components in the drawings are merely illustrative, and do not reflect actual dimensional relationships between the components.
In the description of the present application, the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus are not to be construed as limiting the present application.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art in a specific case.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
In the description of the present application, unless otherwise indicated, "/" means that the objects associated in tandem are in a "or" relationship, e.g., A/B may represent A or B; the "and/or" in the present application is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate: there are three cases, a alone, a and B together, and B alone, wherein a, B may be singular or plural.
Also, in the description of the present application, unless otherwise indicated, "a plurality" means two or more than two. "at least one of the following" or similar expressions thereof, means any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.
Furthermore, in the description of the present specification and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims (8)

1. A pixel structure, comprising: a plurality of sub-pixels, the sub-pixels including, for each sub-pixel, a first anode, a second anode, a pixel defining layer, a first light emitting device, and a second light emitting device;
The first anode and the second anode are arranged at intervals, the first light-emitting device is positioned above the first anode, the second light-emitting device is positioned above the second anode, and the first light-emitting device and the second light-emitting device are alternately conducted in different light-emitting stages;
The pixel defining layer is disposed around the first light emitting device and the second light emitting device;
The first light-emitting device and the second light-emitting device share a plurality of functional structure layers, each functional structure layer comprises a hole transport layer, a light-emitting layer, an electron transport layer and a cathode, which are sequentially arranged from bottom to top, the thickness of a first area of the light-emitting layer is larger than that of a second area and a third area, the first area is positioned between the first anode and the second anode, the second area is positioned above the first anode, and the third area is positioned above the second anode.
2. The pixel structure of claim 1, wherein the first light emitting device and the second light emitting device are spaced apart.
3. The pixel structure of claim 1, wherein the sub-pixel further comprises an auxiliary cathode layer located at a spaced-apart region of the first anode and the second anode and laterally below the first anode and the second anode.
4. A pixel structure according to any one of claims 1-3, wherein the first light emitting device and the second light emitting device emit light of the same color.
5. A pixel driving circuit for driving a pixel structure according to any one of claims 1-4, comprising: the device comprises a data input circuit, a first energy storage circuit, a first switch circuit, a first light emitting control circuit, a second energy storage circuit, a second switch circuit, a second light emitting control circuit and a third switch circuit;
The first output end of the data input circuit is electrically connected with the control end of the first light-emitting control circuit, the second output end of the data input circuit is electrically connected with the control end of the second light-emitting control circuit, and the data input circuit is used for alternately outputting data voltages to the control end of the first light-emitting control circuit and the control end of the second light-emitting control circuit in non-light-emitting phases of different light-emitting periods;
the first energy storage circuit is connected between the control end and the output end of the first light-emitting control circuit, and the second energy storage circuit is connected between the control end and the output end of the second light-emitting control circuit;
The input ends of the first light-emitting control circuit and the second light-emitting control circuit are electrically connected with a first power supply through the third switch circuit, the output end of the first light-emitting control circuit is electrically connected with the anode of a first light-emitting device through the first switch circuit, the output end of the second light-emitting control circuit is electrically connected with the anode of a second light-emitting device through the second switch circuit, the cathode of the first light-emitting device and the cathode of the second light-emitting device are electrically connected with a second power supply, the first light-emitting control circuit is used for outputting a first driving current to the first light-emitting device in a light-emitting stage, and the second light-emitting control circuit is used for outputting a second driving current to the second light-emitting device in a light-emitting stage;
the first switch circuit and the second switch circuit are turned off in a non-light-emitting stage and are alternately turned on in different light-emitting stages.
6. The pixel driving circuit according to claim 5, wherein in each of the alternate on periods, the number of on frames of the first light emission control circuit and the number of on frames of the second light emission control circuit are each N frames, N being a positive integer.
7. A circuit according to claim 5 or 6, wherein the pixel driving circuit further comprises: the first voltage stabilizing circuit is connected to the output end of the first light emitting control circuit and is electrically connected with the second power supply; the second voltage stabilizing circuit is connected with the output end of the second light-emitting control circuit and is electrically connected with the second power supply.
8. A display panel comprising a substrate, a driving layer and a plurality of pixel structures according to any one of claims 1-4, the driving layer being located above the substrate, the pixel structures being located above the driving layer.
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