CN116995096A - Planar MOSFET device and preparation method thereof - Google Patents
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- 238000002360 preparation method Methods 0.000 title abstract description 3
- 239000000758 substrate Substances 0.000 claims abstract description 134
- 210000000746 body region Anatomy 0.000 claims abstract description 38
- 230000005669 field effect Effects 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 153
- 230000000670 limiting effect Effects 0.000 claims description 55
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 36
- 238000005468 ion implantation Methods 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 22
- 239000011229 interlayer Substances 0.000 claims description 20
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
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- H10D12/031—Manufacture or treatment of IGBTs
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
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Abstract
本发明提供了平面型MOSFET器件及其制备方法。平面型MOSFET器件包括：第一外延层设置在第一导电类型衬底的一个表面上；第二外延层设置在第一外延层远离第一导电类型衬底的表面上；结型场效应晶体管设置在第二外延层中；第二导电类型阱区位于第二外延层中，且围绕结型场效应晶体管设置；第一导电类型源区位于第二导电类型阱区中的上部，第一导电类型源区与结型场效应晶体管之间区域为沟道；第二导电类型体区位于第二导电类型阱区中，第二导电类型体区的上表面与第一导电类型衬底之间的垂直间距小于等于第一导电类型源区的下表面与第一导电类型衬底之间的垂直间距。该平面型器件的元胞尺寸较小，可有效提升平面型器件的效率。
The invention provides a planar MOSFET device and a preparation method thereof. The planar MOSFET device includes: a first epitaxial layer is disposed on a surface of a first conductive type substrate; a second epitaxial layer is disposed on a surface of the first epitaxial layer away from the first conductive type substrate; a junction field effect transistor is disposed In the second epitaxial layer; the second conductive type well region is located in the second epitaxial layer and is arranged around the junction field effect transistor; the first conductive type source region is located in the upper part of the second conductive type well region, and the first conductive type The area between the source region and the junction field effect transistor is a channel; the second conductive type body region is located in the second conductive type well region, and the vertical line between the upper surface of the second conductive type body region and the first conductive type substrate The spacing is less than or equal to the vertical spacing between the lower surface of the first conductive type source region and the first conductive type substrate. The cell size of the planar device is smaller, which can effectively improve the efficiency of the planar device.
Description
技术领域Technical field
本发明涉及半导体技术领域，具体的，涉及平面型MOSFET器件及其制备方法。The present invention relates to the field of semiconductor technology, specifically, to a planar MOSFET device and a preparation method thereof.
背景技术Background technique
碳化硅MOSFET是全碳化硅功率模块的重要组成部分，其效率和可靠性至关重要。缩减元胞尺寸是提升碳化硅MOSFET效率的有效手段，然而当平面型元胞尺寸缩减至一定程度后，工艺加工会制约元胞尺寸的进一步缩减。根据文献报导，碳化硅同时进行高剂量N型和P型掺杂的区域，无法形成良好的N型和P型欧姆接触，因此需要在体区区域阻挡源区的离子注入，即需要在进行源区离子注入时，在体区区域的表面保留一个掩膜墩，最终使体区和源区的离子注入区域不发生重叠。但是这个掩膜墩的存在，阻碍了元胞尺寸的有效缩减。Silicon carbide MOSFET is an important component of all-silicon carbide power modules, and its efficiency and reliability are crucial. Reducing the cell size is an effective means to improve the efficiency of silicon carbide MOSFETs. However, when the planar cell size is reduced to a certain level, process processing will restrict further reduction of the cell size. According to literature reports, areas where silicon carbide is doped with high doses of N-type and P-type at the same time cannot form good N-type and P-type ohmic contacts. Therefore, it is necessary to block the ion implantation of the source region in the body region, that is, the source region needs to be During area ion implantation, a mask pier is retained on the surface of the body area, so that the ion implantation areas of the body area and the source area do not overlap. However, the existence of this mask pier hinders the effective reduction of cell size.
此外，由于碳化硅MOSFET向着高电流密度的方向发展，外延浓度逐步增加，场限环终端结构的保护效果逐渐变得困难。一是体现在所需的环间距随着外延浓度的增加而逐步降低，增加了工艺难度；二是表面电场强度随着外延浓度的增加而逐步变大，弱化了终端结构的可靠性。因此，场限环也需进一步改进，以便实现可靠的耐压保护效果。In addition, as silicon carbide MOSFETs develop towards high current density, the epitaxial concentration gradually increases, and the protective effect of the field-limited ring terminal structure gradually becomes difficult. First, the required ring spacing gradually decreases with the increase of epitaxial concentration, which increases the difficulty of the process; second, the surface electric field intensity gradually increases with the increase of epitaxial concentration, weakening the reliability of the terminal structure. Therefore, the field limiting ring also needs to be further improved in order to achieve reliable voltage protection effect.
发明内容Contents of the invention
本发明旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本发明的一个目的在于提出一种平面型MOSFET器件，该平面型MOSFET器件的元胞尺寸较小，提升其效率。The present invention aims to solve one of the technical problems in the related art, at least to a certain extent. To this end, one object of the present invention is to provide a planar MOSFET device, which has a smaller cell size and improves its efficiency.
在本发明的一方面，本发明提供了一种平面型MOSFET器件。根据本发明的实施例，平面型MOSFET器件包括：第一导电类型衬底，所述第一导电类型衬底具有有源区和终端区；第一外延层，所述第一外延层设置在所述第一导电类型衬底的一个表面上；第二外延层，所述第二外延层设置在所述第一外延层远离所述第一导电类型衬底的表面上；结型场效应晶体管，所述结型场效应晶体管设置在所述第二外延层中，且在所述第一导电类型衬底上的正投影位于所述有源区的中间；第二导电类型阱区，所述第二导电类型阱区位于所述第二外延层中，且围绕所述结型场效应晶体管设置，且在所述第一导电类型衬底上的正投影位于所述有源区；第一导电类型源区，所述第一导电类型源区位于所述第二导电类型阱区中的上部，所述第一导电类型源区的边界位于所述第二导电类型阱区的内部，且所述第一导电类型源区远离所述第一导电类型衬底的表面与所述第二导电类型阱区远离所述第一导电类型衬底的表面齐平，其中，所述第一导电类型源区与所述结型场效应晶体管之间区域为沟道；第二导电类型体区，所述第二导电类型体区位于所述第二导电类型阱区中，所述第二导电类型体区远离所述第一导电类型衬底的表面与所述第一导电类型衬底之间的垂直间距小于等于所述第一导电类型源区靠近所述第一导电类型衬底的表面与所述第一导电类型衬底之间的垂直间距。由此，该平面型MOSFET器件的元胞尺寸较小，可有效提升平面型MOSFET器件的效率。In one aspect of the invention, the invention provides a planar MOSFET device. According to an embodiment of the present invention, a planar MOSFET device includes: a first conductive type substrate having an active region and a terminal region; a first epitaxial layer, the first epitaxial layer is disposed on the on one surface of the first conductivity type substrate; a second epitaxial layer, the second epitaxial layer is disposed on a surface of the first epitaxial layer away from the first conductivity type substrate; a junction field effect transistor, The junction field effect transistor is disposed in the second epitaxial layer, and an orthographic projection on the first conductive type substrate is located in the middle of the active region; a second conductive type well region, the third conductive type well region; A two conductivity type well region is located in the second epitaxial layer and is arranged around the junction field effect transistor, and an orthographic projection on the first conductivity type substrate is located in the active region; the first conductivity type source region, the first conductivity type source region is located in the upper part of the second conductivity type well region, the boundary of the first conductivity type source region is located inside the second conductivity type well region, and the third conductivity type well region A surface of a conductive type source region away from the first conductive type substrate is flush with a surface of the second conductive type well region away from the first conductive type substrate, wherein the first conductive type source region is flush with the surface of the second conductive type well region away from the first conductive type substrate. The area between the junction field effect transistors is a channel; a second conductive type body region is located in the second conductive type well region, and the second conductive type body region is far away from the second conductive type well region. The vertical distance between the surface of the first conductive type substrate and the first conductive type substrate is less than or equal to the surface of the first conductive type source region close to the first conductive type substrate and the first conductive type substrate. Vertical spacing between type substrates. As a result, the cell size of the planar MOSFET device is smaller, which can effectively improve the efficiency of the planar MOSFET device.
根据本发明的实施例，平面型MOSFET器件还包括：多个间隔设置的第一浮空场限环，所述第一浮空场限环位于所述第一外延层的上部，且在所述第一导电类型衬底上的正投影位于所述终端区内，所述第一浮空场限环远离所述第一导电类型衬底的表面与所述第一外延层远离所述第一导电类型衬底的表面齐平；多个间隔设置的第二浮空场限环，所述第二浮空场限环位于所述第二外延层中，且所述第二浮空场限环在所述第一导电类型衬底上的正投影与所述第一浮空场限环在所述第一导电类型衬底上的正投影重叠。According to an embodiment of the present invention, the planar MOSFET device further includes: a plurality of first floating field limiting rings arranged at intervals, the first floating field limiting rings are located on the upper part of the first epitaxial layer, and on the The orthographic projection on the first conductive type substrate is located in the terminal area, the first floating field limiting ring is away from the surface of the first conductive type substrate, and the first epitaxial layer is away from the first conductive layer. The surface of the type substrate is flush; a plurality of second floating field limiting rings are arranged at intervals, the second floating field limiting rings are located in the second epitaxial layer, and the second floating field limiting rings are in The orthographic projection on the first conductive type substrate overlaps with the orthographic projection of the first floating field limit ring on the first conductive type substrate.
根据本发明的实施例，所述第二浮空场限环的离子注入深度大于等于所述第二外延层的厚度。According to an embodiment of the present invention, the ion implantation depth of the second floating field limiting ring is greater than or equal to the thickness of the second epitaxial layer.
根据本发明的实施例，所述第一浮空场限环和所述第二浮空场限环还满足以下条件：所述第一浮空场限环和所述第二浮空场限环均为第二导电类型；所述第一浮空场限环靠近所述第一导电类型衬底的表面与所述第二浮空场限环远离所述第一导电类型衬底的表面之间的垂直间距为1～2微米。According to an embodiment of the present invention, the first floating field limited ring and the second floating field limited ring also satisfy the following conditions: the first floating field limited ring and the second floating field limited ring Both are of the second conductivity type; between the surface of the first floating field limitation ring close to the first conductivity type substrate and the surface of the second floating field limitation ring away from the first conductivity type substrate The vertical spacing is 1 to 2 microns.
根据本发明的实施例，所述沟道的长度小于等于0.4微米。According to an embodiment of the present invention, the length of the channel is less than or equal to 0.4 microns.
根据本发明的实施例，平面型MOSFET器件还还包括：栅介质层，所述栅介质层设置在所述第二外延层远离所述第一导电类型衬底的表面上，且覆盖所述结型场效应晶体管、所述沟道和部分所述第一导电类型源区的表面；多晶硅栅电极，所述多晶硅栅电极设置在所述栅介质层远离所述第一导电类型衬底的表面上；层间介质层，所述层间介质层覆盖所述多晶硅栅电极远离所述第一导电类型衬底的表面以及所述第二外延层远离所述第一导电类型衬底的表面，所述层间介质层具有贯穿所述层间介质层的接触孔，所述接触孔暴露出所述第二导电类型体区的表面以及部分所述第一导电类型源区；欧姆接触金属层，所述欧姆接触金属层位于所述接触孔内，与所述接触孔暴露出的所述第二导电类型体区的表面和部分所述第一导电类型源区形成欧姆接触；源极金属和漏极金属，所述源极金属通过所述接触孔与所述欧姆接触金属层电性连接，所述漏极金属位于所述第一导电类型衬底远离所述第一外延层的表面。According to an embodiment of the present invention, the planar MOSFET device further includes: a gate dielectric layer, which is disposed on a surface of the second epitaxial layer away from the first conductive type substrate and covers the junction. type field effect transistor, the channel and part of the surface of the first conductivity type source region; a polysilicon gate electrode, the polysilicon gate electrode is disposed on the surface of the gate dielectric layer away from the first conductivity type substrate ; Interlayer dielectric layer, the interlayer dielectric layer covers the surface of the polysilicon gate electrode away from the first conductive type substrate and the surface of the second epitaxial layer away from the first conductive type substrate, the The interlayer dielectric layer has a contact hole penetrating the interlayer dielectric layer, and the contact hole exposes the surface of the second conductive type body region and part of the first conductive type source region; the ohmic contact metal layer, the The ohmic contact metal layer is located in the contact hole and forms ohmic contact with the surface of the second conductive type body region and part of the first conductive type source region exposed by the contact hole; source metal and drain metal , the source metal is electrically connected to the ohmic contact metal layer through the contact hole, and the drain metal is located on a surface of the first conductive type substrate away from the first epitaxial layer.
在本发明的另一方面，本发明提供了一种制备前面所述的平面型MOSFET器件的方法。根据本发明的实施例，制备前面所述的平面型MOSFET器件的方法包括：提供第一导电类型衬底，所述第一导电类型衬底具有有源区和终端区；在所述第一导电类型衬底的一个表面上外延生长第一外延层；在所述第一外延层远离所述第一导电类型衬底的表面上外延生长第二外延层；在所述第二外延层远离所述第一导电类型衬底的表面上所述有源区内设置阱区掩膜，通过对所述有源区中未被所述阱区掩膜覆盖的所述第二外延层进行第一离子注入形成第二导电类型阱区，被所述阱区掩膜覆盖的所述第二外延层部分构成结型场效应晶体管，所述结型场效应晶体管在所述第一导电类型衬底上的正投影位于所述有源区的中间，所述第二导电类型阱区围绕所述结型场效应晶体管设置；在所述阱区掩膜的侧壁生长多晶硅侧壁，所述多晶硅侧壁覆盖所述第二导电类型阱区的部分表面；以所述阱区掩膜和所述多晶硅侧壁为掩膜版，对未被所述掩膜版覆盖的所述第二导电类型阱区进行第二离子注入形成第一导电类型源区结构层；将所述第一导电类型源区结构层划分为第一部分和第二部分，所述第二部分位于所述第一部分远离所述结型场效应晶体管的一侧，设置掩膜层覆盖所述第一部分，刻蚀去除至少所述第二部分的厚度，所述第一部分构成第一导电类型源区，其中，所述第一导电类型源区与所述结型场效应晶体管之间区域为沟道；向所述第二部分正对应的所述第二导电类型阱区进行第三离子注入形成第二导电类型体区，所述第二导电类型体区远离所述第一导电类型衬底的表面与所述第一导电类型衬底之间的垂直间距小于等于所述第一导电类型源区靠近所述第一导电类型衬底的表面与所述第一导电类型衬底之间的垂直间距。In another aspect of the present invention, the present invention provides a method of preparing the planar MOSFET device described above. According to an embodiment of the present invention, a method for preparing the aforementioned planar MOSFET device includes: providing a first conductive type substrate having an active region and a terminal region; A first epitaxial layer is epitaxially grown on one surface of the first conductive type substrate; a second epitaxial layer is epitaxially grown on a surface of the first epitaxial layer away from the first conductive type substrate; and the second epitaxial layer is epitaxially grown away from the first conductive type substrate. A well region mask is provided in the active region on the surface of the first conductive type substrate, and a first ion implantation is performed on the second epitaxial layer in the active region that is not covered by the well region mask. A second conductivity type well region is formed, and the portion of the second epitaxial layer covered by the well region mask constitutes a junction field effect transistor. The junction field effect transistor has a positive electrode on the first conductivity type substrate. The projection is located in the middle of the active area, and the second conductive type well area is arranged around the junction field effect transistor; polysilicon sidewalls are grown on the side walls of the well area mask, and the polysilicon sidewalls cover all Part of the surface of the second conductivity type well region; using the well region mask and the polysilicon sidewall as a mask, perform a second step on the second conductivity type well region that is not covered by the mask. Ion implantation forms a first conductive type source region structural layer; the first conductive type source region structural layer is divided into a first part and a second part, the second part is located in the first part away from the junction field effect transistor On one side, a mask layer is provided to cover the first part, and at least the thickness of the second part is removed by etching. The first part constitutes a first conductive type source region, wherein the first conductive type source region is connected to the first conductive type source region. The region between the junction field effect transistors is a channel; a third ion implantation is performed into the second conductive type well region corresponding to the second part to form a second conductive type body region, and the second conductive type body region A vertical distance between a surface of a region far away from the first conductive type substrate and the first conductive type substrate is less than or equal to a surface of the first conductive type source region close to the first conductive type substrate and the first conductive type substrate. Vertical spacing between first conductivity type substrates.
根据本发明的实施例，制备前面所述的平面型MOSFET器件的方法还包括：在所述终端区，向所述第一外延层的上部通过第四离子注入形成多个间隔设置的第一浮空场限环；在所述终端区，向所述第二外延层的上部通过第五离子注入形成多个间隔设置的第二浮空场限环，所述第二浮空场限环在所述第一导电类型衬底上的正投影与所述第一浮空场限环在所述第一导电类型衬底上的正投影重叠。According to an embodiment of the present invention, the method for preparing the planar MOSFET device described above further includes: in the terminal region, forming a plurality of first floats arranged at intervals through fourth ion implantation into the upper part of the first epitaxial layer. Empty field limiting rings; in the terminal area, a plurality of second floating field limiting rings arranged at intervals are formed through fifth ion implantation into the upper part of the second epitaxial layer, and the second floating field limiting rings are located at the The orthographic projection on the first conductive type substrate overlaps with the orthographic projection of the first floating field limit ring on the first conductive type substrate.
根据本发明的实施例，所述第五离子注入的深度大于等于所述第二外延层的厚度。According to an embodiment of the present invention, the depth of the fifth ion implantation is greater than or equal to the thickness of the second epitaxial layer.
根据本发明的实施例，制备前面所述的平面型MOSFET器件的方法还包括：在所述第二外延层远离所述第一导电类型衬底的表面上形成栅介质层，且所述栅介质层覆盖所述结型场效应晶体管、所述沟道和部分所述第一导电类型源区的表面；在所述栅介质层远离所述第一导电类型衬底的表面上形成多晶硅栅电极；在所述多晶硅栅电极远离所述第一导电类型衬底的表面以及所述第二外延层远离所述第一导电类型衬底的表面上层间介质层，并在所述层间介质层中形成具有贯穿所述层间介质层的接触孔，所述接触孔暴露出所述第二导电类型体区的表面以及部分所述第一导电类型源区；在所述接触孔内形成欧姆接触金属层，所述欧姆接触金属层与所述接触孔暴露出的所述第二导电类型体区的表面和部分所述第一导电类型源区形成欧姆接触；在所述接触孔中形成源极金属，使得所述源极金属通过所述接触孔与所述欧姆接触金属层电性连接；在所述第一导电类型衬底远离所述第一外延层的表面上形成漏极金属。According to an embodiment of the present invention, the method for preparing the aforementioned planar MOSFET device further includes: forming a gate dielectric layer on a surface of the second epitaxial layer away from the first conductive type substrate, and the gate dielectric layer A layer covering the surface of the junction field effect transistor, the channel and part of the first conductivity type source region; forming a polysilicon gate electrode on the surface of the gate dielectric layer away from the first conductivity type substrate; An interlayer dielectric layer is formed on the surface of the polysilicon gate electrode away from the first conductivity type substrate and the surface of the second epitaxial layer away from the first conductivity type substrate, and in the interlayer dielectric layer Forming a contact hole penetrating the interlayer dielectric layer, the contact hole exposing the surface of the second conductive type body region and part of the first conductive type source region; forming an ohmic contact metal in the contact hole layer, the ohmic contact metal layer forms ohmic contact with the surface of the second conductive type body region exposed by the contact hole and part of the first conductive type source region; forming a source metal in the contact hole , so that the source metal is electrically connected to the ohmic contact metal layer through the contact hole; a drain metal is formed on a surface of the first conductive type substrate away from the first epitaxial layer.
附图说明Description of the drawings
本发明的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：The above and/or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:
图1是本发明一个实施例中平面型MOSFET器件的部分结构示意图；Figure 1 is a partial structural schematic diagram of a planar MOSFET device in one embodiment of the present invention;
图2是本发明另一个实施例中平面型MOSFET器件的部分结构示意图；Figure 2 is a partial structural schematic diagram of a planar MOSFET device in another embodiment of the present invention;
图3是本发明又一个实施例中平面型MOSFET器件的结构示意图；Figure 3 is a schematic structural diagram of a planar MOSFET device in another embodiment of the present invention;
图4是本发明又一个实施例中制备平面型MOSFET器件的结构流程图。Figure 4 is a structural flow chart for preparing a planar MOSFET device in yet another embodiment of the present invention.
具体实施方式Detailed ways
下面将结合实施例对本发明的方案进行解释。本领域技术人员将会理解，下面的实施例仅用于说明本发明，而不应视为限定本发明的范围。实施例中未注明具体技术或条件的，按照本领域内的文献所描述的技术或条件或者按照产品说明书进行。The solutions of the present invention will be explained below with reference to examples. Those skilled in the art will understand that the following examples are only used to illustrate the present invention and should not be regarded as limiting the scope of the present invention. If specific techniques or conditions are not specified in the examples, the techniques or conditions described in literature in the field or product instructions will be followed.
下面参考具体实施例，对本发明进行描述，需要说明的是，这些实施例仅仅是描述性的，而不以任何方式限制本发明。The present invention will be described below with reference to specific embodiments. It should be noted that these embodiments are only illustrative and do not limit the present invention in any way.
在本发明的一方面，本发明提供了一种平面型MOSFET器件。根据本发明的实施例，参照图1，平面型MOSFET器件包括：第一导电类型衬底100，第一导电类型衬底100具有有源区和终端区；第一外延层210，第一外延层210设置在第一导电类型衬底100的一个表面上；第二外延层220，第二外延层220设置在第一外延层210远离第一导电类型衬底100的表面上；结型场效应晶体管(JFET)300，结型场效应晶体管300设置在第二外延层220中，且在第一导电类型衬底100上的正投影位于有源区的中间；第二导电类型阱区410，第二导电类型阱区410位于第二外延层220中，且围绕结型场效应晶体管300设置，且在第一导电类型衬底100上的正投影位于有源区；第一导电类型源区420，第一导电类型源区420位于第二导电类型阱区410中的上部，第一导电类型源区420的边界位于第二导电类型阱区410的内部，且第一导电类型源区420远离第一导电类型衬底100的表面与第二导电类型阱区410远离第一导电类型衬底100的表面齐平，第一导电类型源区420与结型场效应晶体管300之间区域为沟道S；第二导电类型体区430，第二导电类型体区430位于第二导电类型阱区410中，第二导电类型体区430远离第一导电类型衬底100的表面与第一导电类型衬底100之间的垂直间距H1小于等于第一导电类型源区420靠近第一导电类型衬底100的表面与第一导电类型衬底100之间的垂直间距H2(图1中的(a)以H1＝H2为例，图1中的(b)以H1小于H2为例)。由于H1小于等于H2，所以在离子注入制备第二导电类型体区430时，需要预先将第二导电类型体区430正上方的材料刻蚀掉，即通过刻蚀去除第二导电类型体区430正上方的第一导电类型源区半导体材料，再进行离子注入，如此便可以避免第二导电类型体区430和第一导电类型源区420的重叠，如此可有效缩小该平面型MOSFET器件的元胞尺寸，进而有效提升平面型MOSFET器件的效率。总而言之，本发明的平面型MOSFET器件结构简洁，实现方法简单，可提升平面型MOSFET器件的元胞密度，增强单位面积导通电流的能力，提高终端的保护效率，获得高效率的平面型MOSFET器件。In one aspect of the invention, the invention provides a planar MOSFET device. According to an embodiment of the present invention, referring to Figure 1, a planar MOSFET device includes: a first conductive type substrate 100 having an active region and a terminal region; a first epitaxial layer 210, a first epitaxial layer 210 is disposed on a surface of the first conductive type substrate 100; a second epitaxial layer 220, the second epitaxial layer 220 is disposed on a surface of the first epitaxial layer 210 away from the first conductive type substrate 100; a junction field effect transistor (JFET) 300, the junction field effect transistor 300 is disposed in the second epitaxial layer 220, and the orthographic projection on the first conductive type substrate 100 is located in the middle of the active area; the second conductive type well region 410, the second The conductive type well region 410 is located in the second epitaxial layer 220 and is arranged around the junction field effect transistor 300, and the orthographic projection on the first conductive type substrate 100 is located in the active region; the first conductive type source region 420, A conductive type source region 420 is located in the upper part of the second conductive type well region 410. The boundary of the first conductive type source region 420 is located inside the second conductive type well region 410, and the first conductive type source region 420 is away from the first conductive type well region 410. The surface of the type substrate 100 is flush with the surface of the second conductivity type well region 410 away from the first conductivity type substrate 100, and the area between the first conductivity type source region 420 and the junction field effect transistor 300 is the channel S; Two conductive type body regions 430, the second conductive type body region 430 is located in the second conductive type well region 410, the second conductive type body region 430 is away from the surface of the first conductive type substrate 100 and the first conductive type substrate 100 The vertical spacing H1 between the first conductive type source region 420 and the first conductive type substrate 100 is less than or equal to the vertical spacing H2 between the surface of the first conductive type source region 420 and the first conductive type substrate 100 ((a) in FIG. 1 is represented by H1=H2 For example, (b) in Figure 1 takes H1 to be smaller than H2 as an example). Since H1 is less than or equal to H2, when preparing the second conductive type body region 430 by ion implantation, the material directly above the second conductive type body region 430 needs to be etched away in advance, that is, the second conductive type body region 430 is removed by etching. The semiconductor material of the first conductive type source region directly above is then ion implanted, so that the overlap of the second conductive type body region 430 and the first conductive type source region 420 can be avoided, which can effectively reduce the components of the planar MOSFET device. cell size, thereby effectively improving the efficiency of planar MOSFET devices. All in all, the planar MOSFET device of the present invention has a simple structure and a simple implementation method. It can increase the cell density of the planar MOSFET device, enhance the ability to conduct current per unit area, improve the protection efficiency of the terminal, and obtain a high-efficiency planar MOSFET device. .
根据本发明的实施，上述第一导电类型和第二导电类型可以为N型半导体和P型半导体，即第一导电类型为N型半导体，第二导电类型为P型半导体，或者，第一导电类型为P型半导体，第二导电类型为N型半导体。According to the implementation of the present invention, the above-mentioned first conductivity type and second conductivity type may be N-type semiconductor and P-type semiconductor, that is, the first conductivity type is N-type semiconductor and the second conductivity type is P-type semiconductor, or the first conductivity type is N-type semiconductor and the second conductivity type is P-type semiconductor. The first conductivity type is P-type semiconductor, and the second conductivity type is N-type semiconductor.
根据本发明的实施例，第一导电类型衬底100的材料可以为碳化硅、氮化镓、氧化镓、氮化硼、硅材料中的一种。在本发明的一些具体实施例中，第一导电类型衬底100的材料可以为碳化硅，第一导电类型衬底100为第一导电类型碳化硅衬底。According to embodiments of the present invention, the material of the first conductive type substrate 100 may be one of silicon carbide, gallium nitride, gallium oxide, boron nitride, and silicon materials. In some specific embodiments of the present invention, the material of the first conductive type substrate 100 may be silicon carbide, and the first conductive type substrate 100 is a first conductive type silicon carbide substrate.
进一步的，第二外延层的厚度为0.5～1微米，如此，可以有足够的空间满足第二导电类型体区430和第一导电类型源区420在垂直方向上的错位设置，且不会影响第二导电类型阱区410的性能。Furthermore, the thickness of the second epitaxial layer is 0.5 to 1 micron. In this way, there can be enough space to accommodate the misalignment of the second conductive type body region 430 and the first conductive type source region 420 in the vertical direction without affecting the Performance of the second conductivity type well region 410 .
根据本发明的实施例，如图1所示，第一导电类型源区420的边界位于第二导电类型阱区410的内部，即第一导电类型源区420与结型场效应晶体管300之间具有一定厚度的第二导电类型阱区410，第一导电类型源区420与结型场效应晶体管300之间区域构成沟道S，沟道的长度小于等于0.4微米，比如沟道的长度为0.4微米、0.3微米、0.2微米、0.1微米等。According to an embodiment of the present invention, as shown in FIG. 1 , the boundary of the first conductivity type source region 420 is located inside the second conductivity type well region 410 , that is, between the first conductivity type source region 420 and the junction field effect transistor 300 The second conductivity type well region 410 has a certain thickness, the region between the first conductivity type source region 420 and the junction field effect transistor 300 forms a channel S. The length of the channel is less than or equal to 0.4 microns, for example, the length of the channel is 0.4 Micron, 0.3 micron, 0.2 micron, 0.1 micron, etc.
根据本发明的实施例，参照图2，平面型MOSFET器件还包括：多个间隔设置的第一浮空场限环510，第一浮空场限环510位于第一外延层210的上部，且在第一导电类型衬底100上的正投影位于终端区内，第一浮空场限环510远离第一导电类型衬底100的表面与第一外延层210远离第一导电类型衬底100的表面齐平；多个间隔设置的第二浮空场限环520，第二浮空场限环520位于第二外延层220中，且第二浮空场限环520在第一导电类型衬底100上的正投影与第一浮空场限环510在第一导电类型衬底100上的正投影重叠。由此，第二浮空场限环520与第一浮空场限环510自对准，进而可以得到深度较深的浮空场限环，可以有效提高终端区的保护效率，并且降低半导体表面的电场强度，提高终端结构的可靠性，本发明通过“离子注入-二次外延-离子注入”的方法，实现较深的(1～2μm)浮空场限环结构，获得高效的终端保护结构。According to an embodiment of the present invention, referring to Figure 2, the planar MOSFET device further includes: a plurality of first floating field limiting rings 510 arranged at intervals, the first floating field limiting rings 510 are located on the upper part of the first epitaxial layer 210, and The orthographic projection on the first conductive type substrate 100 is located in the terminal area, the first floating field limiting ring 510 is away from the surface of the first conductive type substrate 100 and the first epitaxial layer 210 is away from the first conductive type substrate 100 The surface is flush; a plurality of second floating field limiting rings 520 are arranged at intervals, the second floating field limiting rings 520 are located in the second epitaxial layer 220, and the second floating field limiting rings 520 are on the first conductive type substrate The orthographic projection on 100 overlaps with the orthographic projection of the first floating field limiting ring 510 on the first conductive type substrate 100 . As a result, the second floating field limiting ring 520 and the first floating field limiting ring 510 are self-aligned, and thus a floating field limiting ring with a deeper depth can be obtained, which can effectively improve the protection efficiency of the terminal area and reduce the semiconductor surface area. The electric field strength improves the reliability of the terminal structure. The present invention uses the method of "ion implantation-secondary epitaxy-ion implantation" to achieve a deeper (1-2 μm) floating field-limited ring structure and obtain an efficient terminal protection structure. .
根据本发明的实施例，第二浮空场限环的离子注入深度大于等于第二外延层的厚度。即第二浮空场限环结深等于第二外延层的厚度，或者第二浮空场限环结深由第二外延层延伸至第一外延层，即第一浮空场限环与和第二浮空场限环有部分的交叠。由此，上述两种情况，两层的浮空场限环的每根环都一一对应相连，组合成一根较深的场限环(即第二浮空场限环远离所述第一导电类型衬底的表面与所述第一浮空场限环靠近所述第一导电类型衬底的表面之间的垂直间距为两层浮空场限环的深度)。According to an embodiment of the present invention, the ion implantation depth of the second floating field limiting ring is greater than or equal to the thickness of the second epitaxial layer. That is, the second floating field-limited ring junction depth is equal to the thickness of the second epitaxial layer, or the second floating field-limited ring junction depth extends from the second epitaxial layer to the first epitaxial layer, that is, the first floating field-limited ring and the sum The second floating field-limited ring partially overlaps. Therefore, in the above two cases, each ring of the two layers of floating field-limited rings is connected one-to-one, forming a deeper field-limited ring (that is, the second floating field-limited ring is far away from the first conductive field-limited ring). The vertical distance between the surface of the first conductive type substrate and the surface of the first floating field limiting ring close to the first conductive type substrate is the depth of two layers of floating field limiting rings).
进一步的，如图2所示，第二浮空场限环远离所述第一导电类型衬底的表面与所述第一浮空场限环靠近所述第一导电类型衬底的表面之间的垂直间距D(即两层浮空场限环的深度)为1～2微米。由此，通过增加浮空场限环的深度，可以有效提高终端区的保护效率，并且降低半导体表面的电场强度，提高终端结构的可靠性。Further, as shown in FIG. 2 , there is a gap between the surface of the second floating field limiting ring away from the first conductive type substrate and the surface of the first floating field limiting ring close to the first conductive type substrate. The vertical spacing D (that is, the depth of the two floating field limiting rings) is 1 to 2 microns. Therefore, by increasing the depth of the floating field limiting ring, the protection efficiency of the terminal area can be effectively improved, the electric field intensity on the semiconductor surface can be reduced, and the reliability of the terminal structure can be improved.
其中，第一浮空场限环的深度和第二浮空场限环的深度可以相等，可以不等，本领域技术人员根据工艺的具体情况灵活选择即可，在此不作限制要求。The depth of the first floating field limiting ring and the depth of the second floating field limiting ring may be equal or different. Those skilled in the art can flexibly choose according to the specific conditions of the process, and there is no restriction here.
根据本发明的实施例，第一浮空场限环和第二浮空场限环均为第二导电类型。According to an embodiment of the present invention, both the first floating field limiting ring and the second floating field limiting ring are of the second conductivity type.
根据本发明的实施例，参照图3，平面型MOSFET器件还还包括：栅介质层610，栅介质层610设置在第二外延层220远离第一导电类型衬底100的表面上，且覆盖结型场效应晶体管300、沟道和部分第一导电类型源区420的表面；多晶硅栅电极620，多晶硅栅电极620设置在栅介质层610远离第一导电类型衬底100的表面上；层间介质层630，层间介质层630覆盖多晶硅栅电极620远离第一导电类型衬底100的表面以及第二外延层220远离第一导电类型衬底100的表面，层间介质层630具有贯穿层间介质层630的接触孔，接触孔暴露出第二导电类型体区430的表面以及部分第一导电类型源区420的表面；欧姆接触金属层640，欧姆接触金属层640位于接触孔内，与接触孔暴露出的第二导电类型体区430的表面和部分第一导电类型源区420的表面形成欧姆接触；源极金属650和漏极金属660，源极金属650通过接触孔与欧姆接触金属层640电性连接，漏极金属660位于第一导电类型衬底100远离第一外延层210的表面。由此，可以获得高效率的平面型MOSFET器件。According to an embodiment of the present invention, referring to FIG. 3 , the planar MOSFET device further includes: a gate dielectric layer 610 . The gate dielectric layer 610 is disposed on the surface of the second epitaxial layer 220 away from the first conductive type substrate 100 and covers the junction. Type field effect transistor 300, the channel and part of the surface of the first conductivity type source region 420; the polysilicon gate electrode 620, the polysilicon gate electrode 620 is disposed on the surface of the gate dielectric layer 610 away from the first conductivity type substrate 100; interlayer dielectric Layer 630, the interlayer dielectric layer 630 covers the surface of the polysilicon gate electrode 620 away from the first conductive type substrate 100 and the surface of the second epitaxial layer 220 away from the first conductive type substrate 100, and the interlayer dielectric layer 630 has a penetrating interlayer dielectric. The contact hole of layer 630 exposes the surface of the second conductivity type body region 430 and part of the surface of the first conductivity type source region 420; the ohmic contact metal layer 640 is located in the contact hole and is connected to the contact hole. The exposed surface of the second conductive type body region 430 forms an ohmic contact with a portion of the surface of the first conductive type source region 420; the source metal 650 and the drain metal 660, the source metal 650 contacts the ohmic metal layer 640 through the contact hole. To be electrically connected, the drain metal 660 is located on the surface of the first conductive type substrate 100 away from the first epitaxial layer 210 . As a result, a high-efficiency planar MOSFET device can be obtained.
在本发明的另一方面，本发明提供了一种制备前面所述的平面型MOSFET器件的方法。根据本发明的实施例，参照图4，制备前面所述的平面型MOSFET器件的方法包括：In another aspect of the present invention, the present invention provides a method of preparing the planar MOSFET device described above. According to an embodiment of the present invention, referring to Figure 4, a method for preparing the aforementioned planar MOSFET device includes:
S1：提供第一导电类型衬底100，第一导电类型衬底100具有有源区和终端区；S1: Provide a first conductive type substrate 100. The first conductive type substrate 100 has an active area and a terminal area;
S2：在第一导电类型衬底100的一个表面上外延生长第一外延层210；S2: Epitaxially grow the first epitaxial layer 210 on one surface of the first conductive type substrate 100;
S3：在第一外延层210远离第一导电类型衬底100的表面上外延生长第二外延层220；S3: epitaxially grow the second epitaxial layer 220 on the surface of the first epitaxial layer 210 away from the first conductive type substrate 100;
S4：在第二外延层220远离第一导电类型衬底100的表面上有源区内设置阱区掩膜710，通过对有源区中未被阱区掩膜710覆盖的第二外延层220进行第一离子注入形成第二导电类型阱区410，被阱区掩膜710覆盖的第二外延层220部分构成结型场效应晶体管300，结型场效应晶体管300在第一导电类型衬底100上的正投影位于有源区的中间，第二导电类型阱区410围绕结型场效应晶体管300设置，如图4中的(a)；S4: Set the well region mask 710 in the active area on the surface of the second epitaxial layer 220 away from the first conductive type substrate 100, by covering the second epitaxial layer 220 in the active area that is not covered by the well area mask 710. The first ion implantation is performed to form the second conductivity type well region 410. The portion of the second epitaxial layer 220 covered by the well region mask 710 constitutes the junction field effect transistor 300. The junction field effect transistor 300 is formed on the first conductivity type substrate 100. The orthographic projection on is located in the middle of the active area, and the second conductivity type well area 410 is arranged around the junction field effect transistor 300, as shown in (a) of Figure 4;
S5：在阱区掩膜710的侧壁生长多晶硅侧壁720，多晶硅侧壁720覆盖第二导电类型阱区410的部分表面，如图4中的(b)；S5: Grow polysilicon sidewalls 720 on the sidewalls of the well region mask 710, and the polysilicon sidewalls 720 cover part of the surface of the second conductivity type well region 410, as shown in (b) of Figure 4;
S6：以阱区掩膜710和多晶硅侧壁720为掩膜版，对未被掩膜版覆盖的第二导电类型阱区410进行第二离子注入形成第一导电类型源区结构层421，如图4中的(b)；S6: Using the well region mask 710 and the polysilicon sidewall 720 as a mask, perform a second ion implantation on the second conductivity type well region 410 not covered by the mask to form the first conductivity type source region structure layer 421, such as (b) in Figure 4;
S7：将第一导电类型源区结构层421划分为第一部分和第二部分，第二部分位于第一部分远离结型场效应晶体管300的一侧，设置掩膜层730覆盖第一部分，刻蚀去除至少第二部分的厚度(即可使得深度大于等于第二部分的厚度，图中以深度等于第二部分的厚度为例)，第一部分构成第一导电类型源区420，其中，第一导电类型源区420与结型场效应晶体管300之间区域为沟道S，如图4中的(c)；S7: Divide the first conductivity type source region structure layer 421 into a first part and a second part. The second part is located on the side of the first part away from the junction field effect transistor 300. A mask layer 730 is set to cover the first part and is removed by etching. At least the thickness of the second part (that is, the depth is greater than or equal to the thickness of the second part, in the figure, the depth is equal to the thickness of the second part as an example), the first part constitutes the first conductive type source region 420, wherein the first conductive type The area between the source region 420 and the junction field effect transistor 300 is the channel S, as shown in (c) in Figure 4;
S8：向第二部分正对应的第二导电类型阱区410进行第三离子注入形成第二导电类型体区430，第二导电类型体区430远离第一导电类型衬底100的表面与第一导电类型衬底100之间的垂直间距H1小于等于第一导电类型源区420靠近第一导电类型衬底100的表面与第一导电类型衬底100之间的垂直间距H2(图4中以H1＝H2为例)。S8: Perform third ion implantation into the second conductive type well region 410 corresponding to the second part to form a second conductive type body region 430. The second conductive type body region 430 is away from the surface of the first conductive type substrate 100 and the first conductive type body region 430. The vertical spacing H1 between the conductive type substrates 100 is less than or equal to the vertical spacing H2 between the surface of the first conductive type source region 420 close to the first conductive type substrate 100 and the first conductive type substrate 100 (referred to as H1 in FIG. 4 =H2 as an example).
根据本发明的实施例，在离子注入制备第二导电类型体区430时，需要预先将第二导电类型体区430正上方的材料刻蚀掉，即通过刻蚀去除第二导电类型体区430正上方的第一导电类型源区半导体材料，再进行离子注入，如此便可以避免第二导电类型体区430和第一导电类型源区420的重叠，如此可有效缩小该平面型MOSFET器件的元胞尺寸，进而有效提升平面型MOSFET器件的效率。总而言之，本发明的上述方法制备的平面型MOSFET器件结构简洁，实现方法简单，可提升平面型MOSFET器件的元胞密度，增强单位面积导通电流的能力，提高终端的保护效率，获得高效率的平面型MOSFET器件。According to the embodiment of the present invention, when preparing the second conductive type body region 430 by ion implantation, the material directly above the second conductive type body region 430 needs to be etched away in advance, that is, the second conductive type body region 430 is removed by etching. The semiconductor material of the first conductive type source region directly above is then ion implanted, so that the overlap of the second conductive type body region 430 and the first conductive type source region 420 can be avoided, which can effectively reduce the components of the planar MOSFET device. cell size, thereby effectively improving the efficiency of planar MOSFET devices. All in all, the planar MOSFET device prepared by the above method of the present invention has a simple structure and a simple implementation method. It can increase the cell density of the planar MOSFET device, enhance the ability to conduct current per unit area, improve the protection efficiency of the terminal, and obtain high-efficiency Planar MOSFET devices.
根据本发明的实施例，制备前面所述的平面型MOSFET器件的方法还包括：在终端区，向第一外延层210的上部通过第四离子注入形成多个间隔设置的第一浮空场限环510；在终端区，向第二外延层220的上部通过第五离子注入形成多个间隔设置的第二浮空场限环520，第二浮空场限环520在第一导电类型衬底100上的正投影与第一浮空场限环510在第一导电类型衬底100上的正投影重叠，结构示意图可参照图2。由此，第二浮空场限环520与第一浮空场限环510自对准，进而可以得到深度较深的浮空场限环，可以有效提高终端区的保护效率，并且降低半导体表面的电场强度，提高终端结构的可靠性，本发明通过“离子注入-二次外延-离子注入”的方法，实现较深的(1～2μm)浮空场限环结构，获得高效的终端保护结构。According to an embodiment of the present invention, the method for preparing the aforementioned planar MOSFET device further includes: in the terminal region, forming a plurality of spaced-apart first floating field limits through fourth ion implantation into the upper part of the first epitaxial layer 210 Ring 510; in the terminal area, a plurality of second floating field limiting rings 520 arranged at intervals are formed through fifth ion implantation into the upper part of the second epitaxial layer 220. The second floating field limiting rings 520 are formed on the first conductive type substrate. The orthographic projection on 100 overlaps with the orthographic projection of the first floating field limiting ring 510 on the first conductive type substrate 100 . For a schematic structural diagram, refer to FIG. 2 . As a result, the second floating field limiting ring 520 and the first floating field limiting ring 510 are self-aligned, and thus a floating field limiting ring with a deeper depth can be obtained, which can effectively improve the protection efficiency of the terminal area and reduce the semiconductor surface area. The electric field strength improves the reliability of the terminal structure. The present invention uses the method of "ion implantation-secondary epitaxy-ion implantation" to achieve a deeper (1-2 μm) floating field-limited ring structure and obtain an efficient terminal protection structure. .
根据本发明的实施例，第五离子注入的深度大于等于第二外延层的厚度。即第二浮空场限环结深等于第二外延层的厚度，或者第二浮空场限环结深由第二外延层延伸至第一外延层，即第一浮空场限环与和第二浮空场限环有部分的交叠。由此，上述两种情况，两层的浮空场限环的每根环都一一对应相连，组合成一根较深的场限环(即第二浮空场限环远离所述第一导电类型衬底的表面与所述第一浮空场限环靠近所述第一导电类型衬底的表面之间的垂直间距为两层浮空场限环的深度)。According to an embodiment of the present invention, the depth of the fifth ion implantation is greater than or equal to the thickness of the second epitaxial layer. That is, the second floating field-limited ring junction depth is equal to the thickness of the second epitaxial layer, or the second floating field-limited ring junction depth extends from the second epitaxial layer to the first epitaxial layer, that is, the first floating field-limited ring and the sum The second floating field-limited ring partially overlaps. Therefore, in the above two cases, each ring of the two layers of floating field-limited rings is connected one-to-one, forming a deeper field-limited ring (that is, the second floating field-limited ring is far away from the first conductive field-limited ring). The vertical distance between the surface of the first conductive type substrate and the surface of the first floating field limiting ring close to the first conductive type substrate is the depth of two layers of floating field limiting rings).
其中，形成第一浮空场限环510的步骤是在形成第二外延层220之前进行，形成第二浮空场限环520的步骤可以在形成第二导电类型阱区410之前进行。The step of forming the first floating field limiting ring 510 is performed before forming the second epitaxial layer 220 , and the step of forming the second floating field limiting ring 520 may be performed before forming the second conductive type well region 410 .
根据本发明的实施例，制备前面所述的平面型MOSFET器件的方法还包括：在第二外延层220远离第一导电类型衬底100的表面上形成栅介质层610，且栅介质层610覆盖结型场效应晶体管300、沟道S和部分第一导电类型源区420的表面；在栅介质层610远离第一导电类型衬底100的表面上形成多晶硅栅电极620；在多晶硅栅电极620远离第一导电类型衬底100的表面以及第二外延层220远离第一导电类型衬底100的表面上层间介质层630，并在层间介质层630中形成具有贯穿层间介质层630的接触孔，接触孔暴露出第二导电类型体区430的表面以及部分第一导电类型源区420；在接触孔内形成欧姆接触金属层640，欧姆接触金属层640与接触孔暴露出的第二导电类型体区430的表面和部分第一导电类型源区420的表面形成欧姆接触；在接触孔中形成源极金属650，使得源极金属650通过接触孔与欧姆接触金属层640电性连接；在第一导电类型衬底100远离第一外延层210的表面上形成漏极金属660，结构示意图可参照图3。由此，可以获得高效率的平面型MOSFET器件。According to an embodiment of the present invention, the method of preparing the aforementioned planar MOSFET device further includes: forming a gate dielectric layer 610 on a surface of the second epitaxial layer 220 away from the first conductive type substrate 100, and covering the gate dielectric layer 610. The surface of the junction field effect transistor 300, the channel S and part of the first conductivity type source region 420; a polysilicon gate electrode 620 is formed on the surface of the gate dielectric layer 610 away from the first conductivity type substrate 100; The surface of the first conductive type substrate 100 and the second epitaxial layer 220 are away from the interlayer dielectric layer 630 on the surface of the first conductive type substrate 100 , and a contact penetrating the interlayer dielectric layer 630 is formed in the interlayer dielectric layer 630 hole, the contact hole exposes the surface of the second conductivity type body region 430 and part of the first conductivity type source region 420; an ohmic contact metal layer 640 is formed in the contact hole, and the ohmic contact metal layer 640 and the second conductivity type exposed by the contact hole The surface of the type body region 430 forms an ohmic contact with the surface of part of the first conductivity type source region 420; a source metal 650 is formed in the contact hole, so that the source metal 650 is electrically connected to the ohmic contact metal layer 640 through the contact hole; in A drain metal 660 is formed on the surface of the first conductive type substrate 100 away from the first epitaxial layer 210. For a schematic structural diagram, refer to FIG. 3 . As a result, a high-efficiency planar MOSFET device can be obtained.
其中，栅介质层610可以由热氧化、LPCVD(低压力化学气相沉积法)、PECVD(等离子体增强化学的气相沉积法)、ALD(原子层沉积)中的至少之一种方法形成，多晶硅栅电极620可以通过原位掺杂形成，或非掺多晶硅通过掺杂形成。上述工艺成熟，便于工业化生产，效率也较好。The gate dielectric layer 610 may be formed by at least one of thermal oxidation, LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), and ALD (Atomic Layer Deposition). The polysilicon gate Electrode 620 may be formed by in-situ doping, or undoped polysilicon may be formed by doping. The above-mentioned technology is mature, easy for industrial production, and has high efficiency.
文中术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。The terms "first" and "second" in this article are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of this application, "plurality" means two or more than two, unless otherwise explicitly and specifically limited.
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。In the description of this specification, reference to the terms "one embodiment," "some embodiments," "an example," "specific examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the invention. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。Although the embodiments of the present invention have been shown and described above, it can be understood that the above-mentioned embodiments are illustrative and should not be construed as limitations of the present invention. Those of ordinary skill in the art can make modifications to the above-mentioned embodiments within the scope of the present invention. The embodiments are subject to changes, modifications, substitutions and variations.
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