CN117034296A - System starting method, system, equipment and medium - Google Patents
System starting method, system, equipment and medium Download PDFInfo
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- CN117034296A CN117034296A CN202311148976.9A CN202311148976A CN117034296A CN 117034296 A CN117034296 A CN 117034296A CN 202311148976 A CN202311148976 A CN 202311148976A CN 117034296 A CN117034296 A CN 117034296A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F21/575—Secure boot
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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Abstract
The invention discloses a system starting method, a system, equipment and a medium. The method comprises the following steps: responding to the received starting signal, and acquiring a chip selection signal through a monitoring chip to determine a first flash memory which is read when the starting signal is received; sequentially loading and checking firmware programs of all partitions in the first flash memory, and timing by using a watchdog; if the firmware program of the partition in the first flash memory fails to check, sending a chip switching signal request to point to the second flash memory by the chip switching signal in the time of watchdog timing, loading and checking the firmware program of the partition corresponding to the partition which fails to check in the second flash memory, and setting an abnormal starting identifier; if the firmware program verification of the corresponding partition passes, sequentially loading and verifying the firmware programs of the partitions after the corresponding partition; if the firmware programs of the partitions after the corresponding partitions are loaded and checked successfully and the watchdog is not overtime, starting the control system through all the firmware programs loaded and checked successfully in the first flash memory and the second flash memory.
Description
Technical Field
The present invention relates to the field of system security management technologies, and in particular, to a system startup method, system, device, and medium.
Background
The BMC (Baseboard Management Controller ) is an embedded microcontroller that can be used to manage and monitor the hardware and system management functions of a server or computer system. As BMC systems are increasingly used, security requirements are also increasing, especially for firmware programs in BMC systems. Firmware programs of the BMC system are generally burnt in a flash memory (flash) chip, if the flash memory chip is damaged or a part of the firmware programs are maliciously tampered, the BMC system cannot be started normally, the overall safety of a server or a computer system cannot be ensured, and the reliability of the BMC system is reduced.
Therefore, how to provide a system starting method with high security and high reliability to avoid the problem of abnormal starting of the BMC system is a technical problem that needs to be solved urgently.
Disclosure of Invention
In view of this, the invention provides a system starting method, system, device and medium, which solves the problem of starting failure of the BMC system caused by abnormal firmware programs in different partitions in the dual flash memory, and enhances the stability and robustness of the BMC system.
Based on the above objects, an aspect of the embodiments of the present invention provides a system startup method, which specifically includes the following steps:
Responding to a received starting signal, and acquiring a chip selection signal through a monitoring chip to determine a first flash memory which is read when the starting signal is received;
sequentially loading and checking firmware programs of all partitions in the first flash memory, and timing by using a watchdog;
if the firmware program of the partition in the first flash memory fails to check, sending a chip switching signal request to point to a second flash memory by a chip switching signal in the time of the watchdog timing, loading and checking the firmware program of the partition corresponding to the partition which fails to check in the second flash memory, and setting an abnormal starting identifier;
if the firmware program verification of the corresponding partition in the second flash memory passes, sequentially loading and verifying the firmware programs of all partitions after the corresponding partition in the second flash memory;
if the firmware programs of all the partitions after the corresponding partitions in the second flash memory are loaded and verified successfully, and the watchdog is not overtime, starting a control system through all the firmware programs loaded and verified successfully in the first flash memory and the second flash memory.
In some embodiments, the step of sending a request for switching the chip select signal to direct the chip select signal to the second flash memory in the time of watchdog timing if the firmware program verification of the partition exists in the first flash memory fails includes:
If the firmware program verification of the partition in the first flash memory fails, confirming that the firmware program of the partition in the first flash memory is an abnormal firmware program, recording a starting path of the firmware program of the partition in the first flash memory into an abnormal starting path file, and sending a chip switching signal request;
and responding to the monitoring chip receiving the chip selection signal switching request, and directing the chip selection signal to the second flash memory by inverting the chip selection signal.
In some embodiments, the method further comprises:
if the firmware program of the partition in the second flash memory fails to be checked again after the corresponding partition exists, a switch chip selection signal request is sent again in the time of the watchdog timing so that the switch chip selection signal points to the first flash memory, and the firmware program of the partition corresponding to the partition failing to be checked again in the first flash memory is loaded and checked;
if the firmware program of the partition corresponding to the partition which fails to be checked again in the first flash memory passes the verification, loading and checking the firmware programs of the subsequent partitions in the first flash memory again in sequence;
if the firmware programs of the subsequent partitions in the first flash memory are loaded and checked successfully, and the watchdog is not overtime, starting the control system through all the firmware programs which are loaded and checked successfully in the first flash memory and the second flash memory.
In some embodiments, if the firmware program of the partition after the corresponding partition in the second flash memory fails to check again, the step of sending a request for switching the chip select signal again to switch the chip select signal to point to the first flash memory within the time of the watchdog timing includes:
if the firmware program of the partition fails to be checked again after the corresponding partition exists in the second flash memory, confirming that the firmware program of the partition which fails to be checked again in the second flash memory is an abnormal firmware program, recording the starting path of the firmware program of the partition which fails to be checked again in the second flash memory into an abnormal starting path file, and sending a chip selection signal switching request;
and responding to the monitoring chip receiving the request for switching the chip selection signal, and reversing the chip selection signal again to point the chip selection signal to the first flash memory.
In some embodiments, the method further comprises:
in response to completion of control system start-up, checking the status of the abnormal start-up flag;
if the abnormal starting identifier is in a set state, reading the abnormal starting path file to determine abnormal firmware path information of each abnormal firmware program;
determining all normal firmware programs in the first flash memory and the second flash memory based on all abnormal firmware path information, and storing data of all normal firmware programs in a memory;
Judging whether abnormal firmware path information corresponding to the first flash memory and/or the second flash memory exists or not;
if abnormal firmware path information corresponding to the first flash memory exists, sending a chip selection signal switching request to switch the chip selection signal to point to the first flash memory, and writing data of all normal firmware programs in a memory into the first flash memory;
if abnormal firmware path information corresponding to the second flash memory exists, sending a chip selection signal switching request to switch the chip selection signal to point to the second flash memory, and writing data of all normal firmware programs in the memory into the second flash memory;
determining to complete repair of the abnormal firmware program in response to complete updating of all flash memories with abnormal firmware path information;
and starting a configuration information synchronization process to synchronize the second flash memory with the first flash memory, and determining that the control system normally completes operation.
In some embodiments, the method further comprises:
and if the abnormal starting identifier is in an unset state, starting a configuration information synchronization process to synchronize the second flash memory with the first flash memory, and determining that the control system normally completes operation.
In some embodiments, the step of setting the abnormal start flag includes:
Responding to the monitoring chip receiving the switch chip selection signal request, judging whether the abnormal starting mark is in a set state or not;
if the abnormal starting identifier is in an unset state, updating the abnormal starting identifier to be in a set state, and reading a flash memory corresponding to the switched chip selection signal;
and if the abnormal starting mark is in a set state, reading the flash memory corresponding to the switched chip select signal.
In some embodiments, the method further comprises:
if the firmware programs of all the partitions in the first flash memory are loaded and verified successfully, determining that all the firmware programs in the first flash memory are normal firmware programs, starting a control system through all the firmware programs in the first flash memory, and starting a feeding signal to determine that the control system is started and completed.
In some embodiments, the method further comprises:
if the first flash memory and the second flash memory have the partitions with the firmware programs failing to check, resetting the control system and stopping starting the control system after waiting for the timeout of the watchdog.
The step of loading and verifying the firmware programs of all the partitions in the first flash memory in sequence comprises the following steps:
and sequentially loading and checking the firmware programs of all the partitions in the first flash memory from the firmware programs of the initial partition.
In some embodiments, the monitoring chip comprises a complex programmable logic device and the control system comprises a baseboard management controller.
In another aspect of the embodiment of the present invention, there is also provided a system start-up system, including:
the acquisition unit is used for responding to the received starting signal, and acquiring a chip selection signal through the monitoring chip to determine a first flash memory carried out when the starting signal is received;
the first loading verification unit is used for sequentially loading and verifying the firmware programs of all the partitions in the first flash memory, and timing by using a watchdog;
the switching unit is used for sending a switching chip selection signal request to switch the chip selection signal to point to the second flash memory in the time of the watchdog timing when the verification of the firmware program of the partition in the first flash memory fails, loading and verifying the firmware program of the partition corresponding to the partition which fails to verify in the second flash memory, and setting an abnormal starting identifier;
the second loading verification unit is used for sequentially loading and verifying the firmware programs of all the partitions after the corresponding partitions in the second flash memory if the firmware programs of the corresponding partitions in the second flash memory pass verification;
And the starting unit is used for starting the control system through all the firmware programs loaded and checked successfully in the first flash memory and the second flash memory if the firmware programs of all the partitions after the corresponding partitions in the second flash memory are loaded and checked successfully and the watchdog is not overtime.
In yet another aspect of the embodiment of the present invention, there is also provided a computer apparatus, including: at least one processor; and a memory storing a computer program executable on the processor, which when executed by the processor, performs the steps of the method as above.
In yet another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the method steps as described above.
The invention has at least the following beneficial technical effects:
the invention provides a system starting method, which adopts a safe starting strategy to check each part of firmware programs in the current flash memory, once abnormal firmware programs exist in the current flash memory, a switch chip selection signal is sent to inform a monitoring chip to switch to another flash memory to load and check the firmware programs in the same partition as the abnormal firmware programs in the other flash memory in the time of watchdog timing, namely, once the check of a certain partition in a certain flash memory fails, normal firmware programs in the same partition in the other flash memory can be automatically loaded in the time of watchdog timing to complete the starting of the system, only the firmware programs in the same partition as the abnormal firmware programs in the other flash memory need to be reloaded, the reset control system is not needed to reload all the firmware programs in the other flash memory after the watchdog timing is carried out again, and when the abnormal firmware programs in different partitions exist in the double flash memory at the same time, the switch chip selection signals can be mutually loaded in the same partition as the other flash memory in the time of watchdog timing to complete the starting of the system, thereby solving the problem that the starting failure of the control system is caused by data abnormality of one or more different partition firmware programs in the double flash memories, and enhancing the stability and robustness of the control system.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a dual-image backup mechanism according to an embodiment of the related art;
FIG. 2 is a block diagram of an embodiment of a system startup method provided by the present invention;
FIG. 3 is a flowchart illustrating an embodiment of a control system in a system start method according to the present invention;
FIG. 4 is a flowchart of an embodiment of a method for monitoring a chip side in a system start-up method according to the present invention;
FIG. 5 is a flowchart illustrating an embodiment of a control system side during a recovery process of a system start method according to the present invention;
FIG. 6 is a flowchart of an embodiment of monitoring a chip side during a recovery process of a system boot method according to the present invention;
FIG. 7 is a schematic diagram of a system start-up system according to an embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating a computer device according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of an embodiment of a computer readable storage medium according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
The firmware program of the BMC is generally burned in the flash memory, and when the BMC system is powered on, the BMC reads the flash memory and loads spl (Secondary Program Loader, second-stage loader), u-boot (Universal Bootloader, general loader), operating system kernel (kernel) and root file system (rootfs) in sequence to complete the startup of the BMC system. Once the flash memory is damaged or some part of data is tampered with maliciously, the starting of the BMC system is abnormal.
In the related art, the safety and reliability of the BMC system are improved by adopting two technical means. The first aspect is a secure startup technology based on a trust chain, namely, in the startup process of the BMC system, each level of image is subjected to validity verification by the previous level of image, and as long as the first level of image has validity, the validity of the second level of image is ensured by the first level of image, so that the trust chain of the whole startup process is formed, and the credibility of the BMC system is ensured. The second aspect is a dual-image backup mechanism, namely, two independent flash memories are adopted in a BMC system to store two independent image files, the BMC system is usually started by a main flash memory by default when started, and the main flash memory is automatically switched to a slave flash memory for starting when abnormal conditions occur in the starting of the main flash memory, so that the BMC system is ensured to be started normally when a certain main flash memory is abnormal.
FIG. 1 is a flow chart illustrating an embodiment of a dual-mirror backup mechanism in the related art. After the BMC system is powered on, the CPLD (Complex Programmable Logic Device ) enables the flash memory corresponding to the CS (Circuit Switching ) state, usually the main flash memory, according to the CS (Circuit Switching ) state recorded in the UFM (User Flash Memory ), the BMC system loads the data of the spl, u-boot, kernel and other firmware programs in the main flash memory in sequence, the starting of the BMC system is completed, and after the BMC system is started, the mirror image files of the two flash memories are synchronized. When the data of a certain firmware program is abnormal during the starting process of the BMC system, the BMC system fails to start, after the WDT (Watch Dog Timer) in the CPLD is required to be overtime, the CS is switched and the BMC is reset to enable the BMC system to be started again by the slave flash memory, the data of the firmware programs such as spl, u-boot and kernel in the slave flash memory are loaded again, and finally the starting of the BMC system is completed through the firmware programs of the slave flash memory. When different firmware programs in the master flash memory and the slave flash memory have data abnormality, for example, when spl of the master flash memory and u-boot of the slave flash memory have data abnormality, the starting abnormality of the BMC system is caused. After the firmware program of a certain partition in the main flash memory is abnormal, waiting for WDT timeout in the CPLD and resetting the BMC system, and then loading and checking the firmware programs of all the partitions in sequence from the first partition of the flash memory, so that the time consumption is long and the process is complicated.
Therefore, the above-mentioned related technical means cannot solve the problem of abnormal starting of the BMC system under the condition that firmware programs of different partitions respectively exist in the main flash memory and the slave flash memory, and cannot realize rapid reloading of the firmware programs in the partitions corresponding to the abnormal firmware programs, and still cannot meet the requirements of high reliability and high security of the BMC system.
In order to solve the above problem, a first aspect of the embodiments of the present invention provides a system startup method, which can solve the problem that a firmware program of one or more partitions in a main flash memory and/or a slave flash memory has an abnormality to cause startup failure of a BMC system, improve startup efficiency of the BMC system, and ensure safety and reliability of the BMC system.
Fig. 2 is a block diagram of an embodiment of a system startup method provided by the present invention. As shown in fig. 1, it includes the steps of:
s100, responding to a starting signal, and acquiring a chip selection signal through a monitoring chip to determine a first flash memory which is read when the starting signal is received.
The chip select signal is used for indicating whether the flash memory which is started by the control system currently is a master flash memory or a slave flash memory. For example, after the system is powered on, the monitoring chip first determines the flash memory to be started currently by acquiring the chip select signal recorded in the memory chip. The monitoring chip comprises a CPLD, and the invention is not limited to the specific type of the monitoring chip. The memory chip includes a UFM, and the present invention is not limited to a specific type of memory chip. The chip select signal is in a CS state, for example, when the chip select signal is CS1, the master flash memory is enabled, and when the chip select signal is CS2, the slave flash memory is enabled.
S200, sequentially loading and checking firmware programs of all partitions in the first flash memory, and timing by using a watchdog.
For example, the first flash memory is a flash memory corresponding to a CS state when powered up, and may be a master flash memory or a slave flash memory. The control system comprises embedded microcontrollers such as a BMC system and the like. Each firmware program is checked through a safe starting strategy, wherein the safe starting strategy is a safe mechanism used in the system starting process, so that only authorized software can be ensured to run in the control system, and malicious software or an unauthorized operating system or driver can be effectively prevented from being loaded into the control system. The firmware program is a complete program running on an ARM (Advanced RISC Machine, reduced instruction set machine) processor and used to support the normal operation of the control system. Each flash memory includes a plurality of parts of firmware programs, for example, the first flash memory may include spl, u-boot, kernel, rootfs and other firmware programs.
The WDT watchdog is a special timer module that can help the server or computer recover, and when the WDT watchdog times out, it triggers the control system to reset.
And S300, if the firmware program of the partition in the first flash memory fails to check, sending a chip switching signal request to point to the second flash memory by the chip switching signal in the time of the watchdog timing, loading and checking the firmware program of the partition corresponding to the partition which fails to check in the second flash memory, and setting an abnormal starting mark.
For example, the second flash memory is a flash memory that is not read when the control system is powered on, and may be a master flash memory or a slave flash memory. The abnormal starting mark is information for judging whether an abnormal firmware program exists in the starting process of the control system, so that the abnormal firmware program can be recovered after the system is started. When the verification of the firmware program of a certain partition in the first flash memory fails, the level state of the chip selection signal is changed to the second flash memory in the time of watchdog timing, and the monitoring chip is automatically switched and loads the firmware program of the same partition in the second flash memory. The monitoring chip can comprise a path switching request monitoring interface and a WDT dog feeding signal monitoring interface. Once the verification of a certain partition in the first flash memory fails, the firmware programs corresponding to the same partition in the second flash memory can be automatically loaded and verified in the time of the watchdog timing, and only the firmware programs of the partition which is positioned in the same partition as the abnormal firmware programs in the first flash memory in the second flash memory are needed to be reloaded, and the reset control system does not need to wait for the starting partition to sequentially load and verify the firmware programs of all the partitions in the second flash memory after the watchdog is overtime.
And S400, if the firmware program verification of the corresponding partition in the second flash memory is passed, loading and verifying the firmware programs of the partitions after the corresponding partition in the second flash memory in sequence.
S500, if the firmware programs of all the partitions after the corresponding partitions in the second flash memory are loaded and checked successfully, and the watchdog is not overtime, starting the control system through all the firmware programs loaded and checked successfully in the first flash memory and the second flash memory.
Specifically, the control system starts to load and check the firmware programs of each partition in the second flash memory sequentially from the firmware programs of the partition corresponding to the abnormal firmware program in the first flash memory, and starts the control system based on the firmware programs normally loaded in the first flash memory and the firmware programs normally loaded in the second flash memory after the firmware programs of other partitions in the second flash memory pass the verification and are normally loaded.
Through the scheme, the safety starting strategy is adopted to check each part of firmware programs in the current flash memory, once abnormal firmware programs exist in the current flash memory, a switch chip selection signal request is sent within the time of watchdog timing to inform a monitoring chip to switch to another flash memory to load and check the firmware programs in the same partition as the abnormal firmware programs, a reset control system is not required to reload all the firmware programs in the other flash memory after the watchdog timing is performed again, the starting safety of the control system is ensured, the loading process of the firmware programs is simplified, the starting efficiency of the control system is improved, and the stability and the robustness of the control system are enhanced.
In some embodiments, further comprising: if the firmware program of the partition in the second flash memory corresponding to the partition fails to be checked again, a chip switching signal request is sent again to switch the chip switching signal to point to the first flash memory in the time of watchdog timing, and the firmware program of the partition corresponding to the partition failing to be checked again in the first flash memory is loaded and checked; if the firmware program of the partition corresponding to the partition which fails to be checked again in the first flash memory passes the verification, loading and checking the firmware programs of the subsequent partitions in the first flash memory again in sequence; if the firmware programs of the subsequent partitions in the first flash memory are loaded and verified successfully, and the watchdog is not overtime, starting the control system through all the firmware programs which are loaded and verified successfully in the first flash memory and the second flash memory.
In one example, when there is a data abnormality in the spl firmware program of the first flash memory and the switch chip select signal is directed to the second flash memory to finish reloading the spl firmware program in the second flash memory, sequentially loading and checking the firmware programs of each partition after the corresponding partition of the spl firmware program in the second flash memory, if there is a data abnormality in the u-boot firmware program after the corresponding partition of the spl firmware program in the second flash memory, switching the chip select signal to the first flash memory again within the time of the watchdog timing, and reloading the u-boot firmware program in the first flash memory.
Through the scheme, when abnormal firmware programs under different partitions exist in the dual flash memories at the same time, the chip selection signals can be switched in the time of the watchdog timing to mutually load the normal firmware programs of the same partition in the opposite flash memory so as to finish the starting of the system, the control system does not need to be reset to reload all the firmware programs in the other flash memory after the watchdog timing is performed again, the starting efficiency of the control system is improved, the starting process of the control system is simplified, the problem that the starting failure of the control system is caused by the occurrence of data abnormality of the firmware programs of one or more different partitions in the dual flash memories is solved, and the stability and the robustness of the control system are enhanced.
In some embodiments, after the control system is started, the method further comprises: in response to completing the control system start, checking for an abnormal start identification status; if the abnormal starting identifier is in a set state, reading an abnormal starting path file to determine abnormal firmware path information of each abnormal firmware program; determining all normal firmware programs in the first flash memory and the second flash memory based on all abnormal firmware path information, and storing data of all normal firmware programs in a memory; judging whether abnormal firmware path information corresponding to the first flash memory and/or the second flash memory exists or not; if abnormal firmware path information corresponding to the first flash memory exists, sending a chip switching signal request to point to the first flash memory by the chip switching signal, and writing data of all normal firmware programs in the memory into the first flash memory; if abnormal firmware path information corresponding to the second flash memory exists, sending a chip switching signal request to point to the second flash memory by the chip switching signal, and writing data of all normal firmware programs in the memory into the second flash memory; determining to complete repair of the abnormal firmware program in response to complete updating of all flash memories with abnormal firmware path information; and starting a configuration information synchronization process to synchronize the second flash memory with the first flash memory, and determining that the control system normally completes operation.
In some embodiments, further comprising: if the abnormal starting identifier is in an unset state, determining that no abnormal firmware program exists in the first flash memory; and starting a configuration information synchronization process to synchronize the second flash memory with the first flash memory, and determining that the control system normally completes operation.
Specifically, after the control system is started, the control system communicates with the monitoring chip through a network two-wire serial bus (I2C) interface to obtain an abnormal starting identifier, when the abnormal starting identifier is enabled, the control system sends an abnormal starting path request to the monitoring chip to obtain abnormal starting paths of all abnormal firmware programs, all normal firmware programs are screened out according to the abnormal starting paths of all the abnormal firmware programs, data of the normal firmware programs are copied into a memory, the data in the memory can be written into the first flash memory and/or the second flash memory, and recovery of all the flash memories with abnormal firmware path information is completed.
Through the scheme, through the abnormal starting identification and the abnormal starting path file, after the control system is started, all normally started firmware programs can be screened out and stored according to the enabled abnormal starting identification and the abnormal starting path file, so that the abnormal firmware programs in the flash memory can be recovered, the efficiency of flash memory repair is improved, the problem that the abnormal firmware programs cause failure when the control system is started next time can be avoided, and the stability and the robustness of the control system are enhanced.
According to several embodiments of the present invention, the step of sequentially loading and verifying firmware programs of each partition in the first flash memory includes: and sequentially loading and checking the firmware programs of all the partitions in the first flash memory from the firmware programs of the initial partition.
Specifically, when the firmware programs to be started in the control system include spl, u-boot, kernel and rootfs firmware programs, the firmware program of the start partition is spl, and the firmware program of the end partition is rootfs.
According to several embodiments of the present invention, if the firmware program verification of the partition exists in the first flash memory fails, the step of sending a request for switching the chip select signal to switch the chip select signal to point to the second flash memory within the time of watchdog timing includes: if the firmware program verification of the partition in the first flash memory fails, confirming that the firmware program of the partition in the first flash memory is an abnormal firmware program, recording the starting path of the firmware program of the partition in the first flash memory into an abnormal starting path file, and sending a chip selection signal switching request; and responding to the monitoring chip receiving the request of switching the chip selection signal, and directing the chip selection signal to the second flash memory by inverting the chip selection signal.
According to several embodiments of the present invention, if the firmware program of the partition after the corresponding partition in the second flash memory fails to check again, a step of sending a chip select signal switching request again to switch the chip select signal to point to the first flash memory within the time of the watchdog timing includes: if the firmware program of the partition fails to be checked again after the corresponding partition exists in the second flash memory, confirming that the firmware program of the partition which fails to be checked again in the second flash memory is an abnormal firmware program, recording the starting path of the firmware program of the partition which fails to be checked again in the second flash memory into an abnormal starting path file, and sending a request for switching the chip selection signal; and responding to the monitoring chip receiving the chip selection signal switching request, and reversing the chip selection signal again to point the chip selection signal to the first flash memory.
In an embodiment, when the firmware programs to be started in the control system include four partition firmware programs of spl, u-boot, kernel and rootfs, the firmware program of the partition existing in the first flash memory may be any one partition firmware program of spl, u-boot and kernel except the root firmware program of the ending partition, and the firmware program of the partition existing after the corresponding partition in the second flash memory may be any one partition firmware program of u-boot, kernel and rootfs except the spl firmware program of the starting partition.
Fig. 3 is a flowchart of an embodiment of a control system side in the system start method provided by the present invention. Fig. 4 is a flowchart of an embodiment of monitoring a chip side in the system start method provided by the present invention. The control system is BMC, the monitoring chip is CPLD, and the firmware programs comprise four partition firmware programs of spl, u-boot, kernel and rootfs. The CPLD comprises a switch chip select signal request monitoring interface and a WDT dog feeding signal monitoring interface.
In an example, the first flash memory is taken as an example of a main flash memory, and a starting process of the firmware program when the path state is not switched is described:
the BMC system reads the main flash memory, loads the spl image in the main flash memory and invokes the safe starting strategy to verify the spl image, when the spl image in the main flash memory passes the verification, the BMC system continues to load the u-boot image in the main flash memory and invokes the safe starting strategy to verify the u-boot image, and when the spl image in the main flash memory fails the verification, the BMC system sends a chip selection signal switching request to the CPLD through the I2C interface to switch the chip selection signal to point to the slave flash memory and enable the slave flash memory. When the CPLD receives a request for switching the chip select signal, firstly, reading the abnormal starting identification stored in the UFM, judging and updating the setting state of the abnormal starting identification, switching the main flash memory into the auxiliary flash memory after the chip select signal is inverted, and storing the starting path of spl in the main flash memory as an abnormal system starting path. And the BMC reloads the image file of spl in the flash memory, invokes the secure boot policy to verify the image file, and when the verification of spl image in the flash memory passes, continues to load the u-boot image in the flash memory and invokes the secure boot policy to verify the image file.
By the scheme, when the firmware program of a certain partition in the flash memory which is started currently by the control system is abnormal, the firmware program of the same partition in the other flash memory is tried to be started, the control system is not required to be reset to reduce the starting efficiency of the control system due to the fact that a watchdog is not required to wait for overtime, only the firmware program of the abnormal partition corresponding to the current partition in the other flash memory is required to be reloaded, all the firmware programs in the other flash memory are not required to be loaded and checked from the initial partition after the control system is reset, normal starting of the BMC system is ensured, meanwhile, the starting efficiency and the starting flow of the control system are improved, and the robustness of the system is improved.
In one example, a start-up procedure of a firmware program after a path state has been switched is described:
and switching the master flash memory into the slave flash memory, and after the BMC starts spl based on the spl image in the slave flash memory, continuing to load the u-boot image in the slave flash memory and calling a safe starting strategy to verify the u-boot image. When the verification of the u-boot image in the slave flash memory passes, the slave flash memory kernel image is continuously loaded, a safe starting strategy is invoked to verify the slave flash memory kernel image, and when the verification of the u-boot image in the slave flash memory fails, the BMC system sends a chip switching signal switching request to the CPLD again through the I2C interface to switch the chip switching signal to point to the slave flash memory and enable the master flash memory. When the CPLD receives a chip selection signal switching request, firstly, reading an abnormal starting identifier stored in the UFM, judging and updating the setting state of the abnormal starting identifier, switching the slave flash memory into the master flash memory again, and storing a starting path of a u-boot in the slave flash memory as an abnormal starting path. The BMC system reloads the image file of the kernel in the main flash memory, invokes the safe starting strategy to check the image file, and when the verification of the kernel image in the main flash memory passes, continues to load the rootfs image in the main flash memory and invokes the safe starting strategy to check the rootfs image.
Through the scheme, when abnormal data appear in firmware programs of different partitions simultaneously exist in the dual flash memory of the control system, the normal firmware programs of the same partition in the opposite flash memory can be mutually loaded by the switch chip selection signals in the time of the watchdog timing so as to finish the starting of the system, the control system does not need to be reset to reload all the firmware programs in the other flash memory after the watchdog timing is performed again, the starting efficiency of the control system is improved, the starting process of the control system is simplified, the situation that the starting of the control system is abnormal due to the fact that the firmware programs of partial partitions simultaneously exist in the dual flash memory are abnormal is avoided, and the stability and the robustness of the control system are improved.
According to the embodiments of the present invention, if the firmware programs of each partition in the first flash memory are loaded and all verified successfully, it is determined that all the firmware programs in the first flash memory are normal firmware programs, the control system is started by all the firmware programs in the first flash memory, and the dog feeding signal is started to determine that the control system is started.
According to several embodiments of the present invention, the step of setting an abnormal start flag includes: responding to the monitoring chip receiving a request for switching the chip selection signal, and judging whether the abnormal starting mark is in a set state or not; if the abnormal starting identifier is in an unset state, updating the abnormal starting identifier to be in a set state, and reading a flash memory corresponding to the switched chip selection signal; and if the abnormal starting mark is in a set state, reading the flash memory corresponding to the switched chip select signal.
For example, as shown in fig. 4, when the monitoring chip receives the request for switching the chip selection signal, firstly, the abnormal start identifier stored in the memory is read, whether the abnormal start identifier is in a set state is judged, and if the abnormal start identifier is not in the set state, the abnormal start identifier is updated to be in the set state. When the abnormal starting mark is in a set state, the chip select signal is requested to be reversed to switch the chip select signal to point to the other flash memory, and meanwhile, starting path information of the abnormal firmware program is stored as recording abnormal starting path information.
By the scheme, the abnormal starting identification is updated in the control system, so that the control system can judge whether abnormal data exists in the starting process according to the abnormal starting identification after being started, and all normally started firmware programs are screened out and stored by inquiring an abnormal starting path, thereby being beneficial to restoring the abnormal firmware programs in the flash memory, improving the efficiency of flash memory restoration, avoiding the problem that the abnormal firmware programs cause failure when the control system is started next time, solving the problem that the control system is started to fail due to the abnormal part of partition data in the double flash memories, and enhancing the stability and the robustness of the control system.
According to the embodiments of the present invention, if there are partitions in the first flash memory and the second flash memory, where the firmware program is not verified, the control system is reset and the control system is stopped to be started after waiting for the watchdog to timeout.
Specifically, fig. 5 is a flowchart of an embodiment of controlling a system side in a system recovery process according to the present invention. FIG. 6 is a flowchart of an embodiment of monitoring a chip side during a system recovery process according to the present invention. After the control system is started, an abnormal starting path acquisition request monitoring interface is added in the control chip and is used for reading the abnormal starting path stored in the memory after the abnormal starting path acquisition request sent by the control system is received, and sending the abnormal starting path to the control system.
Specifically, after the control system acquires the abnormal starting identifier, the abnormal starting identifier is enabled to send an abnormal starting path acquisition request to the monitoring chip, the synchronization process of the flash memory configuration information in the control system is stopped, and the abnormal starting path of the system is received. And analyzing the abnormal starting path to obtain the information such as the flash memory number, the partition name, the offset address, the partition size and the like corresponding to the abnormal firmware program. Screening out normal partitions according to the abnormal partition information, after storing all firmware programs which are normally started in the normal partitions into a memory, sending a chip switching signal switching request to a monitoring chip to switch the chip switching signal to point to a flash memory with the abnormal firmware programs, writing data of the normal firmware programs in the memory into the flash memory with the abnormal firmware programs so as to update the data of the abnormal partitions in the flash memory, determining that all the flash memories with the abnormal firmware path information are updated, and determining that recovery of the abnormal firmware programs is completed. And finally, starting a synchronization process of the flash memory configuration information in the control system to enable the system to normally operate.
Through the scheme, the abnormal starting path is obtained and analyzed according to the abnormal starting identification, the firmware programs of the normal partitions are screened and stored in the memory, the abnormal firmware programs of the partitions in the flash memory can be recovered quickly, the flash memory repairing efficiency is improved, the problem that the abnormal firmware programs fail when the control system is started next time can be avoided, and the stability of the control system is enhanced.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 7, the present invention further provides a system start-up system, including:
an obtaining unit 110, configured to obtain, in response to receiving the boot signal, a chip select signal through a monitoring chip to determine a first flash memory that is read when the boot signal is received;
the first load checking unit 120 is configured to sequentially load and check firmware programs of each partition in the first flash memory, and perform timing by using a watchdog;
the switching unit 130 is configured to send a request for switching the chip select signal to point to the second flash memory in the time of watchdog timing when the verification of the firmware program of the partition in the first flash memory fails, where the second flash memory corresponds to the firmware program of the partition in which the verification fails, and set an abnormal start identifier;
The second loading verification unit 140 is configured to sequentially load and verify the firmware programs of the partitions after the corresponding partitions in the second flash memory if the firmware programs of the corresponding partitions in the second flash memory pass verification;
and the starting unit 150 is used for starting the control system through all the firmware programs loaded and checked successfully in the first flash memory and the second flash memory if the firmware programs of the partitions after the corresponding partitions in the second flash memory are loaded and checked successfully and the watchdog is not overtime.
According to another aspect of the present invention, as shown in fig. 8, according to the same inventive concept, an embodiment of the present invention further provides a computer device 30, in which the computer device 30 includes a processor 310 and a memory 320, the memory 320 storing a computer program 321 executable on the processor, and the processor 310 executing the steps of the method as above.
According to another aspect of the present invention, as shown in fig. 9, there is also provided a computer-readable storage medium 40 according to the same inventive concept, the computer-readable storage medium 40 storing a computer program 410 which when executed by a processor performs the above method.
Finally, it should be noted that, as will be appreciated by those skilled in the art, all or part of the procedures in implementing the methods of the embodiments described above may be implemented by a computer program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, and the program may include the procedures of the embodiments of the methods described above when executed. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (14)
1. A system start-up method, comprising:
responding to a received starting signal, and acquiring a chip selection signal through a monitoring chip to determine a first flash memory which is read when the starting signal is received;
Sequentially loading and checking firmware programs of all partitions in the first flash memory, and timing by using a watchdog;
if the firmware program of the partition in the first flash memory fails to check, sending a chip switching signal request to point to a second flash memory by a chip switching signal in the time of the watchdog timing, loading and checking the firmware program of the partition corresponding to the partition which fails to check in the second flash memory, and setting an abnormal starting identifier;
if the firmware program verification of the corresponding partition in the second flash memory passes, sequentially loading and verifying the firmware programs of all partitions after the corresponding partition in the second flash memory;
if the firmware programs of all the partitions after the corresponding partitions in the second flash memory are loaded and verified successfully, and the watchdog is not overtime, starting a control system through all the firmware programs loaded and verified successfully in the first flash memory and the second flash memory.
2. The method of claim 1, wherein the step of sending a switch chip select signal request to switch the chip select signal to point to the second flash memory within a watchdog timed time if the firmware program verification of the partition exists in the first flash memory fails, comprises:
If the firmware program verification of the partition in the first flash memory fails, confirming that the firmware program of the partition in the first flash memory is an abnormal firmware program, recording a starting path of the firmware program of the partition in the first flash memory into an abnormal starting path file, and sending a chip switching signal request;
and responding to the monitoring chip receiving the chip selection signal switching request, and directing the chip selection signal to the second flash memory by inverting the chip selection signal.
3. The method as recited in claim 1, further comprising:
if the firmware program of the partition in the second flash memory fails to be checked again after the corresponding partition exists, a switch chip selection signal request is sent again in the time of the watchdog timing so that the switch chip selection signal points to the first flash memory, and the firmware program of the partition corresponding to the partition failing to be checked again in the first flash memory is loaded and checked;
if the firmware program of the partition corresponding to the partition which fails to be checked again in the first flash memory passes the verification, loading and checking the firmware programs of the subsequent partitions in the first flash memory again in sequence;
if the firmware programs of the subsequent partitions in the first flash memory are loaded and checked successfully, and the watchdog is not overtime, starting the control system through all the firmware programs which are loaded and checked successfully in the first flash memory and the second flash memory.
4. The method of claim 3, wherein the step of re-sending a switch chip select signal request to switch the chip select signal to the first flash memory within the watchdog timed time if the firmware program of the partition after the corresponding partition in the second flash memory fails to check again comprises:
if the firmware program of the partition fails to be checked again after the corresponding partition exists in the second flash memory, confirming that the firmware program of the partition which fails to be checked again in the second flash memory is an abnormal firmware program, recording the starting path of the firmware program of the partition which fails to be checked again in the second flash memory into an abnormal starting path file, and sending a chip selection signal switching request;
and responding to the monitoring chip receiving the request for switching the chip selection signal, and reversing the chip selection signal again to point the chip selection signal to the first flash memory.
5. The method according to any one of claims 2 or 4, further comprising:
in response to completing the start-up of the control system, checking the status of the abnormal start-up indicator;
if the abnormal starting identifier is in a set state, reading an abnormal starting path file to determine abnormal firmware path information of each abnormal firmware program;
Determining all normal firmware programs in the first flash memory and the second flash memory based on all abnormal firmware path information, and storing data of all normal firmware programs in a memory;
judging whether abnormal firmware path information corresponding to the first flash memory and/or the second flash memory exists or not;
if abnormal firmware path information corresponding to the first flash memory exists, sending a chip selection signal switching request to switch the chip selection signal to point to the first flash memory, and writing the data of all normal firmware programs in the memory into the first flash memory;
if abnormal firmware path information corresponding to the second flash memory exists, sending a chip selection signal switching request to switch the chip selection signal to point to the second flash memory, and writing the data of all normal firmware programs in the memory into the second flash memory;
determining to complete repair of the abnormal firmware program in response to complete updating of all flash memories with abnormal firmware path information;
and starting a configuration information synchronization process to synchronize the second flash memory with the first flash memory, and determining that the control system normally completes operation.
6. The method as recited in claim 5, further comprising:
And if the abnormal starting identifier is in an unset state, starting a configuration information synchronization process to synchronize the second flash memory with the first flash memory, and determining that the control system normally completes operation.
7. The method of claim 1, wherein the step of setting an abnormal start flag comprises:
responding to the monitoring chip receiving the switch chip selection signal request, judging whether the abnormal starting mark is in a set state or not;
if the abnormal starting identifier is in an unset state, updating the abnormal starting identifier to be in a set state, and reading a flash memory corresponding to the switched chip selection signal;
and if the abnormal starting mark is in a set state, reading the flash memory corresponding to the switched chip select signal.
8. The method as recited in claim 1, further comprising:
if the firmware programs of all the partitions in the first flash memory are loaded and verified successfully, determining that all the firmware programs in the first flash memory are normal firmware programs, starting the control system through all the firmware programs in the first flash memory, and starting a dog feeding signal to determine that the starting of the control system is completed.
9. The method as recited in claim 1, further comprising:
If the first flash memory and the second flash memory have the partitions with the firmware programs failing to check, resetting the control system and stopping starting the control system after waiting for the timeout of the watchdog.
10. The method of claim 1, wherein the step of sequentially loading and verifying firmware programs of each partition in the first flash memory comprises:
and sequentially loading and checking the firmware programs of all the partitions in the first flash memory from the firmware programs of the initial partition.
11. The method of claim 1, wherein the monitoring chip comprises a complex programmable logic device and the control system comprises a baseboard management controller.
12. A system start-up system, comprising:
the acquisition unit is used for responding to the received starting signal, acquiring a chip selection signal through the monitoring chip to determine a first flash memory which is read when the starting signal is received;
the first loading verification unit is used for sequentially loading and verifying the firmware programs of all the partitions in the first flash memory, and timing by using a watchdog;
the switching unit is used for sending a switching chip selection signal request to switch the chip selection signal to point to the second flash memory in the time of the watchdog timing when the verification of the firmware program of the partition in the first flash memory fails, loading and verifying the firmware program of the partition corresponding to the partition which fails to verify in the second flash memory, and setting an abnormal starting identifier;
The second loading verification unit is used for sequentially loading and verifying the firmware programs of all the partitions after the corresponding partitions in the second flash memory if the firmware programs of the corresponding partitions in the second flash memory pass verification;
and the starting unit is used for starting the control system through all the firmware programs loaded and checked successfully in the first flash memory and the second flash memory if the firmware programs of all the partitions after the corresponding partitions in the second flash memory are loaded and checked successfully and the watchdog is not overtime.
13. A computer device, comprising:
at least one processor; and
a memory storing a computer program executable on the processor, wherein the processor performs the steps of the method of any one of claims 1 to 11 when the program is executed.
14. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor performs the steps of the method according to any one of claims 1 to 11.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118860758A (en) * | 2024-09-10 | 2024-10-29 | 管芯微技术(上海)有限公司 | A power-on startup method, device, electronic device and computer-readable storage medium based on a baseboard management controller system |
| CN119987874A (en) * | 2025-01-06 | 2025-05-13 | 山东云海国创云计算装备产业创新中心有限公司 | Chip startup method, chip, electronic device and storage medium |
| CN120255970A (en) * | 2025-05-29 | 2025-07-04 | 苏州元脑智能科技有限公司 | Baseboard management controller startup method, computer equipment, medium and product |
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2023
- 2023-09-07 CN CN202311148976.9A patent/CN117034296A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118860758A (en) * | 2024-09-10 | 2024-10-29 | 管芯微技术(上海)有限公司 | A power-on startup method, device, electronic device and computer-readable storage medium based on a baseboard management controller system |
| CN118860758B (en) * | 2024-09-10 | 2025-09-05 | 管芯微技术(上海)有限公司 | A power-on startup method, device, electronic device and computer-readable storage medium based on a baseboard management controller system |
| CN119987874A (en) * | 2025-01-06 | 2025-05-13 | 山东云海国创云计算装备产业创新中心有限公司 | Chip startup method, chip, electronic device and storage medium |
| CN120255970A (en) * | 2025-05-29 | 2025-07-04 | 苏州元脑智能科技有限公司 | Baseboard management controller startup method, computer equipment, medium and product |
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