CN117081513B - Gain amplifying method and circuit for voltage-controlled oscillator, phase-locked loop and clock chip - Google Patents
Gain amplifying method and circuit for voltage-controlled oscillator, phase-locked loop and clock chip Download PDFInfo
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- H—ELECTRICITY
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
Description
技术领域Technical field
本发明涉及电数字数据技术领域，尤其涉及一种压控振荡器增益放大方法与电路、锁相环及时钟芯片。The present invention relates to the technical field of electrical digital data, and in particular to a voltage-controlled oscillator gain amplification method and circuit, a phase-locked loop and a clock chip.
背景技术Background technique
在模拟锁相环设计中，压控振荡器（Voltage-Controlled Oscillator, VCO）的增益K VCO如果设计得偏小，那么在同样的控制电压V cont范围内能覆盖的频率范围就会偏小。为了在设计中采用较小的增益K VCO来实现期望的控制环路，同时解决覆盖范围偏小问题，经常采用粗调制做慢环和细调制做快环两种环路结合的方法。其中，用到慢环放大增益K VCO的电路通常需要根据控制电压V cont的工作范围来调整放大的输入输出曲线。目前，常用的减法电路方案需要额外的驱动电路和驱动电流，增加了电路环节引入的噪声，降低了锁相环性能，且增加了成本和功耗。In the design of analog phase-locked loop, if the gain K VCO of the voltage-controlled oscillator (VCO) is designed to be too small, the frequency range that can be covered within the same control voltage V cont range will be too small. In order to use a smaller gain K VCO in the design to achieve the desired control loop and at the same time solve the problem of small coverage, the method of combining coarse modulation as a slow loop and fine modulation as a fast loop is often used. Among them, circuits using slow loop amplification gain K VCO usually need to adjust the amplified input and output curve according to the working range of the control voltage V cont . Currently, commonly used subtraction circuit solutions require additional drive circuits and drive currents, which increase the noise introduced into the circuit, reduce phase-locked loop performance, and increase cost and power consumption.
发明内容Contents of the invention
为了解决上述问题，本发明提出一种压控振荡器增益放大方法与电路、锁相环及时钟芯片，不需要额外的驱动电路，不会额外消耗面积和功耗，同时不会增加额外的噪声。In order to solve the above problems, the present invention proposes a voltage-controlled oscillator gain amplification method and circuit, a phase-locked loop and a clock chip, which do not require additional drive circuits, will not consume additional area and power consumption, and will not increase additional noise. .
本发明采用的技术方案如下：The technical solutions adopted by the present invention are as follows:
一种压控振荡器增益放大方法，包括以下步骤：A voltage-controlled oscillator gain amplification method includes the following steps:
S1. 将控制电压V cont输入带失调电压的运算放大器，所述带失调电压的运算放大器的正相输入端接入控制电压V cont，负相输入端通过第二电阻接地，输出端依次通过第一电阻和第二电阻接地，且输出端产生目标电压V O；S1. Input the control voltage V cont into the operational amplifier with offset voltage. The positive input terminal of the operational amplifier with offset voltage is connected to the control voltage V cont . The negative input terminal is connected to ground through the second resistor, and the output terminal passes through the second resistor in turn. The first resistor and the second resistor are connected to ground, and the output terminal generates the target voltage V O ;
S2. 通过所述带失调电压的运算放大器产生的目标电压Vo控制压控振荡器的调谐频率，所述失调电压的取值包括压控振荡器的最小调谐频率所对应的电压。S2. The tuning frequency of the voltage controlled oscillator is controlled by the target voltage Vo generated by the operational amplifier with offset voltage, and the value of the offset voltage includes the voltage corresponding to the minimum tuning frequency of the voltage controlled oscillator.
进一步地，所述带失调电压的运算放大器包括NMOS输入级电路，所述NMOS输入级电路包括电流源、第一NMOS管、第二NMOS管、第三电阻和第四电阻，所述第一NMOS管的栅极作为正相输入端，所述第二NMOS管的栅极作为负相输入端，所述第一NMOS管或第二NMOS管的源极通过第三电阻连接电流源，所述电流源通过第四电阻接地；Further, the operational amplifier with offset voltage includes an NMOS input stage circuit. The NMOS input stage circuit includes a current source, a first NMOS transistor, a second NMOS transistor, a third resistor and a fourth resistor. The first NMOS The gate of the tube serves as the positive-phase input terminal, the gate of the second NMOS tube serves as the negative-phase input terminal, the source of the first NMOS tube or the second NMOS tube is connected to the current source through a third resistor, and the current The source is connected to ground through the fourth resistor;
所述失调电压的计算方法包括：The calculation method of the offset voltage includes:
V OS=I 1*R 3=(V ref/R 4)*R 3 V OS = I 1 * R 3 =( V ref / R 4 )* R 3
其中，V OS为失调电压，I 1为电流源提供的电流，R 3为第三电阻阻值，R 4为第四电阻阻值，V ref为基准电压。Among them, V OS is the offset voltage, I 1 is the current provided by the current source, R 3 is the third resistor resistance, R 4 is the fourth resistor resistance, and V ref is the reference voltage.
进一步地，所述带失调电压的运算放大器包括PMOS输入级电路，所述PMOS输入级电路包括电流源、第一PMOS管、第二PMOS管、第三电阻和第四电阻，所述第一PMOS管的栅极作为正相输入端，所述第二PMOS管的栅极作为负相输入端，所述第一PMOS管或第二PMOS管的源极通过第三电阻连接电流源，所述电流源通过第四电阻接地；Further, the operational amplifier with offset voltage includes a PMOS input stage circuit. The PMOS input stage circuit includes a current source, a first PMOS tube, a second PMOS tube, a third resistor and a fourth resistor. The first PMOS The gate of the tube serves as the positive-phase input terminal, the gate of the second PMOS tube serves as the negative-phase input terminal, the source of the first PMOS tube or the second PMOS tube is connected to the current source through a third resistor, and the current The source is connected to ground through the fourth resistor;
所述失调电压的计算方法包括：The calculation method of the offset voltage includes:
V OS=I 1*R 3=(V ref/R 4)*R 3 V OS = I 1 * R 3 =( V ref / R 4 )* R 3
其中，V OS为失调电压，I 1为电流源提供的电流，R 3为第三电阻阻值，R 4为第四电阻阻值，V ref为基准电压。Among them, V OS is the offset voltage, I 1 is the current provided by the current source, R 3 is the third resistor resistance, R 4 is the fourth resistor resistance, and V ref is the reference voltage.
进一步地，所述目标电压Vo的计算方法包括：Further, the calculation method of the target voltage Vo includes:
V O=((R 1+R 2)/R 2)*(V cont-V OS) V O =(( R 1 + R 2 )/ R 2 )*( V cont - V OS )
其中，R 1为第一电阻阻值，R 2为第二电阻阻值，V OS为失调电压。Among them, R 1 is the resistance of the first resistor, R 2 is the resistance of the second resistor, and V OS is the offset voltage.
一种压控振荡器增益放大电路，包括：A voltage controlled oscillator gain amplifier circuit, including:
带失调电压的运算放大器、第一电阻和第二电阻，所述带失调电压的运算放大器的正相输入端接入控制电压V cont，负相输入端通过第二电阻接地，输出端依次通过第一电阻和第二电阻接地，且输出端产生目标电压V O控制压控振荡器的调谐频率，所述失调电压的取值包括压控振荡器的最小调谐频率所对应的电压。An operational amplifier with offset voltage, a first resistor and a second resistor. The positive input terminal of the operational amplifier with offset voltage is connected to the control voltage V cont , the negative input terminal is grounded through the second resistor, and the output terminal is connected through the third resistor in turn. The first resistor and the second resistor are grounded, and the output terminal generates a target voltage V O to control the tuning frequency of the voltage-controlled oscillator. The value of the offset voltage includes the voltage corresponding to the minimum tuning frequency of the voltage-controlled oscillator.
进一步地，所述带失调电压的运算放大器包括NMOS输入级电路，所述NMOS输入级电路包括电流源、第一NMOS管、第二NMOS管、第三电阻和第四电阻，所述第一NMOS管的栅极作为正相输入端，漏极通过第三电阻连接电流源；所述第二NMOS管的栅极作为负相输入端，漏极连接电流源；所述电流源通过第四电阻接地；Further, the operational amplifier with offset voltage includes an NMOS input stage circuit. The NMOS input stage circuit includes a current source, a first NMOS transistor, a second NMOS transistor, a third resistor and a fourth resistor. The first NMOS The gate of the tube serves as a positive-phase input terminal, and the drain is connected to the current source through a third resistor; the gate of the second NMOS tube serves as a negative-phase input terminal, and the drain is connected to the current source; the current source is connected to ground through a fourth resistor. ;
所述失调电压的计算方法包括：The calculation method of the offset voltage includes:
Vos=I 1*R 3=(V ref/R 4)*R 3 Vos = I 1 * R 3 =( V ref / R 4 )* R 3
其中，V OS为失调电压，且取值为正或负，I 1为电流源提供的电流，R 3为第三电阻阻值，R 4为第四电阻阻值，V ref为基准电压。Among them, V OS is the offset voltage, and the value is positive or negative, I 1 is the current provided by the current source, R 3 is the third resistor resistance, R 4 is the fourth resistor resistance, and V ref is the reference voltage.
进一步地，所述带失调电压的运算放大器包括PMOS输入级电路，所述PMOS输入级电路包括电流源、第一PMOS管、第二PMOS管、第三电阻和第四电阻，所述第一PMOS管的栅极作为正相输入端，源极通过第三电阻连接电流源；所述第二PMOS管的栅极作为负相输入端，源极连接电流源；所述电流源通过第四电阻接地；Further, the operational amplifier with offset voltage includes a PMOS input stage circuit. The PMOS input stage circuit includes a current source, a first PMOS tube, a second PMOS tube, a third resistor and a fourth resistor. The first PMOS The gate of the tube is used as a positive-phase input terminal, and the source is connected to the current source through a third resistor; the gate of the second PMOS tube is used as a negative-phase input terminal, and the source is connected to the current source; the current source is connected to ground through a fourth resistor. ;
所述失调电压的计算方法包括：The calculation method of the offset voltage includes:
V OS=I 1*R 3=(V ref/R 4)*R 3 V OS = I 1 * R 3 =( V ref / R 4 )* R 3
其中，V OS为失调电压，且取值为正或负，I 1为电流源提供的电流，R 3为第三电阻阻值，R 4为第四电阻阻值，V ref为基准电压。Among them, V OS is the offset voltage, and the value is positive or negative, I 1 is the current provided by the current source, R 3 is the third resistor resistance, R 4 is the fourth resistor resistance, and V ref is the reference voltage.
进一步地，所述目标电压Vo的计算方法包括：Further, the calculation method of the target voltage Vo includes:
V O=((R 1+R 2)/R 2)*(V cont-V OS) V O =(( R 1 + R 2 )/ R 2 )*( V cont - V OS )
其中，R 1为第一电阻阻值，R 2为第二电阻阻值，V OS为失调电压。Among them, R 1 is the resistance of the first resistor, R 2 is the resistance of the second resistor, and V OS is the offset voltage.
一种锁相环，包括上述压控振荡器增益放大电路，还包括依次电连接的鉴相器、低通滤波器和压控振荡器。A phase-locked loop includes the above-mentioned voltage-controlled oscillator gain amplifier circuit, and also includes a phase detector, a low-pass filter and a voltage-controlled oscillator that are electrically connected in sequence.
一种时钟芯片，包括上述锁相环，所述锁相环被配置为多环路控制锁相环。A clock chip includes the above-mentioned phase-locked loop, and the phase-locked loop is configured as a multi-loop control phase-locked loop.
本发明的有益效果在于：The beneficial effects of the present invention are:
相比常用的减法电路方案，本发明不需要额外的驱动电路和驱动电流，不会额外消耗面积和功耗，可减少电路环节引入的噪声，提高锁相环性能，节省成本和功耗。Compared with commonly used subtraction circuit solutions, the present invention does not require additional drive circuits and drive currents, does not consume additional area and power consumption, can reduce noise introduced by circuit links, improve phase-locked loop performance, and save costs and power consumption.
附图说明Description of the drawings
图1 锁相环示意图；Figure 1 Schematic diagram of phase locked loop;
图2 压控振荡器的增益曲线示意图；Figure 2 Schematic diagram of the gain curve of a voltage controlled oscillator;
图3 锁相环的线性模型示意图；Figure 3 Schematic diagram of the linear model of the phase-locked loop;
图4 双环路压控振荡器示意图；Figure 4 Schematic diagram of dual-loop voltage controlled oscillator;
图5 常见的运放组成的减法电路示意图；Figure 5 is a schematic diagram of a common subtraction circuit composed of operational amplifiers;
图6 不带静态电流的减法放大电路示意图；Figure 6 Schematic diagram of the subtractive amplifier circuit without quiescent current;
图7 带额外驱动电路的运算放大器电路；Figure 7 Operational amplifier circuit with additional drive circuit;
图8 压控振荡器增益放大电路示意图；Figure 8 Schematic diagram of voltage controlled oscillator gain amplification circuit;
图9 NMOS输入级电路示意图；Figure 9 NMOS input stage circuit diagram;
图10 PMOS输入级电路示意图；Figure 10 Schematic diagram of PMOS input stage circuit;
图11 不同的电阻值对应的输入输出曲线示意图。Figure 11 Schematic diagram of input and output curves corresponding to different resistance values.
附图标记：PD-鉴相器，LPF-低通滤波器，VCO-压控振荡器，PFD-鉴频鉴相器，CP-电荷泵，AMP-运算放大器；NMOS1-第一NMOS管，NMOS2-第二NMOS管，PMOS1-第一PMOS管，PMOS2-第二PMOS管；K VCO-增益，ω out-输出角频率，V cont-控制电压，V C-第二控制电压，V ref-基准电压，V OS-失调电压，V O-目标电压，I 1-第一电流，I 2-第二电流。Reference signs: PD - phase detector, LPF - low pass filter, VCO - voltage controlled oscillator, PFD - phase frequency detector, CP - charge pump, AMP - operational amplifier; NMOS 1 - the first NMOS tube, NMOS 2 - the second NMOS tube, PMOS 1 - the first PMOS tube, PMOS 2 - the second PMOS tube; K VCO - gain, ω out - output angular frequency, V cont - control voltage, V C - second control voltage, V ref - reference voltage, V OS - offset voltage, V O - target voltage, I 1 - first current, I 2 - second current.
具体实施方式Detailed ways
为了对本发明的技术特征、目的和效果有更加清楚的理解，现说明本发明的具体实施方式。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明，即所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific implementation modes of the present invention will now be described. It should be understood that the specific embodiments described here are only used to explain the present invention and are not used to limit the present invention. That is, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without any creative work fall within the scope of protection of the present invention.
实施例1Example 1
如图1所示为一种锁相环示意图，其包括鉴相器PD、低通滤波器LPF和压控振荡器VCO，其中压控振荡器VCO的增益曲线如图2所示，输入一个控制电压V cont，输出一个同控制电压V cont相关的振荡频率为ω out的波形，且有：Figure 1 shows a schematic diagram of a phase-locked loop, which includes a phase detector PD, a low-pass filter LPF and a voltage-controlled oscillator VCO. The gain curve of the voltage-controlled oscillator VCO is shown in Figure 2. Input a control The voltage V cont outputs a waveform with an oscillation frequency ω out related to the control voltage V cont , and has:
ω out=ω 0+K VCO *V cont ω out = ω 0 + K VCO *V cont
其中，ω out为输出角频率，ω 0为自由振荡角频率，K VCO为增益，V cont为控制电压。Among them, ω out is the output angular frequency, ω 0 is the free oscillation angular frequency, K VCO is the gain, and V cont is the control voltage.
图3展示了线性化后的电荷泵锁相环模型，增益K VCO作为压控振荡器VCO的关键参数体现到环路内部。Figure 3 shows the linearized charge pump phase-locked loop model. The gain K VCO is reflected inside the loop as a key parameter of the voltage controlled oscillator VCO.
从图2可以看到，如果增益K VCO比较小，那么总的频率变化范围就可能比较小。为了实现增益K VCO较小，同时输出角频率ω out的覆盖范围足够，通常采用多环路压控振荡器VCO来实现。As can be seen from Figure 2, if the gain K VCO is relatively small, then the total frequency variation range may be relatively small. In order to achieve a small gain K VCO and a sufficient coverage range of the output angular frequency ω out , a multi-loop voltage controlled oscillator VCO is usually used.
图4展示了一个双环路的压控振荡器VCO，控制电压V cont额外经过一个放大电路（图中X2），再经过一个低通滤波器LPF，得到低频时候的输出角频率：Figure 4 shows a dual-loop voltage controlled oscillator VCO. The control voltage V cont passes through an additional amplifier circuit (X2 in the figure), and then passes through a low-pass filter LPF to obtain the output angular frequency at low frequency:
ω out=V cont*K VCO+V C*K VCO=V cont*K VCO+2*V cont*K VCO=K VCO*3*V cont ω out = V cont * K VCO + V C * K VCO = V cont * K VCO +2* V cont * K VCO = K VCO *3* V cont
其中，V C为第二控制电压。通过调节放大电路的放大倍数，实现同样的控制电压V cont变化范围，更宽的输出角频率ω out。Among them, VC is the second control voltage. By adjusting the amplification factor of the amplifier circuit, the same change range of control voltage V cont and a wider output angular frequency ω out can be achieved.
基于图2的增益曲线，放大电路需要先减去一个固定电压再放大，所以实现起来通常需要带减法的放大电路。通常带减法的放大电路如图5所示，其中V p=V cont=V n，V O/R 1=(V p-V ref)/R2，如果R 1=2R，R 2=R，那么目标电压V O=(R 1/R 2)*(V cont-V ref)=2*(V cont-V ref)，由于第二电流I 2的存在，基准电压V ref必须具有驱动能力，因为第二电流I 2的大小会随着控制电压V cont的变化而变化。Based on the gain curve in Figure 2, the amplifier circuit needs to subtract a fixed voltage before amplifying, so implementation usually requires an amplifier circuit with subtraction. The usual amplifier circuit with subtraction is shown in Figure 5, where V p = V cont = V n , V O / R 1 =( V p - V ref )/R2, if R 1 =2R, R 2 =R, then Target voltage V O =( R 1 / R 2 )*( V cont - V ref )=2*( V cont - V ref ). Due to the existence of the second current I 2 , the reference voltage V ref must have driving capability because The magnitude of the second current I 2 changes with the change of the control voltage V cont .
如图7所示，图6的基准电压V ref产生需要由额外的驱动电路来实现，这样有两个缺点：（1）消耗额外的电流和面积；（2）运算放大器AMP1会引入额外的噪声。As shown in Figure 7, the reference voltage V ref of Figure 6 needs to be generated by an additional drive circuit, which has two disadvantages: (1) It consumes additional current and area; (2) The operational amplifier AMP1 will introduce additional noise .
如图8所示，本实施例提供了一种压控振荡器增益放大方法及电路，采用带失调电压V OS的运算放大器AMP实现减法和放大的控制电压V cont，其中目标电压为：As shown in Figure 8, this embodiment provides a voltage-controlled oscillator gain amplification method and circuit, using an operational amplifier AMP with an offset voltage V OS to achieve subtraction and amplification of the control voltage V cont , where the target voltage is:
V O=((R 1+R 2)/R 2)*(V cont-V OS) V O =(( R 1 + R 2 )/ R 2 )*( V cont - V OS )
其中，R 1为第一电阻阻值，R 2为第二电阻阻值。Among them, R 1 is the resistance of the first resistor, and R 2 is the resistance of the second resistor.
本实施例的第二电阻R 2端接地，不需要额外的驱动电路，不会额外消耗面积和功耗，同时不会增加额外的噪声。In this embodiment, the second resistor R2 terminal is connected to the ground, so no additional driving circuit is required, no additional area and power consumption is consumed, and no additional noise is added.
具体地，本实施例的压控振荡器增益放大电路包括带失调电压V OS的运算放大器AMP、第一电阻R 1和第二电阻R 2，其中运算放大器AMP的正相输入端接入控制电压V cont，负相输入端通过第二电阻R 2接地，输出端依次通过第一电阻R 1和第二电阻R 2接地，且输出端产生目标电压V O控制压控振荡器VCO的调谐频率，失调电压V OS的取值包括压控振荡器VCO的最小调谐频率所对应的电压。Specifically, the voltage-controlled oscillator gain amplification circuit of this embodiment includes an operational amplifier AMP with an offset voltage V OS , a first resistor R 1 and a second resistor R 2 , wherein the non-inverting input terminal of the operational amplifier AMP is connected to the control voltage V cont , the negative phase input terminal is grounded through the second resistor R 2 , the output terminal is grounded through the first resistor R 1 and the second resistor R 2 in turn, and the output terminal generates the target voltage V O to control the tuning frequency of the voltage controlled oscillator VCO, The value of the offset voltage V OS includes the voltage corresponding to the minimum tuning frequency of the voltage controlled oscillator VCO.
相应地，本实施例的压控振荡器增益放大方法包括以下步骤：Correspondingly, the voltage controlled oscillator gain amplification method of this embodiment includes the following steps:
S1. 将控制电压V cont输入带失调电压V OS的运算放大器AMP，运算放大器AMP的正相输入端接入控制电压V cont，负相输入端通过第二电阻R 2接地，输出端依次通过第一电阻R 1和第二电阻R 2接地，且输出端产生目标电压V O；S1. Input the control voltage V cont into the operational amplifier AMP with the offset voltage V OS . The positive input terminal of the operational amplifier AMP is connected to the control voltage V cont . The negative input terminal is grounded through the second resistor R 2. The output terminal passes through the second resistor R 2 in turn. A resistor R 1 and a second resistor R 2 are connected to ground, and the output terminal generates a target voltage V O ;
S2. 通过运算放大器AMP产生的目标电压V O控制压控振荡器VCO的调谐频率，失调电压V OS的取值包括压控振荡器VCO的最小调谐频率所对应的电压。S2. The tuning frequency of the voltage controlled oscillator VCO is controlled by the target voltage V O generated by the operational amplifier AMP. The value of the offset voltage V OS includes the voltage corresponding to the minimum tuning frequency of the voltage controlled oscillator VCO.
图9和图10展示了本实施例的失调运放的两种实现方案，PMOS和NMOS输入级电路分别对应不同的工作电压。Figures 9 and 10 show two implementation schemes of the offset operational amplifier in this embodiment. The PMOS and NMOS input stage circuits respectively correspond to different operating voltages.
NMOS输入级电路包括电流源、第一NMOS管NMOS1、第二NMOS管NMOS2、第三电阻R 3和第四电阻R 4，第一NMOS管NMOS1的栅极作为正相输入端，第二NMOS管NMOS2的栅极作为负相输入端，第一NMOS管NMOS1或第二NMOS管NMOS2的源极通过第三电阻R 3连接电流源，电流源通过第四电阻R 4接地。其中，当第一NMOS管NMOS1的源极通过第三电阻R 3连接电流源时，如图9所示，失调电压V OS取值为正；当第二NMOS管NMOS2的源极通过第三电阻R 3连接电流源时，失调电压V OS取值为负。The NMOS input stage circuit includes a current source, a first NMOS transistor NMOS 1 , a second NMOS transistor NMOS 2 , a third resistor R 3 and a fourth resistor R 4 . The gate of the first NMOS transistor NMOS 1 serves as a positive input terminal. The gate of the two NMOS transistors NMOS 2 serves as the negative phase input terminal. The source of the first NMOS transistor NMOS 1 or the second NMOS transistor NMOS 2 is connected to the current source through the third resistor R 3 , and the current source is connected to the ground through the fourth resistor R 4 . Among them, when the source of the first NMOS transistor NMOS 1 is connected to the current source through the third resistor R 3 , as shown in Figure 9, the offset voltage V OS takes a positive value; when the source of the second NMOS transistor NMOS 2 passes through the third resistor R 3, the offset voltage V OS takes a positive value. When the three resistors R 3 are connected to the current source, the offset voltage V OS takes a negative value.
PMOS输入级电路包括电流源、第一PMOS管PMOS1、第二PMOS管PMOS2、第三电阻R 3和第四电阻R 4，第一PMOS管PMOS1的栅极作为正相输入端，第二PMOS管PMOS2的栅极作为负相输入端，第一PMOS管PMOS1或第二PMOS管PMOS2的源极通过第三电阻R 3连接电流源，电流源通过第四电阻R 4接地。当第一PMOS管PMOS1的源极通过第三电阻R 3连接电流源时，如图10所示，失调电压V OS取值为负；当第二PMOS管PMOS2的源极通过第三电阻R 3连接电流源时，失调电压V OS取值为正。The PMOS input stage circuit includes a current source, a first PMOS transistor PMOS 1 , a second PMOS transistor PMOS 2 , a third resistor R 3 and a fourth resistor R 4 . The gate of the first PMOS transistor PMOS 1 serves as the non-inverting input terminal. The gate of the two PMOS transistors PMOS 2 serves as the negative phase input terminal. The source of the first PMOS transistor PMOS 1 or the second PMOS transistor PMOS 2 is connected to the current source through the third resistor R 3 , and the current source is connected to the ground through the fourth resistor R 4 . When the source of the first PMOS transistor PMOS 1 is connected to the current source through the third resistor R 3 , as shown in Figure 10, the offset voltage V OS takes a negative value; when the source of the second PMOS transistor PMOS 2 passes through the third resistor When R 3 is connected to the current source, the offset voltage V OS takes a positive value.
优选地，失调电压的计算方法可以为：Preferably, the calculation method of offset voltage can be:
Vos=I 1*R 3=(V ref/R 4)*R 3 Vos = I 1 * R 3 =( V ref / R 4 )* R 3
其中，I 1为电流源提供的电流，V ref为基准电压。Among them, I 1 is the current provided by the current source, and V ref is the reference voltage.
如图11所示为不同的电阻值对应的输入输出曲线。Figure 11 shows the input and output curves corresponding to different resistance values.
实施例2Example 2
本实施例在实施例1的基础上：This embodiment is based on Embodiment 1:
本实施例提供了一种锁相环，包括实施例1的压控振荡器增益放大电路，还包括依次电连接的鉴相器PD、低通滤波器LPF和压控振荡器VCO。This embodiment provides a phase-locked loop, which includes the voltage-controlled oscillator gain amplification circuit of Embodiment 1, and also includes a phase detector PD, a low-pass filter LPF, and a voltage-controlled oscillator VCO that are electrically connected in sequence.
实施例3Example 3
本实施例在实施例2的基础上：This embodiment is based on Embodiment 2:
本实施例提供了一种时钟芯片，包括实施例2的锁相环，该锁相环被配置为多环路控制锁相环。This embodiment provides a clock chip, including the phase-locked loop of Embodiment 2, and the phase-locked loop is configured as a multi-loop control phase-locked loop.
以上所述仅是本发明的优选实施方式，应当理解本发明并非局限于本文所披露的形式，不应看作是对其他实施例的排除，而可用于各种其他组合、修改和环境，并能够在本文所述构想范围内，通过上述教导或相关领域的技术或知识进行改动。而本领域人员所进行的改动和变化不脱离本发明的精神和范围，则都应在本发明所附权利要求的保护范围内。The above are only preferred embodiments of the present invention. It should be understood that the present invention is not limited to the form disclosed herein and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and Modifications can be made within the scope of the ideas described herein through the above teachings or technology or knowledge in related fields. Any modifications and changes made by those skilled in the art that do not depart from the spirit and scope of the present invention shall be within the protection scope of the appended claims of the present invention.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1543075A (en) * | 2003-04-30 | 2004-11-03 | ���Ӱ뵼������˾ | Capture range control mechanism for voltage controlled oscillators |
| CN101262225A (en) * | 2008-04-11 | 2008-09-10 | 湖南大学 | Lock phase loop frequency mixer |
| CN101873132A (en) * | 2009-04-23 | 2010-10-27 | 瑞萨电子株式会社 | The PLL circuit |
| CN106559072A (en) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | Self-biased phase-locked loop |
| US10686455B1 (en) * | 2019-08-14 | 2020-06-16 | Teledyne Defense Electronics, Llc | Digital high speed acquisition system for phase locked loops |
| CN112242841A (en) * | 2020-11-25 | 2021-01-19 | 灿芯半导体(苏州)有限公司 | A phase-locked loop circuit with high power supply noise rejection ratio |
| CN216672986U (en) * | 2021-12-22 | 2022-06-03 | 南京沁恒微电子股份有限公司 | A loop filter and analog phase-locked loop including the loop filter |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6661297B2 (en) * | 2000-12-20 | 2003-12-09 | Tektronix, Inc. | Multi-octave wideband voltage controlled oscillator |
| KR100433634B1 (en) * | 2002-04-19 | 2004-05-31 | 한국전자통신연구원 | Adaptive loop gain control circuit for voltage controlled oscillator |
| US7663415B2 (en) * | 2005-12-30 | 2010-02-16 | Stmicroelectronics Pvt. Ltd. | Phase locked loop (PLL) method and architecture |
| US8643444B2 (en) * | 2012-06-04 | 2014-02-04 | Broadcom Corporation | Common reference crystal systems |
-
2023
- 2023-10-16 CN CN202311331073.4A patent/CN117081513B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1543075A (en) * | 2003-04-30 | 2004-11-03 | ���Ӱ뵼������˾ | Capture range control mechanism for voltage controlled oscillators |
| CN101262225A (en) * | 2008-04-11 | 2008-09-10 | 湖南大学 | Lock phase loop frequency mixer |
| CN101873132A (en) * | 2009-04-23 | 2010-10-27 | 瑞萨电子株式会社 | The PLL circuit |
| CN106559072A (en) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | Self-biased phase-locked loop |
| US10686455B1 (en) * | 2019-08-14 | 2020-06-16 | Teledyne Defense Electronics, Llc | Digital high speed acquisition system for phase locked loops |
| CN112242841A (en) * | 2020-11-25 | 2021-01-19 | 灿芯半导体(苏州)有限公司 | A phase-locked loop circuit with high power supply noise rejection ratio |
| CN216672986U (en) * | 2021-12-22 | 2022-06-03 | 南京沁恒微电子股份有限公司 | A loop filter and analog phase-locked loop including the loop filter |
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