CN117294306B - Input buffer circuit capable of inhibiting sampling switch from kicking back and improving linearity - Google Patents
Input buffer circuit capable of inhibiting sampling switch from kicking back and improving linearity Download PDFInfo
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- CN117294306B CN117294306B CN202311293941.4A CN202311293941A CN117294306B CN 117294306 B CN117294306 B CN 117294306B CN 202311293941 A CN202311293941 A CN 202311293941A CN 117294306 B CN117294306 B CN 117294306B
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- 238000005070 sampling Methods 0.000 title claims abstract description 69
- 230000002401 inhibitory effect Effects 0.000 title claims abstract description 8
- 230000001629 suppression Effects 0.000 claims abstract description 13
- 238000006243 chemical reaction Methods 0.000 claims abstract description 12
- 238000006880 cross-coupling reaction Methods 0.000 claims abstract description 4
- 239000003990 capacitor Substances 0.000 claims description 63
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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Abstract
The invention discloses an input buffer circuit capable of inhibiting a sampling switch from kicking back and improving linearity, which comprises a level conversion circuit, a sampling switch kickback inhibition circuit, a current source load circuit and a sampling circuit, wherein the level conversion circuit is used for converting the level of the input buffer circuit into a low-level voltage; the level shift circuit is used as a level shift circuit for inputting the voltage of the drain terminal of the input tube in the buffer; the sampling switch kick-back suppression circuit is used as an input circuit of the input buffer and a kick-back cross-coupling circuit; the current source load circuit is used for inputting a current source load of the buffer and a current source bias generating circuit; the sampling circuit is a sampling network of input buffers.
Description
Technical Field
The invention belongs to the field of integrated circuit analog-to-digital converters, and particularly relates to an input buffer circuit capable of inhibiting a sampling switch from kicking back and improving linearity.
Background
As the feature size of semiconductor processes is smaller, the sampling rate of high-speed Analog-to-digital converter (ADC) is greatly improved, and the high-linearity input buffer design technology is also greatly developed. The input buffer is used for connecting the chip with the outside world, is mainly used for improving the driving capability of external analog signals and isolating the influence of the sampling network kickback noise on the input signals. Not only determines the ADC input bandwidth, but its linearity characteristics determine the upper limit of linearity that can be achieved by the overall ADC. Particularly, as the ADC sampling rate and the signal input frequency are continuously increased, the sampling network operation rate is increased, and kickback noise gradually becomes a key point for limiting the performance of the input buffer.
The conventional method for processing kickback noise by the input buffer generally increases the current of the input buffer, ensures that burrs caused by the sampling switch action can be recovered in a short time, and further ensures the performance of the input buffer, but with the continuous increase of the sampling frequency, the quiescent current required for eliminating the burrs caused by the switching action increases exponentially. An increase in quiescent current will lead to a dramatic increase in power consumption of the chip on the one hand and will limit the swing of the input signal on the other hand.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides the input buffer circuit capable of inhibiting the sampling switch from kicking back and improving the linearity.
In order to solve the problems in the prior art, the invention adopts the following technical scheme:
an input buffer circuit capable of inhibiting a sampling switch from kicking back and improving linearity comprises a level conversion circuit, a sampling switch kickback inhibiting circuit, a current source load circuit and a sampling circuit.
The level shift circuit is used as a level shift circuit for inputting the voltage of the drain terminal of the input tube in the buffer;
The sampling switch kick-back suppression circuit is used as an input circuit of the input buffer and a kick-back cross-coupling circuit;
the current source load circuit is used for inputting a current source load of the buffer and a current source bias generating circuit;
the sampling circuit is a sampling network of input buffers.
Further, the level conversion circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first N-type MOS tube, a second N-type MOS tube, a third N-type MOS tube and a fourth N-type MOS tube, wherein the positive electrode of the first resistor is connected with a fixed reference VREF3, and the negative electrode of the first resistor is connected with the grid electrode of the first N-type MOS tube and the positive electrode of the first capacitor; one pole of the second resistor is connected with the fixed reference VREF2, the other pole of the second resistor is respectively connected with the grid electrode of the third N-type MOS tube, the positive pole of the second capacitor and the negative pole of the first capacitor, the drain electrode of the third N-type MOS tube is connected with the source electrode of the first N-type MOS tube, the drain electrode of the first N-type MOS tube is connected with the power supply, one pole of the third resistor is connected with the fixed reference VREF3, and the other pole of the third resistor is connected with the grid electrode of the second N-type MOS tube and the positive pole of the third capacitor; one pole of the fourth resistor is connected with the fixed reference VREF2, the other pole of the fourth resistor is connected with the grid electrode of the fourth N-type MOS tube, the positive pole of the fourth capacitor and the negative pole of the third capacitor, the drain electrode of the fourth N-type MOS tube is connected with the source electrode of the second N-type MOS tube, and the drain electrode of the second N-type MOS tube is connected with a power supply.
Further, the sampling switch kick suppression circuit comprises a fifth N-type MOS tube, a sixth N-type MOS tube, a fourteenth P-type MOS tube, a fifteenth P-type MOS tube, a fifth resistor and a sixth resistor, wherein the grid electrode of the fifth N-type MOS tube is respectively connected with an input signal VIP, the cathode of a second capacitor and the sixth resistor, the drain electrode of the fifth N-type MOS tube is connected with the source electrode of the third N-type MOS tube and the source electrode of the fourteenth P-type MOS tube, the source electrode of the fifth N-type MOS tube is the positive output of an input buffer and is connected with a current source load circuit and a sampling circuit, the grid electrode of the fourteenth P-type MOS tube is connected with a fifth resistor R5, and the source electrode of the fourteenth P-type MOS tube is connected with the ground; the input signal VIN is connected with the cathode of the fourth capacitor C4, the grid electrode of the sixth N-type MOS tube and the fifth resistor, the drain electrode of the sixth N-type MOS tube is connected with the source electrode of the fourth N-type MOS tube and the source electrode of the fifteenth P-type MOS tube, the source electrode of the sixth N-type MOS tube is the cathode output of the input buffer and is connected with the current source load circuit and the sampling circuit, the grid electrode of the fifteenth P-type MOS tube is connected with the cathode of the sixth resistor, and the source electrode of the fifteenth P-type MOS tube is connected with the ground.
Further, the current source load circuit includes a seventh N-type MOS transistor, an eighth N-type MOS transistor, a ninth N-type MOS transistor, a tenth N-type MOS transistor, an eleventh N-type MOS transistor, a twelfth N-type MOS transistor, and a thirteenth N-type MOS transistor, wherein the gate of the eleventh N-type MOS transistor is connected to the drain of the eleventh N-type MOS transistor, the current source IB0, the gate of the twelfth N-type MOS transistor, the gate of the seventh N-type MOS transistor, the gate of the eighth N-type MOS transistor, the drain of the twelfth N-type MOS transistor is connected to the source of the eleventh N-type MOS transistor, the source of the twelfth N-type MOS transistor is connected to ground, the gate of the thirteenth N-type MOS transistor, the drain of the thirteenth N-type MOS transistor, the gate of the current source IB1, the gate of the ninth N-type MOS transistor, the gate of the tenth N-type MOS transistor are connected to ground, and the drain of the seventh N-type MOS transistor are positive outputs of the input buffer. The drain electrode of the tenth N-type MOS tube is connected with the source electrode of the eighth N-type MOS tube, and the drain electrode of the eighth N-type MOS tube is the negative output of the input buffer and is connected with the sampling switch kickback suppression circuit and the sampling circuit.
Further, the sampling circuit comprises a first switch, a second switch, a fifth capacitor and a sixth capacitor, wherein one pole of the first switch is connected with the positive electrode output of the input buffer, the other pole of the first switch is connected with the positive electrode of the fifth capacitor, the negative electrode of the fifth capacitor is connected with the common mode or the ground, one pole of the second switch is connected with the negative electrode of the input buffer, the other pole of the second switch is connected with the positive electrode of the sixth capacitor, and the negative electrode of the sixth capacitor is connected with the common mode or the ground.
Furthermore, the currents IB0 and IB1 in the input buffer can be adjusted according to the frequency of the input signal, and the fixed voltages VREF2 and VREF3 can also be adjusted according to the input frequency, so that the linearity of the input buffer can be optimized at different input frequencies.
The beneficial effects of the invention are as follows:
On the one hand, the input level conversion is realized through the resistor-capacitor network in the first circuit, so that the drain end of the input transistor can track the input signal, the drain-source voltage is kept unchanged, the channel length modulation effect is restrained, and the linearity of the input buffer is improved.
On the other hand, when the sampling switch is turned on, due to the resistances R5 and R6 and the auxiliary PMOS source follower in the second circuit, the positive output VoutP and the negative output VoutN drop simultaneously, and at this time, kickback is converted into a common mode error, so that the linearity of the input buffer can be improved under the situation that the output range is not affected.
In summary, the input buffer circuit for suppressing the kickback of the sampling switch and improving the linearity of the input buffer circuit not only suppresses the channel length modulation effect of the input transistor through the auxiliary level conversion circuit, but also converts the kickback noise of the sampling switch into a common mode error, improves the linearity of the input buffer, and is very suitable for a high-speed high-precision analog-to-digital converter.
Drawings
Fig. 1 is a circuit schematic of the present invention.
Detailed Description
The invention is further described with reference to the drawings and reference numerals.
In order that the above-recited objects, features and advantages of the present application will be more clearly understood, a more particular description of the application will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It should be noted that, without conflict, the embodiments of the present application and features in the embodiments may be combined with each other.
The terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
Example 1:
As shown in fig. 1, an input buffer circuit capable of suppressing kickback of a sampling switch and improving linearity includes a first circuit, a second circuit, a third circuit, and a fourth circuit.
The level shift circuit is used as a level shift circuit for inputting the voltage of the drain terminal of the input tube in the buffer;
The sampling switch kick-back suppression circuit is used as an input circuit of the input buffer and a kick-back cross-coupling circuit;
the current source load circuit is used for inputting a current source load of the buffer and a current source bias generating circuit;
the sampling circuit is a sampling network of input buffers.
Example 2:
Based on embodiment 1, the first circuit is a level conversion circuit, the level conversion circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first N-type MOS tube M1, a second N-type MOS tube M2, a third N-type MOS tube M3, and a fourth N-type MOS tube M4, the positive electrode of the first resistor R1 is connected with a fixed reference VREF3, and the negative electrode of the first resistor R1 is connected with the gate electrode of the first N-type MOS tube M1 and the positive electrode of the first capacitor C1; one pole of the second resistor R2 is connected with the fixed reference VREF2, the other pole of the second resistor R2 is respectively connected with the grid electrode of the third N-type MOS tube M3, the positive pole of the second capacitor C2 and the negative pole of the first capacitor C1, the drain electrode of the third N-type MOS tube M3 is connected with the source electrode of the first N-type MOS tube M1, the drain electrode of the first N-type MOS tube M1 is connected with a power supply, one pole of the third resistor R3 is connected with the fixed reference VREF3, and the other pole of the third resistor R3 is connected with the grid electrode of the second N-type MOS tube M2 and the positive pole of the third capacitor C3; one pole of the fourth resistor R4 is connected with the fixed reference VREF2, the other pole of the fourth resistor R4 is connected with the grid electrode of the fourth N-type MOS tube M4, the positive pole of the fourth capacitor C4 and the negative pole of the third capacitor C3, the drain electrode of the fourth N-type MOS tube M4 is connected with the source electrode of the second N-type MOS tube M2, and the drain electrode of the second N-type MOS tube M2 is connected with a power supply;
the second circuit is a sampling switch kick suppression circuit, the sampling switch kick suppression circuit comprises a fifth N-type MOS tube M5, a sixth N-type MOS tube M6, a fourteenth P-type MOS tube M14, a fifteenth P-type MOS tube M15, a fifth resistor R5 and a sixth resistor R6, the grid electrode of the fifth N-type MOS tube M5 is respectively connected with an input signal VIP, the cathode of a second capacitor C2 and the sixth resistor R6, the drain electrode of the fifth N-type MOS tube M5 is connected with the source electrode of a third N-type MOS tube M3 and the source electrode of a fourteenth P-type MOS tube M14, the source electrode of the fifth N-type MOS tube M5 is the positive output of an input buffer, the fifth N-type MOS tube M14 is connected with a current source load circuit and the sampling circuit, the grid electrode of the fourteenth P-type MOS tube M14 is connected with the fifth resistor R5R5, and the source electrode of the fourteenth P-type MOS tube M14 is connected with the ground; the input signal VIN is connected with the cathode of the fourth capacitor C4C4, the grid electrode of the sixth N-type MOS tube M6 and the fifth resistor R5, the drain electrode of the sixth N-type MOS tube M6 is connected with the source electrode of the fourth N-type MOS tube M4 and the source electrode of the fifteenth P-type MOS tube M15, the source electrode of the sixth N-type MOS tube M6 is the cathode output of the input buffer, the input signal VIN is connected with the current source load circuit and the sampling circuit, the grid electrode of the fifteenth P-type MOS tube M15 is connected with the cathode of the sixth resistor R6, and the source electrode of the fifteenth P-type MOS tube M15 is connected with the ground;
The third circuit is a current source load circuit, the current source load circuit comprises a seventh N-type MOS transistor M7, an eighth N-type MOS transistor M8, a ninth N-type MOS transistor M9, a tenth N-type MOS transistor M10, an eleventh N-type MOS transistor M11, a twelfth N-type MOS transistor M12 and a thirteenth N-type MOS transistor M13, the gate of the eleventh N-type MOS transistor M11 is connected with the drain of the eleventh N-type MOS transistor M11, the current source IB0, the gate of the twelfth N-type MOS transistor M12, the gate of the seventh N-type MOS transistor M7, the gate of the eighth N-type MOS transistor M8, the drain of the twelfth N-type MOS transistor M12 is connected with the source of the eleventh N-type MOS transistor M11, the source of the twelfth N-type MOS transistor M12 is connected with the ground, the gate of the thirteenth N-type MOS transistor M13, the drain of the current source IB1, the gate of the ninth N-type MOS transistor M9, the gate of the tenth N-type MOS transistor M10 is connected with the drain of the seventh N-type MOS transistor M7, and the drain of the ninth N-type MOS transistor M9 is connected with the drain of the seventh N-type MOS transistor M7. The sampling switch kickback suppression circuit is connected with the sampling circuit, the source electrode of the tenth N-type MOS tube M10 is connected with the ground, the drain electrode of the tenth N-type MOS tube M10 is connected with the source electrode of the eighth N-type MOS tube M8, and the drain electrode of the eighth N-type MOS tube M8 is the negative output of the input buffer and is connected with the sampling switch kickback suppression circuit and the sampling circuit;
The fourth circuit is a sampling circuit, the sampling circuit comprises a first switch SW1, a second switch SW2, a fifth capacitor C5 and a sixth capacitor C6, one pole of the first switch SW1 is connected with the positive output of the input buffer, the other pole of the first switch SW1 is connected with the positive pole of the fifth capacitor C5, the negative pole of the fifth capacitor C5 is connected with a common mode or ground, one pole of the second switch SW2 is connected with the negative pole of the input buffer, the other pole of the second switch SW2 is connected with the positive pole of the sixth capacitor C6, and the negative pole of the sixth capacitor C6 is connected with the common mode or ground.
The currents IB0 and IB1 in the input buffer can be adjusted according to the frequency of the input signal, and the fixed voltages VREF2 and VREF3 can also be adjusted according to the input frequency and can be used for optimizing the linearity of the input buffer under different input frequencies;
the specific working principle is as follows:
the level conversion circuit is characterized in that positive (negative) input signals are coupled to the grid electrode of the third N-type MOS tube M3 and the grid electrode of the fourth N-type MOS tube M4 in an alternating current mode through a second capacitor C2 and a fourth capacitor C4, then direct current level VREF2 is transmitted to the grid electrode of the third N-type MOS tube M3 and the grid electrode of the fourth N-type MOS tube M4 through a second resistor R2 and a fourth resistor R4, so that the grid electrode of the third N-type MOS tube M3 and the grid electrode of the fourth N-type MOS tube M4 are consistent with alternating current components of the input signals, and only differences of direct current components exist; then, the grid electrode of the third N-type MOS tube M3 and the grid electrode of the fourth N-type MOS tube M4 are coupled to the grid electrode of the first N-type MOS tube M1 and the grid electrode of the second N-type MOS tube M2 in an alternating current mode through the first capacitor C1 and the third capacitor C3, then the direct current level VREF3 is transmitted to the grid electrode of the first N-type MOS tube M1 and the grid electrode of the second N-type MOS tube M2 through the first resistor R1 and the third resistor R3, so that the alternating current components of the grid electrode of the first N-type MOS tube M1 and the grid electrode of the second N-type MOS tube M2 are consistent with the alternating current component of the grid electrode of the third N-type MOS tube M3 and the grid electrode of the fourth N-type MOS tube M4, namely, the alternating current components of input signals are consistent, and only the difference of direct current components exists; then, the grid electrode of the first N-type MOS tube M1 and the grid electrode of the second N-type MOS tube M2 are used as source followers, so that the drain electrode of the third N-type MOS tube M3 is ensured, the drain voltage alternating current component of the fourth N-type MOS tube M4 follows an input signal, the third N-type MOS tube M3 and the fourth N-type MOS tube M4 are also used as source followers, the drain voltage alternating current component of the drain electrode of the fifth N-type MOS tube M5 and the drain voltage alternating current component of the sixth N-type MOS tube M6 are ensured to follow the input signal, and further the drain-source voltage of the fifth N-type MOS tube M5 and the sixth N-type MOS tube M6 is kept unchanged, and the channel length modulation effect is restrained, so that the linearity of the input buffer is improved.
When the sampling switch is in a sampling phase, that is, when the first switch SW1 is turned on, when the positive output VoutP level is reduced due to the connection of the load capacitor, the parasitic gate-source capacitance coupling of the fifth N-type MOS transistor M5 causes the positive input VIP to be reduced, so that the negative vip_t of the sixth resistor R6 is also reduced, the fifteenth P-type MOS transistor M15 is used as a source follower, and the drain voltage of the sixth N-type MOS transistor M6 of the input tube is reduced, thereby causing the negative output VoutN to be reduced; similarly, when the negative output VoutN decreases, the positive output VoutP also decreases; when the first switch SW1 and the second switch SW2 are turned on, voutP and VoutN will drop simultaneously due to the connection of the load, at this time, kickback caused by the conduction of the sampling switch will be converted into an output common mode error of the input buffer, and in the situation that the input buffer is differential input and differential output, the common mode error will not affect the circuit, so that the linearity of the input buffer can be improved.
The current source load circuit is a current source load of the input buffer, and when the current sources flow in from IB0 and IB1, the eleventh N-type MOS tube M11, the twelfth N-type MOS tube M12 and the thirteenth N-type MOS tube M13 can convert the current into corresponding voltage signals, namely VB0 and VB1; when the voltage signal is connected to the grid electrode of the seventh N-type MOS tube M7, the grid electrode of the eighth N-type MOS tube M8, the grid electrode of the ninth N-type MOS tube M9 and the grid electrode of the tenth N-type MOS tube M10, the voltage signal is converted into current, at this time, the eleventh N-type MOS tube M11, the twelfth N-type MOS tube M12 and the thirteenth N-type MOS tube M13 form a group of current mirrors, the seventh N-type MOS tube M7, the eighth N-type MOS tube M8, the ninth N-type MOS tube M9 and the tenth N-type MOS tube M10 form another group of current mirrors, the duplication of the input currents IB0 and IB1 is completed, and the current source load is provided for the input buffer.
The sampling circuit is a sampling circuit of the input buffer, and when the first switch SW1 and the second switch SW2 are turned on, namely in a sampling phase, the positive output and the negative output of the input buffer are respectively transmitted to the sixth capacitor C6 and the fifth capacitor C5; while in the hold phase, the capacitor holds the sampled value for subsequent comparator comparison.
Based on the description, on one hand, the first circuit is utilized to realize level conversion to inhibit the channel length modulation effect, and on the other hand, the second circuit is utilized to convert the sampling switch back to a common mode error, and the differential characteristic of the input buffer is utilized to eliminate the influence of the common mode error on the performance of the input buffer, so that the linearity of the input buffer is improved.
The invention is not limited to the above-described alternative embodiments, and any person who may derive other various forms of products in the light of the present invention, however, any changes in shape or structure thereof, all falling within the technical solutions defined in the scope of the claims of the present invention, fall within the scope of protection of the present invention.
Claims (4)
1. An input buffer circuit capable of inhibiting a sampling switch from kicking back and improving linearity is characterized in that: the device comprises a level conversion circuit, a sampling switch kick suppression circuit, a current source load circuit and a sampling circuit;
the level shift circuit is used as a level shift circuit for inputting the voltage of the drain terminal of the input tube in the buffer;
The sampling switch kick-back suppression circuit is used as an input circuit of the input buffer and a kick-back cross-coupling circuit;
the current source load circuit is used for inputting a current source load of the buffer and a current source bias generating circuit;
the sampling circuit is a sampling network of an input buffer;
The level conversion circuit comprises a first resistor (R1), a second resistor (R2), a third resistor (R3), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a first N-type MOS tube (M1), a second N-type MOS tube (M2), a third N-type MOS tube (M3) and a fourth N-type MOS tube (M4), wherein the positive electrode of the first resistor (R1) is connected with a fixed reference VREF3, and the negative electrode of the first resistor (R1) is connected with the grid electrode of the first N-type MOS tube (M1) and the positive electrode of the first capacitor (C1); one electrode of the second resistor (R2) is connected with the fixed reference VREF2, the other electrode of the second resistor (R2) is respectively connected with the grid electrode of the third N-type MOS tube (M3), the anode of the second capacitor (C2) and the cathode of the first capacitor (C1), the drain electrode of the third N-type MOS tube (M3) is connected with the source electrode of the first N-type MOS tube (M1), the drain electrode of the first N-type MOS tube (M1) is connected with a power supply, one electrode of the third resistor (R3) is connected with the fixed reference VREF3, and the other electrode of the third resistor (R3) is connected with the grid electrode of the second N-type MOS tube (M2) and the anode of the third capacitor (C3); one pole of the third resistor (R3) is connected with the fixed reference VREF2, the other pole of the third resistor (R3) is connected with the grid electrode of the fourth N-type MOS tube (M4), the anode of the fourth capacitor (C4) and the cathode of the third capacitor (C3), the drain electrode of the fourth N-type MOS tube (M4) is connected with the source electrode of the second N-type MOS tube (M2), and the drain electrode of the second N-type MOS tube (M2) is connected with a power supply.
2. The input buffer circuit capable of suppressing kickback of a sampling switch and improving linearity as claimed in claim 1, wherein: the sampling switch kick suppression circuit comprises a fifth N-type MOS tube (M5), a sixth N-type MOS tube (M6), a fourteenth P-type MOS tube (M14), a fifteenth P-type MOS tube (M15), a fifth resistor (R5) and a sixth resistor (R6), wherein the grid electrode of the fifth N-type MOS tube (M5) is respectively connected with an input signal VIP, the cathode of a second capacitor (C2) and the sixth resistor (R6), the drain electrode of the fifth N-type MOS tube (M5) is connected with the source electrode of a third N-type MOS tube (M3) and the source electrode of a fourteenth P-type MOS tube (M14), the source electrode of the fifth N-type MOS tube (M5) is the positive output of an input buffer, the fifth N-type MOS tube is connected with a current source load circuit and the sampling circuit, the grid electrode of the fourteenth P-type MOS tube (M14) is connected with the fifth resistor (R5) R5, and the source electrode of the fourteenth P-type MOS tube (M14) is connected with ground; the input signal VIN is connected with the cathode of a fourth capacitor (C4) C4, the grid electrode of a sixth N-type MOS tube (M6) and a fifth resistor (R5), the drain electrode of the sixth N-type MOS tube (M6) is connected with the source electrode of the fourth N-type MOS tube (M4) and the source electrode of a fifteenth P-type MOS tube (M15), the source electrode of the sixth N-type MOS tube (M6) is the cathode output of an input buffer and is connected with a current source load circuit and a sampling circuit, the grid electrode of the fifteenth P-type MOS tube (M15) is connected with the cathode of the sixth resistor (R6), and the source electrode of the fifteenth P-type MOS tube (M15) is connected with the ground.
3. The input buffer circuit capable of suppressing kickback of a sampling switch and improving linearity as claimed in claim 2, wherein: the current source load circuit comprises a seventh N-type MOS tube (M7), an eighth N-type MOS tube (M8), a ninth N-type MOS tube (M9), a tenth N-type MOS tube (M10), an eleventh N-type MOS tube (M11), a twelfth N-type MOS tube (M12) and a tenth N-type MOS tube (M13), wherein the grid electrode of the eleventh N-type MOS tube (M11) is respectively connected with the drain electrode of the eleventh N-type MOS tube (M11), the current source IB0, the grid electrode of the twelfth N-type MOS tube (M12), the grid electrode of the seventh N-type MOS tube (M7), the grid electrode of the eighth N-type MOS tube (M8) is connected, the drain electrode of the twelfth N-type MOS tube (M12) is connected with the source electrode of the eleventh N-type MOS tube (M11), the grid electrode of the tenth N-type MOS tube (M13) is connected with the ground, the drain electrode of the tenth N-type MOS tube (M13) is connected with the drain electrode of the ninth N-type MOS tube (M1), the tenth N-type MOS tube (M9) is connected with the drain electrode of the ninth N-type MOS tube (M7), the sampling circuit is connected with the drain electrode of the eighth N-type MOS tube (M10), the sampling circuit is connected with the eighth N-type MOS tube (M9) is connected with the drain electrode of the eighth N-type MOS tube (M9, the drain electrode of the eighth N-type MOS tube (M8) is the negative electrode output of the input buffer and is connected with the sampling switch kick-back suppression circuit and the sampling circuit.
4. An input buffer circuit capable of suppressing kickback of a sampling switch and improving linearity as recited in claim 3, wherein: the sampling circuit comprises a first switch (SW 1), a second switch (SW 2), a fifth capacitor (C5) and a sixth capacitor (C6), wherein one pole of the first switch (SW 1) is connected with the output of the positive pole of the input buffer, the other pole of the first switch (SW 1) is connected with the positive pole of the fifth capacitor (C5), the negative pole of the fifth capacitor (C5) is connected with a common mode or ground, one pole of the second switch (SW 2) is connected with the negative pole of the input buffer, the other pole of the second switch (SW 2) is connected with the positive pole of the sixth capacitor (C6), and the negative pole of the sixth capacitor (C6) is connected with the common mode or ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311293941.4A CN117294306B (en) | 2023-10-08 | 2023-10-08 | Input buffer circuit capable of inhibiting sampling switch from kicking back and improving linearity |
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| CN109683651A (en) * | 2019-03-05 | 2019-04-26 | 电子科技大学 | A kind of low differential voltage linear voltage stabilizer circuit of high PSRR |
| CN112260690B (en) * | 2020-10-16 | 2023-01-20 | 中国电子科技集团公司第二十四研究所 | High linearity input buffer and pipeline analog-to-digital converter without sampling and protection structure |
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