CN117370255A - Error reporting structure of multi-port PCIe bridging chip - Google Patents

Abstract

The invention discloses a multi-port PCIe bridging chip error reporting architecture, and belongs to the field of integrated circuits. The invention can buffer PCIe errors detected by the downstream ports of the PCIe virtual switches, generate error report requests and corresponding error information according to the buffer information, report the error information received by the downstream ports of the PCIe virtual switches to the RC through the upstream ports of the corresponding PCIe virtual switches, or route and forward the error information received by the downstream ports of the PCIe virtual switches to the upstream ports of the corresponding PCIe virtual switches, and report the error information to the RC through the upstream ports of the corresponding PCIe virtual switches, thereby being convenient for the RC to locate, analyze and correct the errors in time, avoiding the problem of downtime of the system caused by the errors, enhancing the robustness and reliability of the system and being applicable to realizing the error report function of the multi-port PCIe bridge chip.

Description

A multi-port PCIe bridge chip error reporting architecture

Technical field

The invention relates to the technical field of integrated circuits, and in particular to a multi-port PCIe bridge chip error reporting architecture.

Background technique

PCI-Express is a high-speed serial computer expansion bus standard. It is widely used in computers because of its high data transfer rate, high bandwidth, high data transmission reliability and data integrity, high compatibility and support for parallel data channels. Hardware devices such as graphics cards, network adapters, and storage. PCIe Switch (switch) is one of the most common device types in PCIe. It can divide a PCIe bus into multiple sub-buses. It has 1 upstream port and more than or equal to 2 downstream ports. It can transmit data from an endpoint device to Another endpoint device that controls both the direction and speed of data flow. The PCIe Switch chip can expand the number of PCIe lanes in the system when the number of PCIe lanes provided by the CPU is insufficient, improving expansion capabilities and flexibility.

Some errors will occur during the PCIe transmission process. These errors can be roughly divided into correctable errors and uncorrectable errors. Uncorrectable errors are further divided into fatal errors and non-fatal errors. Among them, correctable errors can be automatically recognized by the hardware and automatically corrected or restored. Nonfatal errors may cause a specific transmission to become unreliable, but other functions of the link and hardware are not affected. Fatal errors will cause link and hardware abnormalities, and recovery can only be achieved through a system reset. If these errors are not resolved in time, a large number of error reports will cause system downtime and have a great impact on PCIe transmission.

The multi-port PCIe bridge chip includes multiple PCIe Switch controllers, and the multi-port PCIe bridge chip also has a Virtual Switch mode. This mode has multiple PCIe Switch upstream ports and communication between the upstream and downstream ports. There are more changes, and the situations that cause PCIe errors will be more complicated. Therefore, in order to solve the problem of centralized reporting of PCIe errors received or detected by each port in the multi-port PCIe bridge chip, a special error reporting design needs to be provided to implement the error reporting function of the entire PCIe bridge chip.

Contents of the invention

The purpose of the present invention is to provide a multi-port PCIe bridge chip error reporting architecture to solve the problem that the existing technology cannot report the PCIE Error received or detected by multiple downstream ports of the PCIE Switch to the RC (RootComplex, corresponding root complex) The problem.

In order to solve the above technical problems, the present invention provides a multi-port PCIe bridge chip error reporting architecture, including an error reporting interface module, an error reporting bus module and an error reporting module, wherein:

The error reporting interface module is connected to the upstream and downstream ports of the PCIe virtual switch in the multi-port PCIe bridge chip, and the error reporting interface module performs cross-clock and cache processing on signals received from the downstream ports of multiple PCIe switches;

The error reporting bus module is connected to the error reporting interface module, and the error reporting module is connected to the error reporting bus module.

In one implementation, the error reporting interface module is connected to downstream ports of multiple PCIe switches, and supports error reporting of multiple PCIe virtual switches in virtual switch mode.

In one implementation, the error reporting interface module caches the error information received by the downstream port of the PCIe virtual switch connected to it, the detected PCIe errors of different levels, and the port information to the error reporting interface module. In the Ingress FIFO, the error reporting request and error information will be sent from the Egress FIFO of the error reporting interface module to the upstream port of the corresponding PCIe virtual switch;

The error reporting interface module simultaneously performs cross-clock processing, so that the signals in the clock domain of the downstream port of the PCIe virtual switch are synchronized to the clock domain of the corresponding upstream port after processing.

In one implementation, the error reporting bus module outputs different levels of error information and error detection prompt signals of the PCIe virtual switch downstream ports stored in the Ingress FIFO to the error reporting module for processing, and at the same time The error information output by the error reporting module is stored in the Egress FIFO to achieve the purpose of managing the port data path interconnection of the PCIe virtual switch.

In one implementation, the error reporting module converts and routes the error information and PCIe error signals stored in the Ingress FIFO to generate corresponding error information and error reporting requests, and then arbitrates and responds to the error reporting requests. After pressure processing, it is sent to the error reporting bus module.

In one implementation, the PCIe error detected on the downstream port of the PCIe virtual switch generates corresponding error information and error reporting request according to the port configuration information and PCIe error type, and sends the request to the error reporting bus module, or sends the request to the error reporting bus module. The error information received by the downstream port is directly routed to the error reporting bus module.

In one implementation, multiple error reporting requests are arbitrated based on the not-full signal of the Egress FIFO, and at the same time, back pressure is performed based on the feedback signal from the upstream port of the PCIe virtual switch, and subsequent errors are cached before receiving the feedback signal from the upstream port. Error reporting request, after receiving the feedback signal from the upstream port, read and send subsequent error reporting requests.

The invention provides a multi-port PCIe bridge chip error reporting architecture that can cache PCIe errors detected by the downstream ports of multiple PCIe virtual switches, generate error reporting requests and corresponding error information based on the cached information, and pass the corresponding PCIe virtual switch The upstream port of the corresponding PCIe virtual switch is reported to the RC, or the error information received by the downstream ports of multiple PCIe virtual switches is routed and forwarded to the upstream port of the corresponding PCIe virtual switch, and then reported to the RC through the upstream port of the corresponding PCIe virtual switch, which facilitates the timely positioning of the RC. Analyze and correct errors to avoid system downtime caused by errors, enhance the robustness and reliability of the system, and can be used to implement the error reporting function of multi-port PCIe bridge chips.

Description of the drawings

Figure 1 is a schematic diagram of the overall framework of the multi-port PCIE bridge chip error reporting architecture provided by the present invention;

Figure 2 is a schematic diagram of the design architecture of the error reporting module provided by the present invention;

Figure 3 is a schematic diagram of the multi-port PCIE bridge chip error reporting process provided by the present invention.

Detailed ways

The multi-port PCIe bridge chip error reporting architecture proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present invention.

Figure 1 is a schematic diagram of the overall framework of the error reporting architecture of the multi-port PCIE bridge chip provided by the present invention. It mainly includes an error reporting interface module, an error reporting bus module and an error reporting module. The error reporting interface module is connected to the multi-port PCIe bridge chip. The error reporting interface module performs cross-clock and cache processing on the signals received from multiple PCIE Virtual Switch downstream ports. The purpose of cross-clock processing is to prevent the PCIE Virtual Switch from being blocked. The clock frequencies of the downstream ports are different, so the signal received from the downstream port needs to be synchronized from the downstream port clock domain to the clock domain of the upstream port that needs to be reported, so that the ErrorMessage (error message) can be reported to the RC through the upstream port. The logic of cache processing is to generate the write enable signal and input signal of the Ingress FIFO based on the port information, the different levels of Error Messages received by the PCIE downstream port, the different levels of detected PCIE errors and the non-empty signal of the asynchronous FIFO, and then based on The non-empty signal of the asynchronous FIFO generates the read enable signal of the Engress FIFO, and sends the ErrorMessage in the Engress FIFO to the upstream port.

The Ingress FIFO read control logic in the error reporting bus module generates the Ingress FIFO read enable signal based on the non-empty signal of the asynchronous FIFO, and sends the buffered signal in the Ingress FIFO to the error reporting module for processing. The Engress FIFO write control logic generates the write enable signal of the Engress FIFO based on the arbitration result in the error reporting module, and writes the signal processed by the error reporting module into the Engress FIFO.

The error reporting module mainly converts and arbitrates the PCIE error information read from the Ingress FIFO and then writes it into the Ingress FIFO.

Figure 2 is the design architecture diagram of the error reporting module in the multi-port PCIE bridge chip. The error reporting module generates corresponding ErrorMessage and error reporting requests for errors detected by the PCIE Virtual Switch downstream port according to the port configuration signal and PCIE error type, or reports the error to the downstream port. The Error Message received by the port generates an error reporting request. At the same time, the error reporting module arbitrates multiple error reporting requests, and determines the source and destination of the Error Message in Virtual Switch mode based on the upstream and downstream port configuration signals, and then passes the corresponding VS( The error reporting sub-module of Virtual Switch sends it to the error reporting bus module. At the same time, back pressure is performed based on the feedback signal of the PCIE Virtual Switch upstream port, and subsequent Error Message requests are cached before receiving the feedback signal from the upstream port. After receiving the feedback signal from the upstream port, subsequent Error Message requests are read and sent.

Figure 3 is a schematic diagram of the error reporting process of the multi-port PCIE bridge chip of the present invention, which mainly includes the processing and reporting process of PCIE errors detected or received by PCIE upstream and downstream ports.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes or modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the scope of the claims.

Claims (7)

1. A multi-port PCIe bridge chip error reporting architecture, characterized by including an error reporting interface module, an error reporting bus module and an error reporting module, wherein: The error reporting interface module is connected to the upstream and downstream ports of the PCIe virtual switch in the multi-port PCIe bridge chip, and the error reporting interface module performs cross-clock and cache processing on signals received from the downstream ports of multiple PCIe switches; The error reporting bus module is connected to the error reporting interface module, and the error reporting module is connected to the error reporting bus module. 2. The multi-port PCIe bridge chip error reporting architecture as claimed in claim 1, wherein the error reporting interface module is connected to the downstream ports of multiple PCIe switches and supports errors of multiple PCIe virtual switches in virtual switch mode. Report. 3. The multi-port PCIe bridge chip error reporting architecture as claimed in claim 1, wherein the error reporting interface module reports error information received by the downstream port of the PCIe virtual switch connected to it, and different levels of detected errors. The PCIe errors and port information are cached in the Ingress FIFO of the error reporting interface module, and at the same time, the error reporting request and error information are sent from the Egress FIFO of the error reporting interface module to the upstream port of the corresponding PCIe virtual switch; The error reporting interface module simultaneously performs cross-clock processing, so that the signals in the clock domain of the downstream port of the PCIe virtual switch are synchronized to the clock domain of the corresponding upstream port after processing. 4. The multi-port PCIe bridge chip error reporting architecture according to claim 3, wherein the error reporting bus module stores different levels of error information and error detection of the PCIe virtual switch downstream ports stored in the Ingress FIFO. The prompt signal is output to the error reporting module for processing, and the error information output by the error reporting module is stored in the Egress FIFO to achieve the purpose of managing the port data path interconnection of the PCIe virtual switch. 5. The multi-port PCIe bridge chip error reporting architecture of claim 4, wherein the error reporting module converts and routes the error information and PCIe error signals stored in the Ingress FIFO to generate corresponding errors. Information and error reporting requests are then sent to the error reporting bus module after arbitration and back-pressure processing are performed on the error reporting requests. 6. The multi-port PCIe bridge chip error reporting architecture according to claim 5, characterized in that the PCIe errors detected by the downstream ports of the PCIe virtual switch generate corresponding error information and error reporting requests according to the port configuration information and PCIe error types. , and send the request to the error reporting bus module, or directly route the error information received by the downstream port to the error reporting bus module. 7. The multi-port PCIe bridge chip error reporting architecture of claim 6, wherein multiple error reporting requests are arbitrated according to the non-full signal of the Egress FIFO, and at the same time, based on the feedback signal of the PCIe virtual switch upstream port Perform back pressure, cache subsequent error reporting requests before receiving the feedback signal from the upstream port, and read and send subsequent error reporting requests after receiving the feedback signal from the upstream port.