CN117391032B - Circuit topology diagram generation method, device, equipment and storage medium - Google Patents
Circuit topology diagram generation method, device, equipment and storage medium Download PDFInfo
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Abstract
The application provides a circuit topology diagram generation method, a device, equipment and a storage medium, and relates to the technical field of circuit design. The method comprises the following steps: according to the preset circuit function, an initial circuit topological graph and an initial adjacent matrix of the initial circuit topological graph are obtained, a preset countercurrent model is adopted, the initial adjacent matrix is mapped into an initial continuous vector, the initial continuous vector is updated according to the target circuit performance of the preset circuit function, a target continuous vector is obtained, the target continuous vector is restored into a target adjacent matrix by adopting the countercurrent model, and the circuit topological graph corresponding to the target adjacent matrix is determined to be a target circuit topological graph of the preset circuit function. Mapping the initial adjacent matrix into an initial continuous vector through a countercurrent model, updating the initial continuous vector to obtain a target continuous vector, and restoring the target continuous vector to obtain a target adjacent matrix, so that the circuit performance of the target circuit topological graph meets the target circuit performance of a preset circuit function.
Description
Technical Field
The present invention relates to the field of circuit design technologies, and in particular, to a method, an apparatus, a device, and a storage medium for generating a circuit topology map.
Background
In the overall design flow of an analog integrated circuit, a circuit level design is located at the front end of the overall design flow. The engineer needs to select the types of components needed by the circuit construction according to the circuit design target, designs the circuit topology structure, namely designs how to connect all components, finally determines the value of each component parameter, and uses the circuit simulation software to check whether the circuit performance reaches the target. At present, a mature commercial tool automatically calculates the optimal component parameter value under a given circuit topology structure, but the upper limit of the circuit performance is still limited by the circuit topology structure, and in many cases, the design target cannot be achieved by adjusting the component parameter anyway. At the topology level, engineers can only manually change the topology of the circuit, and try repeatedly until the performance reaches the expected level. The design process of the circuit topology is highly dependent on the experience of engineers, cannot be separated from manual operation, and has a great automation and intelligent space.
At present, the existing method mainly adopts a genetic algorithm to search the circuit topology, but the searching method relies on random crossing gene sequences to generate new circuit topology, lacks directionality, has low algorithm efficiency and slow convergence speed, and each batch of new 'offspring' individuals are generated to simulate the new circuit topology one by one, so that a great amount of time is consumed.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a circuit topology graph generation method, a device, equipment and a storage medium, wherein an initial adjacent matrix is mapped into an initial continuous vector through a countercurrent model, the initial continuous vector is updated to obtain a target continuous vector, then the target continuous vector is reversely mapped to obtain a target adjacent matrix, and a circuit topology graph corresponding to the target adjacent matrix is determined.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the application is as follows:
in a first aspect, an embodiment of the present application provides a circuit topology map generating method, including:
according to a preset circuit function, an initial circuit topological graph and an initial adjacency matrix of the initial circuit topological graph are obtained, wherein the initial circuit topological graph is as follows: a plurality of topology nodes and a connection between topology nodes, the initial adjacency matrix comprising: indication information of circuit devices between every two topology nodes in the plurality of topology nodes;
Mapping the initial adjacent matrix into an initial continuous vector by adopting a preset countercurrent model;
updating the initial continuous vector according to the target circuit performance of the preset circuit function to obtain a target continuous vector;
Reducing the target continuous vector into a target adjacent matrix by adopting the countercurrent model;
and determining the circuit topology diagram corresponding to the target adjacent matrix as the target circuit topology diagram of the preset circuit function.
In an optional implementation manner, the updating the initial continuous vector according to the target circuit performance of the preset circuit function to obtain a target continuous vector includes:
according to the initial continuous vector, performing performance prediction by adopting a preset performance prediction model corresponding to the target circuit performance to obtain initial circuit performance parameters of the initial circuit topological graph;
updating the initial continuous vector according to the initial circuit performance parameter;
and carrying out performance prediction again by adopting the preset performance prediction model according to the updated continuous vector until a preset iteration stop condition is reached, and determining the continuous vector when the preset iteration stop condition is reached as the target continuous vector.
In an alternative embodiment, the counter-flow model comprises: the device comprises a normalization unit, a countercurrent unit and a connecting unit; the mapping the initial adjacency matrix into an initial continuous vector by adopting a preset countercurrent model comprises the following steps:
Normalizing parameters in the initial adjacency matrix to a preset parameter range by adopting the normalization unit to obtain a normalized adjacency matrix;
performing first processing on a first unit vector in the normalized adjacent matrix by adopting the countercurrent unit to obtain an initial processed adjacent matrix;
adopting the countercurrent unit to continuously process the second unit vector in the initial processed adjacent matrix until the number of the processed unit vectors meets a preset number threshold;
and generating the initial continuous vector according to the processed adjacent matrix when the number of the processed unit vectors meets the preset number threshold by adopting the connecting unit.
In an alternative embodiment, the counter flow unit comprises: a mask layer, a classification model and a coupling layer;
The first processing is performed on the first unit vector in the normalized adjacency matrix by adopting the countercurrent unit to obtain an initial processed adjacency matrix, and the method comprises the following steps:
Masking other vectors except the first unit vector in the normalized adjacent matrix by adopting the masking layer to obtain a first masking matrix, and masking the first unit vector in the normalized adjacent matrix to obtain a second masking matrix;
Classifying the second mask matrix by adopting the classification model to obtain a first classification matrix and a second classification matrix;
and adopting the coupling layer to couple the first mask matrix, the first classification matrix and the second classification matrix to generate the initial processed adjacency matrix.
In an alternative embodiment, the preset iteration stop condition is: and reaching the preset iteration times, or enabling the circuit performance after performance prediction is performed again by the preset performance prediction model to meet the target circuit performance.
In an optional embodiment, before performing performance prediction by using a preset performance prediction model corresponding to the target circuit performance according to the initial continuous vector to obtain an initial circuit performance parameter of the initial circuit topology, the method further includes:
acquiring a plurality of circuit topological graphs and adjacent matrixes of the circuit topological graphs according to the preset circuit function;
Performing device parameter tuning on the plurality of circuit topological graphs to obtain circuit performance parameters of the plurality of circuit topological graphs;
Generating a training data set according to the adjacency matrix of the plurality of circuit topological graphs and the circuit performance parameters of the plurality of circuit topological graphs;
and training an initial countercurrent model and an initial performance prediction model by adopting the training data set to obtain the countercurrent model and the performance prediction model.
In an optional embodiment, the obtaining an initial circuit topology map and an initial adjacency matrix of the initial circuit topology map according to a preset circuit function includes:
According to the preset circuit function, randomly generating the initial circuit topological graph, and acquiring an initial adjacency matrix of the initial circuit topological graph;
Or according to the preset circuit function, acquiring the initial circuit topology diagram from the existing circuit topology set corresponding to the preset circuit function, and acquiring an initial adjacency matrix of the initial circuit topology diagram.
In a second aspect, an embodiment of the present application further provides a circuit topology map generating apparatus, where the apparatus includes:
The acquisition module is used for acquiring an initial circuit topological graph and an initial adjacency matrix of the initial circuit topological graph according to a preset circuit function, wherein the initial circuit topological graph is as follows: a plurality of topology nodes and a connection between topology nodes, the initial adjacency matrix comprising: indication information of circuit devices between every two topology nodes in the plurality of topology nodes;
the mapping module is used for mapping the initial adjacent matrix into an initial continuous vector by adopting a preset countercurrent model;
The updating module is used for updating the initial continuous vector according to the target circuit performance of the preset circuit function to obtain a target continuous vector;
The reduction module is used for reducing the target continuous vector into a target adjacent matrix by adopting the countercurrent model;
And the determining module is used for determining the circuit topology diagram corresponding to the target adjacent matrix as the target circuit topology diagram of the preset circuit function.
In a third aspect, an embodiment of the present application further provides a computer apparatus, including: a processor, a storage medium and a bus, the storage medium storing program instructions executable by the processor, the processor and the storage medium communicating over the bus when the computer device is running, the processor executing the program instructions to perform the steps of the circuit topology method of any of the first aspects.
In a fourth aspect, embodiments of the present application also provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the circuit topology map method of any of the first aspects.
The beneficial effects of the application are as follows:
The embodiment of the application provides a circuit topology diagram generation method, a device, equipment and a storage medium, wherein the method comprises the following steps: according to a preset circuit function, an initial circuit topological graph and an initial adjacent matrix of the initial circuit topological graph are obtained, then a preset countercurrent model is adopted, the initial adjacent matrix is mapped into an initial continuous vector, the initial continuous vector is updated according to the target circuit performance of the preset circuit function, a target continuous vector is obtained, finally the target continuous vector is restored into a target adjacent matrix by adopting the countercurrent model, and the circuit topological graph corresponding to the target adjacent matrix is determined to be a target circuit topological graph of the preset circuit function. According to the method, the initial adjacent matrix is mapped into the initial continuous vector through the countercurrent model, so that the initial continuous vector is convenient to update subsequently to obtain the target continuous vector, and then the countercurrent model is adopted to reversely map the target continuous vector to obtain the target adjacent matrix, so that lossless inverse operation of the target continuous vector can be realized, the circuit performance of the target circuit topology graph can meet the target circuit performance of a preset circuit function, and the efficiency of generating the target circuit topology graph is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a circuit topology diagram generating method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an initial circuit topology provided in an embodiment of the present application;
FIG. 3 is a schematic diagram of an initial adjacency matrix according to an embodiment of the present application;
FIG. 4 is a second schematic flow chart of a circuit topology generating method according to an embodiment of the present application;
FIG. 5 is a third schematic flow chart of a circuit topology generating method according to an embodiment of the present application;
FIG. 6 is a flowchart of a circuit topology generating method according to an embodiment of the present application;
FIG. 7 is a schematic structural diagram of a reversible flow model according to an embodiment of the present application;
FIG. 8 is a flowchart of a circuit topology generating method according to an embodiment of the present application;
fig. 9 is a schematic functional block diagram of a circuit topology generating device according to an embodiment of the present application;
fig. 10 is a schematic diagram of a computer device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that, if the terms "upper", "lower", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or an azimuth or the positional relationship conventionally put in use of the product of the application, it is merely for convenience of describing the present application and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application.
Furthermore, the terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
In order to accurately determine a target circuit topology diagram of a preset circuit function, the embodiment of the application provides a circuit topology diagram generation method, which comprises the steps of firstly acquiring an initial circuit topology diagram and an initial adjacent matrix of the initial circuit topology diagram according to the preset circuit function, then mapping the initial adjacent matrix into an initial continuous vector by adopting a preset countercurrent model, updating the initial continuous vector according to the target circuit performance of the preset circuit function to obtain a target continuous vector, and then restoring the target continuous vector into the target adjacent matrix by adopting the countercurrent model, so as to determine the circuit topology diagram corresponding to the target adjacent matrix as the target circuit topology diagram of the preset circuit function. Updating the initial continuous vector through a preset countercurrent model to ensure that the circuit performance of the circuit topology diagram corresponding to the target continuous vector is optimal, thereby accurately determining the target circuit topology diagram with the preset circuit function.
The circuit topology map generating method provided by the embodiment of the application is explained in detail by specific examples with reference to the accompanying drawings. The circuit topology diagram generating method provided by the embodiment of the application can be realized by the following steps: the method comprises the steps of presetting a circuit topology diagram generation algorithm or detecting software, and realizing by running the algorithm or the software. The computer device may be, for example, a server or a terminal, which may be a user computer. Fig. 1 is a schematic flow chart of a circuit topology diagram generating method according to an embodiment of the present application; FIG. 2 is a schematic diagram of an initial circuit topology provided in an embodiment of the present application;
fig. 3 is a schematic diagram of an initial adjacency matrix according to an embodiment of the present application. As shown in fig. 1, the method includes:
S101, acquiring an initial circuit topological graph and an initial adjacency matrix of the initial circuit topological graph according to a preset circuit function.
In this embodiment, the preset circuit functions may include: the circuit comprises an amplifying circuit, a signal operation and processing circuit, an oscillating circuit, a demodulation circuit and the like, wherein an initial circuit diagram corresponding to the preset circuit function is obtained according to the preset circuit function and circuit devices required by the preset circuit function, and an initial circuit topology diagram corresponding to the initial circuit diagram and an initial adjacency matrix corresponding to the initial circuit topology diagram are determined.
The initial circuit topology diagram is as follows: the initial adjacency matrix comprises a plurality of topological nodes and connecting lines among the topological nodes: indication information of circuit devices between every two topology nodes in the plurality of topology nodes. By way of example, as shown in fig. 2, determining the initial circuit diagram may include: the initial circuit diagram is abstracted by the initial circuit diagram, and only comprises a plurality of topological nodes and a set of branch connection lines among the topological nodes, wherein the initial circuit diagram can reflect the connection relation and the property of a circuit in the initial circuit diagram.
According to the initial circuit topology diagram and the indication information of each circuit device in the initial circuit diagram, an initial adjacent matrix of the initial circuit topology diagram is generated, as shown in fig. 3, wherein the indication information of the forward operational amplifier device in the initial circuit diagram is represented by an edge weight 1, the indication information of the reverse operational amplifier device in the initial circuit diagram is represented by an edge weight 2, the indication information of the capacitor is represented by an edge weight 3, and by way of example, the circuit device connected between the topology node V in and the topology node1 is a forward operational amplifier device, the topology node V in and the topology node1 are represented by an edge weight 1, and if two topology nodes exist in a plurality of topology nodes, no circuit device is connected, such as the topology node V in is connected with the topology node GND, the two topology nodes are represented by an edge weight 4, and the topology node itself is not connected with the topology node itself, and therefore the initial adjacent matrix shown in fig. 3 is obtained. It should be noted that the edge weight may be extended according to the kind of the circuit device in the initial circuit.
S102, mapping the initial adjacent matrix into an initial continuous vector by adopting a preset countercurrent model.
Specifically, as the values of the adjacent matrix are discrete, the adjacent matrix cannot be directly optimized, and therefore, the initial adjacent matrix is reversibly mapped into the initial continuous vector by adopting a preset reversible flow model, so that the initial continuous vector can be optimized subsequently.
S103, updating the initial continuous vector according to the target circuit performance of the preset circuit function to obtain a target continuous vector.
Specifically, when the initial circuit topology diagram is obtained, the target circuit performance parameters required by the preset circuit function are also required to be obtained according to the preset circuit function, wherein the target circuit performance parameters include: and if the circuit performance of the circuit topology diagram corresponding to the initial continuous vector does not meet the target circuit performance, updating the initial continuous vector to obtain a target continuous vector, wherein the circuit performance of the circuit topology diagram corresponding to the target continuous vector meets the target circuit performance.
S104, reducing the continuous vector of the target into a target adjacent matrix by adopting a countercurrent model.
S105, determining a circuit topology diagram corresponding to the target adjacent matrix as a target circuit topology diagram with a preset circuit function.
The method comprises the steps of adopting a countercurrent model to restore a target continuous vector to a target adjacent matrix, and determining a circuit topology diagram corresponding to the target adjacent matrix according to the target adjacent matrix, so as to determine a target circuit topology diagram of a preset circuit function.
In summary, the embodiment of the application provides a circuit topology graph generation method, which includes: according to a preset circuit function, an initial circuit topological graph and an initial adjacent matrix of the initial circuit topological graph are obtained, then a preset countercurrent model is adopted, the initial adjacent matrix is mapped into an initial continuous vector, the initial continuous vector is updated according to the target circuit performance of the preset circuit function, a target continuous vector is obtained, finally the target continuous vector is restored into a target adjacent matrix by adopting the countercurrent model, and the circuit topological graph corresponding to the target adjacent matrix is determined to be a target circuit topological graph of the preset circuit function. According to the method, the initial adjacent matrix is mapped into the initial continuous vector through the countercurrent model, so that the initial continuous vector is convenient to update subsequently to obtain the target continuous vector, and then the countercurrent model is adopted to reversely map the target continuous vector to obtain the target adjacent matrix, so that lossless inverse operation of the target continuous vector can be realized, the circuit performance of the target circuit topology graph can meet the target circuit performance of a preset circuit function, and the efficiency of generating the target circuit topology graph is improved.
The embodiment of the application also provides another possible implementation manner of the circuit topology graph generation method, and fig. 4 is a second schematic flow chart of the circuit topology graph generation method provided by the embodiment of the application. As shown in fig. 4, updating the initial continuous vector according to the target circuit performance of the preset circuit function to obtain a target continuous vector includes:
S201, according to the initial continuous vector, performing performance prediction by adopting a preset performance prediction model corresponding to the target circuit performance, and obtaining initial circuit performance parameters of an initial circuit topological graph.
In this embodiment, the preset performance prediction model may be a multi-layer perceptron (Multiple Layer Perceptron, MLP) model, which is used to predict the circuit performance of the initial circuit topology corresponding to the initial continuous vector, so as to obtain the initial circuit performance parameter of the initial circuit topology, where the initial circuit performance parameter of the initial circuit topology may include: gain-bandwidth product, load capacitance and power consumption, and determining the figure of merit of an initial circuit topology based on a plurality of initial circuit performance parametersThe expression of (2) is as follows:
Where GBW is expressed as a gain-bandwidth product, C L is expressed as a load capacitance, and Power is expressed as Power consumption, so that a figure of merit is determined based on a predicted plurality of initial circuit performance parameters, the larger the figure of merit, the better the circuit performance of the initial circuit topology.
S202, updating the initial continuous vector according to the initial circuit performance parameters.
Specifically, if the initial circuit performance parameter does not meet the target circuit performance parameter, that is, the circuit performance of the initial circuit topology does not meet the target circuit performance, the initial continuous vector is updated, and specifically, the initial continuous vector is updated through the countercurrent model.
S203, according to the updated continuous vector, adopting a preset performance prediction model to predict the performance again until a preset iteration stop condition is reached, and determining the continuous vector when the preset iteration stop condition is reached as a target continuous vector.
Optionally, the preset iteration stop condition is: and (3) reaching the preset iteration times, or enabling the circuit performance after performance prediction is performed again by the preset performance prediction model to meet the target circuit performance.
Specifically, according to the updated continuous vector, adopting a preset performance prediction model to carry out performance prediction again until the iteration number of the preset performance prediction model reaches the preset iteration number, or if the circuit performance parameter of the preset performance prediction model after carrying out performance prediction again is greater than or equal to the target circuit performance parameter, stopping updating the continuous vector, and determining the continuous vector when reaching the preset iteration stop condition as the target continuous vector.
It should be noted that, the preset performance prediction model predicts the circuit performance parameters of the circuit topology diagram corresponding to the target continuous vector, and determines the quality factors of the circuit topology diagram to be:
z*＝argmax MLP(z)
The quality factor of the circuit topological graph is the maximum value of a plurality of quality factors predicted by a preset performance prediction model.
According to the method provided by the embodiment of the application, according to the initial continuous vector, a preset performance prediction model corresponding to the target circuit performance is adopted to perform performance prediction, so that initial circuit performance parameters of an initial circuit topological graph are obtained, then according to the initial circuit performance parameters, the initial continuous vector is updated, according to the updated continuous vector, the performance prediction is performed again by adopting the preset performance prediction model until a preset iteration stop condition is reached, and the continuous vector when the preset iteration stop condition is reached is determined to be the target continuous vector. And the performance prediction is performed through a preset performance prediction model, so that the accuracy of the performance prediction is higher, and the prediction speed is faster.
The embodiment of the application also provides another possible implementation manner of the circuit topology graph generation method, and the countercurrent model comprises the following steps: the device comprises a normalization unit, a countercurrent unit and a connecting unit; fig. 5 is a third flowchart of a circuit topology generating method according to an embodiment of the present application. As shown in fig. 5, the initial adjacency matrix is mapped into initial continuous vectors by using a preset countercurrent model, and the method comprises:
S301, normalizing parameters in the initial adjacent matrix to a preset parameter range by adopting a normalization unit to obtain a normalized adjacent matrix.
In this embodiment, the initial adjacency matrix is a (0)∈{0,1,2,…,c}n×n, where c represents the circuit device type and n represents the number of circuit topology nodes. The normalization unit may employ an activation normalization (Activation Normalization, actNorm), and the normalization unit ActNorm normalizes the parameters in the initial adjacency matrix to [ -1,1], thereby improving the computational stability of the subsequent reversible flow model, and obtaining a normalized adjacency matrix.
S302, performing first processing on the first unit vector in the normalized adjacent matrix by adopting a countercurrent unit to obtain an initial processed adjacent matrix.
S303, adopting a countercurrent unit, and continuing to continuously process the second unit vector in the initial processed adjacent matrix until the number of the processed unit vectors meets a preset number threshold.
The first unit vector indicates a first row vector or a first column vector in the normalized adjacent matrix, if the first unit vector is the first row vector in the normalized adjacent matrix, the second unit vector is a second row vector in the normalized adjacent matrix, and if the first unit vector is the first column vector in the normalized adjacent matrix, the second unit vector is the second column vector in the normalized adjacent matrix, so that each row vector or each column vector in the normalized adjacent matrix is sequentially processed by adopting a countercurrent unit.
Specifically, the countercurrent unit performs first processing on a first unit vector in the normalized adjacent matrix to obtain an initial processed adjacent matrix A (1), and then performs second processing on a second unit vector in the initial processed adjacent matrix to obtain a second processed adjacent matrix, until each unit vector in the normalized adjacent matrix is processed, or the number of processed unit vectors meets a preset number threshold, and then stops processing the unit vectors.
S304, generating initial continuous vectors by adopting a connection unit according to the processed adjacent matrixes when the number of the processed unit vectors meets a preset number threshold.
The processed adjacency matrix a (n) is connected row by row using a connection unit, thereby generating an initial continuous vector.
In the method provided by the embodiment of the application, a normalization unit is adopted to normalize parameters in an initial adjacent matrix to a preset parameter range to obtain the normalized adjacent matrix, then a countercurrent unit is adopted to perform first processing on a first unit vector in the normalized adjacent matrix to obtain an initial processed adjacent matrix, a countercurrent unit is adopted to continuously process a second unit vector in the initial processed adjacent matrix until the number of processed unit vectors meets a preset number threshold, and finally a connection unit is adopted to generate an initial continuous vector according to the processed adjacent matrix when the number of processed unit vectors meets the preset number threshold, so that the initial continuous vector is mapped to the initial continuous vector.
The embodiment of the application also provides another possible implementation manner of the circuit topology diagram generating method, and the countercurrent unit comprises: a mask layer, a classification model and a coupling layer; fig. 6 is a flowchart of a circuit topology generating method according to an embodiment of the present application. As shown in fig. 6, the first unit vector in the normalized adjacency matrix is subjected to a first process by using a countercurrent unit to obtain an initial processed adjacency matrix, and the method includes:
S401, masking other vectors except the first unit vector in the normalized adjacent matrix by using a masking layer to obtain a first masking matrix, and masking the first unit vector in the normalized adjacent matrix to obtain a second masking matrix.
In this embodiment, the normalized adjacent matrix is classified by a mask layer to obtain a first mask matrix a 1 (0) and a second mask matrix a 2 (0), where the first mask matrix is a matrix obtained by masking other vectors except for the first unit vector by using the mask layer, the first mask matrix is a matrix obtained by masking the first unit vector by using the mask layer, and if the first unit vector is a first row vector in the normalized adjacent matrix, the first mask matrix is a matrix that only retains the first row vector in the normalized adjacent matrix, the other vectors are 0, the second mask matrix is a matrix that retains the first row vector in the normalized adjacent matrix, and the other vectors are retained.
S402, classifying the second mask matrix by using a classification model to obtain a first classification matrix and a second classification matrix.
S403, coupling the first mask matrix, the first classification matrix and the second classification matrix by adopting a coupling layer to generate an initial processed adjacent matrix.
The classification model may classify the second mask matrix a 2 (0) using a multi-layer perceptron (Multiple Layer Perceptron, MLP) model, where the classification model fits the second mask matrix using s and t functions to obtain a first classification matrix s (a 2 (0)) and a second classification matrix t (a 2 (0)).
The coupling layer may employ an affine coupling layer (Affine Coupling layer) to couple the first mask matrix, the first classification matrix, and the second classification matrix to obtain an initial processed adjacency matrix, where the coupling formula is as follows:
wherein, Represented as a first matrix of masks,Represented as a second mask matrix,Represented as a first classification matrix,Represented as a second classification matrix,Represented as a third mask matrix,Represented as a fourth mask matrix.
And processing the second mask matrix by the classification model, and coupling to obtain a third mask matrix, wherein the third mask matrix is a matrix for masking other vectors except the first unit vector of the initial processed adjacent matrix, the third mask matrix is different from the first mask matrix in that the first unit vector is different, the first unit vector of the first mask matrix is an integer, and the first unit vector of the third mask matrix is a floating point number. The fourth mask matrix is a matrix for masking the first unit vector of the initially processed adjacent matrix, and since the other vectors than the first unit vector are not processed, the fourth mask matrix is identical to the second mask matrix, and the third mask matrix and the fourth mask matrix are superimposed to obtain the initially processed adjacent matrix. And similarly, sequentially carrying out continuous processing on the second unit vectors in the initial processed adjacent matrix by adopting a countercurrent unit to obtain the processed adjacent matrix when the number of the processed unit vectors meets the preset number threshold.
It should be noted that, according to the initially processed adjacency matrix, the normalized adjacency matrix can be restored by the countercurrent unit, and the specific restoration formula is expressed as follows:
And then the first mask matrix and the second mask matrix are overlapped, and the normalized adjacent matrix can be restored.
In the method provided by the embodiment of the application, a masking layer is adopted to mask other vectors except the first unit vector in the normalized adjacent matrix to obtain a first masking matrix, and masking is carried out on the first unit vector in the normalized adjacent matrix to obtain a second masking matrix; classifying the second mask matrix by adopting a classification model to obtain a first classification matrix and a second classification matrix; and adopting a coupling layer to couple the first mask matrix, the first classification matrix and the second classification matrix to generate an initial processed adjacent matrix. Thus, the first unit vector in the normalized adjacency matrix is subjected to first processing, and the initial processed adjacency matrix is obtained.
The embodiment of the application also provides another possible implementation manner of the circuit topology diagram generating method, and fig. 7 is a schematic structural diagram of a countercurrent model provided by the embodiment of the application. as shown in fig. 7, an initial adjacency matrix a (0) is input, the parameters in the initial adjacency matrix are normalized to [ -1,1] by a normalization unit ActNorm, then the other vectors than the first unit vector in the normalized adjacency matrix are masked by a masking layer Mask in a counter flow unit to obtain a first masking matrix a 1 (0), And masking the first unit vector in the normalized adjacency matrix to obtain a second mask matrix A 2 (0), classifying the second mask matrix A 2 (0) by the classification model MLP and the scaling layer Rescale, Obtaining a first classification matrix s (A 2 (0)) and a second classification matrix t (A 2 (0)), and finally using a coupling layer AffineCoupling to couple the first mask matrix A 1 (0), The first classification matrix s (a 2 (0)) and the second classification matrix t (a 2 (0)) are coupled, A third mask matrix a 1 (1) is obtained, The third mask matrix a 1 (1) and the fourth mask matrix a 2 (1) are superimposed to obtain an initial processed adjacency matrix a (1). then, the second unit vector of the initial processed adjacency matrix a (1) is processed continuously to obtain the processed adjacency matrix a (n), and the process of processing the second unit vector continuously is similar to that of processing the first unit vector, which is not described in detail herein.
The embodiment of the application also provides another possible implementation manner of the circuit topology graph generation method, and fig. 8 is a fifth flow chart of the circuit topology graph generation method provided by the embodiment of the application. As shown in fig. 8, according to the initial continuous vector, the performance prediction is performed by using a preset performance prediction model corresponding to the target circuit performance, and before the initial circuit performance parameters of the initial circuit topology are obtained, the method further includes:
S501, acquiring a plurality of circuit topological graphs and adjacent matrixes of the circuit topological graphs according to a preset circuit function.
S502, performing device parameter tuning on the multiple circuit topological graphs to obtain circuit performance parameters of the multiple circuit topological graphs.
S503, generating a training data set according to the adjacency matrix of the plurality of circuit topological graphs and the circuit performance parameters of the plurality of circuit topological graphs.
In this embodiment, according to a preset circuit function, a plurality of circuit topology diagrams for realizing the preset circuit function and adjacent matrixes of the plurality of circuit topology diagrams are obtained, then device parameter tuning is performed on the plurality of circuit topology diagrams respectively, circuit performance parameters of the plurality of circuit topology diagrams are obtained, and a training data set is generated according to the adjacent matrixes of the plurality of circuit topology diagrams and the circuit performance parameters.
S504, training the initial countercurrent model and the initial performance prediction model by adopting a training data set to obtain the countercurrent model and the performance prediction model.
Wherein, the countercurrent flow model and the performance prediction model are respectively denoted as f and g, and the countercurrent flow model f is denoted as: z=f (a), the performance prediction model g is expressed as: the performance prediction model is optimized through a limited memory quasi-Newton method (L-BFGS), and the parameters of the countercurrent model and the performance prediction model are trained according to the following purposes:
According to the method provided by the embodiment of the application, a plurality of circuit topological graphs and adjacent matrixes of the circuit topological graphs are obtained according to a preset circuit function, device parameter tuning is carried out on the circuit topological graphs to obtain circuit performance parameters of the circuit topological graphs, a training data set is generated according to the adjacent matrixes of the circuit topological graphs and the circuit performance parameters of the circuit topological graphs, and the training data set is adopted to train an initial countercurrent model and an initial performance prediction model to obtain the countercurrent model and the performance prediction model. The countercurrent model and the performance prediction model can determine the target circuit topological graph according to the initial circuit topological graph and the initial adjacency matrix of the initial circuit topological graph.
The embodiment of the application also provides another possible implementation manner of the circuit topology diagram generating method, and the method comprises the steps of:
According to the preset circuit function, an initial circuit topological graph is randomly generated, and an initial adjacency matrix of the initial circuit topological graph is obtained.
Or according to the preset circuit function, acquiring an initial circuit topology diagram from the existing circuit topology set corresponding to the preset circuit function, and acquiring an initial adjacency matrix of the initial circuit topology diagram.
Specifically, the initial circuit topology map is randomly generated according to the preset circuit function and the circuit devices required by the preset circuit function, or the initial circuit topology map is obtained from the existing circuit topology set corresponding to the preset circuit function according to the preset circuit function, and the mode of obtaining the initial circuit topology map is not limited.
The circuit topology generating device and the computer device provided by any of the embodiments of the present application are further explained correspondingly, and specific implementation processes and technical effects thereof are the same as those of the corresponding method embodiments, and for brevity, reference may be made to corresponding contents in the method embodiments for the parts not mentioned in the present embodiment.
Fig. 9 is a schematic functional block diagram of a circuit topology generating apparatus according to an embodiment of the present application. As shown in fig. 9, the circuit topology generation apparatus 100 includes:
the obtaining module 110 is configured to obtain an initial circuit topology diagram and an initial adjacency matrix of the initial circuit topology diagram according to a preset circuit function, where the initial circuit topology diagram is: the initial adjacency matrix comprises a plurality of topological nodes and connecting lines among the topological nodes: indication information of circuit devices between every two topology nodes in the plurality of topology nodes;
The mapping module 120 is configured to map the initial adjacency matrix into an initial continuous vector by using a preset reversible flow model;
The updating module 130 is configured to update the initial continuous vector according to a target circuit performance of a preset circuit function, so as to obtain a target continuous vector;
A reduction module 140, configured to reduce the target continuous vector to a target adjacent matrix by using a countercurrent model;
The determining module 150 is configured to determine a circuit topology map corresponding to the target adjacency matrix as a target circuit topology map with a preset circuit function.
Optionally, the updating module 130 is further configured to perform performance prediction by using a preset performance prediction model corresponding to the target circuit performance according to the initial continuous vector, so as to obtain an initial circuit performance parameter of the initial circuit topology; updating an initial continuous vector according to the initial circuit performance parameters; and carrying out performance prediction again by adopting a preset performance prediction model according to the updated continuous vector until a preset iteration stop condition is reached, and determining the continuous vector when the preset iteration stop condition is reached as a target continuous vector.
Optionally, the counter-flow model comprises: the device comprises a normalization unit, a countercurrent unit and a connecting unit; the mapping module 120 is further configured to normalize parameters in the initial adjacency matrix to a preset parameter range by using a normalization unit, so as to obtain a normalized adjacency matrix; performing first processing on a first unit vector in the normalized adjacent matrix by adopting a countercurrent unit to obtain an initial processed adjacent matrix; adopting a countercurrent unit to continuously process the second unit vector in the initial processed adjacent matrix until the number of the processed unit vectors meets a preset number threshold; and generating initial continuous vectors by adopting a connection unit according to the processed adjacent matrixes when the number of the processed unit vectors meets a preset number threshold.
Optionally, the counter flow unit comprises: a mask layer, a classification model and a coupling layer; the mapping module 120 is further configured to mask other vectors except the first unit vector in the normalized adjacent matrix by using a mask layer to obtain a first mask matrix, and mask the first unit vector in the normalized adjacent matrix to obtain a second mask matrix; classifying the second mask matrix by adopting a classification model to obtain a first classification matrix and a second classification matrix; and adopting a coupling layer to couple the first mask matrix, the first classification matrix and the second classification matrix to generate an initial processed adjacent matrix.
Optionally, the circuit topology map generating apparatus 100 further includes:
The training module is used for acquiring a plurality of circuit topological graphs and adjacent matrixes of the circuit topological graphs according to a preset circuit function; performing device parameter tuning on the multiple circuit topological graphs to obtain circuit performance parameters of the multiple circuit topological graphs; generating a training data set according to the adjacency matrix of the plurality of circuit topological graphs and the circuit performance parameters of the plurality of circuit topological graphs; and training the initial countercurrent model and the initial performance prediction model by adopting a training data set to obtain the countercurrent model and the performance prediction model.
Optionally, the obtaining module 110 is further configured to randomly generate an initial circuit topology map according to a preset circuit function, and obtain an initial adjacency matrix of the initial circuit topology map; or according to the preset circuit function, acquiring an initial circuit topology diagram from the existing circuit topology set corresponding to the preset circuit function, and acquiring an initial adjacency matrix of the initial circuit topology diagram.
The foregoing apparatus is used for executing the method provided in the foregoing embodiment, and its implementation principle and technical effects are similar, and are not described herein again.
The above modules may be one or more integrated circuits configured to implement the above methods, for example: one or more Application SPECIFIC INTEGRATED Circuits (ASIC), or one or more microprocessors, or one or more field programmable gate arrays (Field Programmable GATE ARRAY FPGA), etc. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Fig. 10 is a schematic diagram of a computer device according to an embodiment of the present application, where the computer device may be used for generating a circuit topology map. As shown in fig. 10, the electronic apparatus 200 includes: a processor 210, a storage medium 220, and a bus 230.
The storage medium 220 stores machine-readable instructions executable by the processor 210. When the computer device is running, the processor 210 communicates with the storage medium 220 via the bus 230, and the processor 210 executes the machine-readable instructions to perform the steps of the method embodiments described above. The specific implementation manner and the technical effect are similar, and are not repeated here.
Optionally, the present application further provides a storage medium 220, where the storage medium 220 stores a computer program, which when executed by a processor performs the steps of the above-described method embodiments. The specific implementation manner and the technical effect are similar, and are not repeated here.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (english: processor) to perform some of the steps of the methods according to the embodiments of the invention. And the aforementioned storage medium includes: u disk, mobile hard disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily appreciate variations or alternatives within the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (9)
1. A circuit topology generation method, comprising:
according to a preset circuit function, an initial circuit topological graph and an initial adjacency matrix of the initial circuit topological graph are obtained, wherein the initial circuit topological graph is as follows: a plurality of topology nodes and a connection between topology nodes, the initial adjacency matrix comprising: indication information of circuit devices between every two topology nodes in the plurality of topology nodes;
Mapping the initial adjacent matrix into an initial continuous vector by adopting a preset countercurrent model;
updating the initial continuous vector according to the target circuit performance of the preset circuit function to obtain a target continuous vector;
Reducing the target continuous vector into a target adjacent matrix by adopting the countercurrent model;
determining a circuit topology diagram corresponding to the target adjacent matrix as a target circuit topology diagram of the preset circuit function;
the reversible flow model comprises: the device comprises a normalization unit, a countercurrent unit and a connecting unit; the mapping the initial adjacency matrix into an initial continuous vector by adopting a preset countercurrent model comprises the following steps:
Normalizing parameters in the initial adjacency matrix to a preset parameter range by adopting the normalization unit to obtain a normalized adjacency matrix;
performing first processing on a first unit vector in the normalized adjacent matrix by adopting the countercurrent unit to obtain an initial processed adjacent matrix;
adopting the countercurrent unit to continuously process the second unit vector in the initial processed adjacent matrix until the number of the processed unit vectors meets a preset number threshold;
generating the initial continuous vector according to the processed adjacent matrix when the number of the processed unit vectors meets the preset number threshold by adopting the connecting unit;
the countercurrent unit includes: a mask layer;
And masking other vectors except the first unit vector in the normalized adjacent matrix by adopting the masking layer to obtain a first masking matrix, and masking the first unit vector in the normalized adjacent matrix to obtain a second masking matrix.
2. The method of claim 1, wherein updating the initial continuous vector according to the target circuit performance of the preset circuit function to obtain the target continuous vector comprises:
according to the initial continuous vector, performing performance prediction by adopting a preset performance prediction model corresponding to the target circuit performance to obtain initial circuit performance parameters of the initial circuit topological graph;
updating the initial continuous vector according to the initial circuit performance parameter;
and carrying out performance prediction again by adopting the preset performance prediction model according to the updated continuous vector until a preset iteration stop condition is reached, and determining the continuous vector when the preset iteration stop condition is reached as the target continuous vector.
3. The method of claim 1, wherein the counter-current unit further comprises: a classification model, a coupling layer;
Classifying the second mask matrix by adopting the classification model to obtain a first classification matrix and a second classification matrix;
and adopting the coupling layer to couple the first mask matrix, the first classification matrix and the second classification matrix to generate the initial processed adjacency matrix.
4. The method according to claim 2, wherein the preset iteration stop condition is: and reaching the preset iteration times, or enabling the circuit performance after performance prediction is performed again by the preset performance prediction model to meet the target circuit performance.
5. The method according to claim 2, wherein before performing performance prediction according to the initial continuous vector by using a preset performance prediction model corresponding to the target circuit performance to obtain an initial circuit performance parameter of the initial circuit topology, the method further comprises:
acquiring a plurality of circuit topological graphs and adjacent matrixes of the circuit topological graphs according to the preset circuit function;
Performing device parameter tuning on the plurality of circuit topological graphs to obtain circuit performance parameters of the plurality of circuit topological graphs;
Generating a training data set according to the adjacency matrix of the plurality of circuit topological graphs and the circuit performance parameters of the plurality of circuit topological graphs;
and training an initial countercurrent model and an initial performance prediction model by adopting the training data set to obtain the countercurrent model and the performance prediction model.
6. The method of claim 1, wherein the obtaining an initial circuit topology and an initial adjacency matrix for the initial circuit topology according to a preset circuit function comprises:
according to the preset circuit function, randomly generating the initial circuit topological graph, and acquiring an initial adjacency matrix of the initial circuit topological graph; or alternatively
According to the preset circuit function, the initial circuit topology diagram is obtained from the existing circuit topology set corresponding to the preset circuit function, and an initial adjacency matrix of the initial circuit topology diagram is obtained.
7. A circuit topology generation apparatus, the apparatus comprising:
The acquisition module is used for acquiring an initial circuit topological graph and an initial adjacency matrix of the initial circuit topological graph according to a preset circuit function, wherein the initial circuit topological graph is as follows: a plurality of topology nodes and a connection between topology nodes, the initial adjacency matrix comprising: indication information of circuit devices between every two topology nodes in the plurality of topology nodes;
the mapping module is used for mapping the initial adjacent matrix into an initial continuous vector by adopting a preset countercurrent model;
The updating module is used for updating the initial continuous vector according to the target circuit performance of the preset circuit function to obtain a target continuous vector;
The reduction module is used for reducing the target continuous vector into a target adjacent matrix by adopting the countercurrent model;
The determining module is used for determining a circuit topology diagram corresponding to the target adjacent matrix as a target circuit topology diagram of the preset circuit function;
The reversible flow model comprises: the device comprises a normalization unit, a countercurrent unit and a connecting unit; the mapping module is further configured to normalize parameters in the initial adjacency matrix to a preset parameter range by using the normalization unit, so as to obtain a normalized adjacency matrix; performing first processing on a first unit vector in the normalized adjacent matrix by adopting the countercurrent unit to obtain an initial processed adjacent matrix; adopting the countercurrent unit to continuously process the second unit vector in the initial processed adjacent matrix until the number of the processed unit vectors meets a preset number threshold; generating the initial continuous vector according to the processed adjacent matrix when the number of the processed unit vectors meets the preset number threshold by adopting the connecting unit;
The countercurrent unit includes: a mask layer; the mapping module is further configured to mask other vectors except the first unit vector in the normalized adjacency matrix by using the mask layer to obtain a first mask matrix, and mask the first unit vector in the normalized adjacency matrix to obtain a second mask matrix.
8. A computer device, comprising: a processor, a storage medium and a bus, the storage medium storing program instructions executable by the processor, the processor and the storage medium communicating over the bus when the computer device is running, the processor executing the program instructions to perform the steps of the circuit topology method of any of claims 1 to 6.
9. A computer-readable storage medium, characterized in that the storage medium has stored thereon a computer program which, when executed by a processor, performs the steps of the circuit topology method of any of claims 1 to 6.
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