CN117518709A - Photomask and overlay error measurement methods - Google Patents
Photomask and overlay error measurement methods Download PDFInfo
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- CN117518709A CN117518709A CN202311475712.4A CN202311475712A CN117518709A CN 117518709 A CN117518709 A CN 117518709A CN 202311475712 A CN202311475712 A CN 202311475712A CN 117518709 A CN117518709 A CN 117518709A
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- 238000000691 measurement method Methods 0.000 title claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 16
- 238000000034 method Methods 0.000 abstract description 13
- 238000005520 cutting process Methods 0.000 abstract description 10
- 238000005259 measurement Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/44—Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
The application provides a photomask and an overlay error measurement method, wherein the photomask comprises a center mark pattern and a bar pattern; setting a bar pattern around the center mark pattern; the mark patterns which initially surround the bar patterns are reduced to form a center mark pattern, and the center mark pattern is arranged between the bar patterns to form a standard pattern, so that offset errors of overlapping design patterns are obtained after the wafer is exposed by using a photomask. According to the embodiment of the specification, the process steps and the like do not need to be improved, the standard pattern with new design is formed by recombining the cross corresponding to the periphery of the MASK and the strip pattern placed on the cutting path in the MASK, and the pattern is placed at different positions on the cutting path of the photomask, so that not only can the offset corresponding to the photomask be obtained, but also the offset of pattern overlapping in the exposure process can be accurately obtained. Namely, the efficiency and the quality of the chip manufacturing process are greatly improved through smaller improvement on the standard patterns.
Description
Technical Field
The present disclosure relates to the field of semiconductor measurement, and in particular, to a photomask and an overlay error measurement method.
Background
An integrated circuit (chip) is fabricated by a lithographic process characterized by a series of lithographic processes for each layer of the chip to transfer the pattern on the photomask to wafer (as shown in fig. 1A). The complex circuit structure of the chip meets the design requirement by the effective overlapping among all the hole line layers. If the overlay difference between the layers after exposure is too large (as shown in fig. 1B), the circuit pattern on wafer after exposure will shift, and the electrical property of the circuit will be affected to a certain extent by the amount of shift, so that the performance of the chip is reduced.
Thus, a new photomask solution is needed.
Disclosure of Invention
In view of the foregoing, embodiments of the present disclosure provide a photomask and overlay error measurement method.
The embodiment of the specification provides the following technical scheme:
embodiments of the present disclosure provide a photomask, the photomask comprising: a center mark pattern and a bar pattern;
setting a bar pattern around the center mark pattern;
and the central mark patterns are arranged between the bar patterns to form standard patterns, so that offset errors of overlapping design patterns are obtained after the wafer is exposed by adopting the photomask.
The embodiment of the specification also provides an overlay error measurement method, which adopts the photomask in the technical scheme to expose the wafer to obtain the target design pattern so as to obtain the offset error of the overlapping design patterns.
Compared with the prior art, the beneficial effects that above-mentioned at least one technical scheme that this description embodiment adopted can reach include at least:
according to the embodiment of the specification, the process steps and the like do not need to be improved, the standard pattern with new design is formed by recombining the cross corresponding to the periphery of the MASK and the strip pattern placed on the cutting path in the MASK, and the pattern is placed at different positions on the cutting path of the photomask, so that not only can the offset corresponding to the photomask be obtained, but also the offset of pattern overlapping in the exposure process can be accurately obtained. Namely, the efficiency and the quality of the chip manufacturing process are greatly improved through smaller improvement on the standard patterns.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of overlay error during chip exposure;
FIG. 2 is a schematic illustration of a prior art OVL mark placement location;
FIG. 3 is a schematic diagram of the mask end and wafer end measuring OVL marks at different positions to obtain different offset values;
FIG. 4 is a schematic illustration of a photomask overlay mark design pattern of the present application;
FIG. 5 is a schematic illustration of New OVL mark in the present application;
FIG. 6 is a graph showing correlation between old and new OVL measurements and chip side measurements.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details.
The wafer exposure pattern is transferred from the photomask, and if there is an overlay error (overlay value) between the layers of the photomask itself, this error is directly reflected to the wafer end. However, if the fab is able to know the error value before wafer exposure, the overlay error can be effectively reduced by adjusting the exposure settings, so the photomask fab needs to provide the error value to the fab. And each layer of patterns of the chip are different, and the required overlay cannot be obtained accurately by directly comparing the differences between the circuit patterns.
In the present stage, a cross mark (as shown in fig. 2) is placed in the scribe line and the outer frame during the manufacture of the photomask, and is used as an OVL mark for detecting the overlay of the photomask, the photomask manufacturer measures the center position of the cross after the manufacture of the photomask, and the offset between each photomask and the design size is obtained by comparing the design coordinates of the mark (as shown in the left example of fig. 3), so that the customer can judge and judge whether the manufacture of the photomask meets the design requirement according to the offset. After the customer takes the photomask to expose at the wafer end, the photomask is placed on an ovmark in the measured customer pattern to obtain an overlay value of the wafer end (as illustrated in the right example of fig. 3), but the correlation between the two obtained sets of overlay values is lower, and the correlation coefficient is less than 0.5.
In view of this, the inventor has found that a new standard pattern needs to be designed, the standard pattern is placed in a designated position of the photomask, and the difference between the photomask and the design Layout can be obtained by measuring the difference between the standard pattern and the design dimension, so that the difference is fed back to the chip factory, and the quality of the chip is improved.
Based on this, the embodiments of the present specification propose a new photomask scheme: based on the conventional standard patterns, such as setting a cross Mark in a cutting channel and an outer frame, the new standard pattern combines the cross structure originally placed at the periphery of the Mark with the bar pattern placed on the cutting channel inside the Mark to form the new standard pattern. Thus, the offset of the photomask and the design pattern is obtained by measuring the center coordinates of the cross patterns at different positions. And then measuring the coordinates of the four-edge strip-shaped structure after the exposure of the wafer according to the photomask corresponding to the photomask to obtain the offset of the wafer end, and analyzing two groups of offset data to obtain a distribution diagram with a definite linear relationship (as shown in fig. 6). As can be seen from FIG. 6, the correlation coefficient of the two sets of offset data obtained by measurement is higher than 0.85. In other words, the embodiments of the present disclosure design new standard patterns on a photomask to determine the overlay alignment of the patterns, thereby accurately copying the design patterns on the photomask to the chip.
The following describes the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.
In the embodiment of the present disclosure, based on the conventional OVLmark, specifically, a cross mark (as shown in fig. 2) is placed in the scribe line and the outer frame, and is used as the OVLmark for detecting the overlay of the photomask, the photomask manufacturer measures the center position of the cross after the photomask is manufactured, and the offset between each photomask and the design size is obtained by comparing the design coordinates of the mark, so that whether the photomask manufacturing meets the design requirement can be determined and judged according to the offset. As shown in fig. 3, the left is the offset between the photomask and the design dimension, and the right is the offset of the photomask where the patterns overlap after wafer exposure. However, by analyzing the offset between the photomask and the design dimension, the correlation between the offset at the wafer end according to the photomask exposure is low, i.e. the chip manufacturing process cannot be guided.
Therefore, the embodiment of the present disclosure designs a new standard pattern, i.e., based on the conventional standard pattern (as shown in fig. 2), the cross initially set at the periphery of Mark and the bar pattern placed on the internal scribe line of Mark are recombined to form a complete new designed standard pattern, as shown in fig. 4. Specifically, the Mark patterns which are initially arranged on the periphery of the Mark and surround the internal cutting lines are provided with the bar patterns, and the center Mark patterns are formed after the appropriate size reduction, so that the center Mark patterns in the new standard patterns are arranged between the bar patterns, not only can the offset between the photomask corresponding to the photomask and the design pattern be obtained, but also the offset which is overlapped according to the patterns of the photomask after exposure on the wafer can be obtained, and a higher linear correlation exists between the offset and the offset, thereby the two offsets can be used as the judgment basis of the manufacturing quality of the photomask, and the data basis is provided for the adjustment of the technological parameters in the chip manufacturing process, and the quality and the efficiency of the chip manufacturing are improved.
According to the embodiment of the specification, the process steps and the like do not need to be improved, the standard patterns with new designs are formed by combining the cross corresponding to the periphery of the MASK and the center of the strip-shaped patterns placed on the internal cutting path of the MASK, and the patterns are placed at different positions on the cutting path of the photomask, so that not only the offset corresponding to the photomask, but also the offset of pattern overlapping in the exposure process can be accurately obtained. Namely, the efficiency and the quality of the chip manufacturing process are greatly improved through smaller improvement on the standard patterns.
In some embodiments, the center mark pattern and the bar pattern are in a rotationally symmetrical structure, and the total length of the center mark pattern and the bar pattern is 40 μm.
As shown in fig. 4, the embodiment of the present disclosure provides a rotationally symmetrical structure of the center mark pattern and the stripe pattern in the measurement standard pattern on the photomask. Based on the design dimensions of the conventional standard pattern, the total length of the center mark pattern and the bar pattern in some embodiments is 40 μm.
In some embodiments, the center mark pattern and the bar pattern are integrally disposed at different locations of the photomask scribe line.
In connection with the above embodiments, as shown in fig. 4 and 5, a newly designed standard pattern composed of a center mark pattern and a stripe pattern is disposed at different positions of the scribe line on the photomask (e.g., black squares in fig. 5). The offset of the photomask and the design pattern is obtained by measuring the center positions of the cross patterns at different positions. And further measuring the coordinates of the four-edge strip-shaped structure after the wafer is exposed to obtain the offset of the wafer end, and analyzing two groups of offset data to obtain a distribution diagram with a definite linear relation.
In some embodiments, the center mark pattern is used to obtain the error between the photomask and the design pattern, and the stripe pattern is exposed to the wafer to obtain the offset error of the overlay of the design pattern.
In combination with the above embodiment, the standard pattern designed in the embodiment of the present disclosure is placed on the photomask, and the offset between the photomask and the designed pattern is obtained by measuring the center coordinates of the standard pattern corresponding to the center mark pattern in different positions. And further, measuring the coordinates of the corresponding four-side strip-shaped structures on the chip according to the photo mask after the wafer is exposed to obtain the offset of the wafer end, thereby obtaining the offset error of overlapping the design patterns.
In some embodiments, the center mark pattern is a center symmetrical pattern. In some embodiments, the center mark pattern comprises a cross shape. The length of the center mark pattern is 5um.
The newly designed standard pattern in this specification is modified based on the conventional over Mark pattern by combining the cross originally placed on the periphery of Mark with the bar pattern placed on the scribe line inside Mark (as shown in fig. 4) to form a new standard pattern. As shown in fig. 4, in the new standard pattern, the center mark pattern is a center symmetrical pattern, and the center mark pattern includes, but is not limited to, a cross shape. And as shown in fig. 4, in order to reduce the size of the conventionally set center Mark pattern from 15 μm to 5 μm under the condition that the standard pattern size is not changed, the center Mark pattern can be placed from the original Mark periphery, the middle part of the bar pattern placed on the Mark inner cutting line is improved so as to obtain the error between the photomask and the design pattern, and the offset of the overlay of the design pattern can be obtained after the wafer is exposed, so that the process parameters and the like in the chip manufacturing process can be correspondingly adjusted according to the offset, and the quality and the efficiency of the chip manufacturing are improved.
In some embodiments, the bar graph includes horizontal bars, vertical bars; the center mark patterns are symmetrically arranged corresponding to the areas of the bar patterns.
In combination with the above embodiment, in the standard pattern newly designed in the embodiment of the present specification, the bar pattern includes a horizontal stripe and a vertical stripe. As shown in fig. 4, vertical stripes, horizontal stripes, vertical stripes, and horizontal stripes are provided clockwise in the standard pattern. Of course, the specific design sequence of the vertical stripes and the horizontal stripes in the bar graph is determined according to different actual conditions.
As shown in fig. 4, the central mark patterns are symmetrically arranged in the length, width and other directions corresponding to the surrounding bar patterns, i.e. the areas of the central mark patterns corresponding to the bar patterns are symmetrically arranged.
In some embodiments, the bar graph includes stripes of different sizes.
In combination with the above embodiment, in the newly designed standard pattern, the size of each stripe corresponding to the stripe pattern may be set according to the actual size, or the horizontal and vertical stripes with different sizes may be set in the same newly designed standard pattern. The bar patterns can be arranged as transverse stripes or vertical stripes of different sizes, etc.
In combination with the above embodiments, the embodiments of the present disclosure further provide a method for measuring overlay error, specifically, a photomask including a new design standard pattern is used, exposure is performed on a wafer to obtain a target design pattern, and the coordinates of the surrounding bar structures in the standard pattern are measured to obtain an offset of overlay of the design pattern at the wafer end, where the offset has practical production guiding significance, and the offset can be provided to a chip manufacturer to make corresponding adjustment on the chip manufacturing process parameters, so as to improve the quality and efficiency of chip manufacturing.
It is noted that the terms "first," "second," "third," "fourth," and the like in the description and claims of the invention and in the foregoing figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.
The same and similar parts of the embodiments in this specification are all mutually referred to, and each embodiment focuses on the differences from the other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the description is relatively simple, and reference is made to the description of parts of the system embodiments.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A photomask comprising a center mark pattern and a bar pattern;
setting a bar pattern around the center mark pattern;
and the central mark patterns are arranged between the bar patterns to form standard patterns, so that offset errors of overlapping design patterns are obtained after the wafer is exposed by adopting the photomask.
2. The photomask of claim 1, wherein the center mark pattern and the stripe pattern are in a rotationally symmetrical structure, and the total length of the center mark pattern and the stripe pattern is 40um.
3. The photomask of claim 1 wherein the center mark pattern and the stripe pattern are integrally disposed at different locations of the scribe line on the photomask.
4. The photomask of claim 1 wherein the center mark pattern is used to obtain an error between the photomask and the design pattern and the stripe pattern is used to obtain an offset error of the overlay of the design pattern after being exposed to the wafer.
5. The photomask of claim 1 wherein the center mark pattern is a center symmetrical pattern.
6. The photomask of claim 1 wherein the center mark pattern comprises a cross shape.
7. The photomask of claim 6 wherein the center mark pattern has a length of 5um.
8. The photomask of claim 1 wherein the bar pattern comprises horizontal stripes, vertical stripes; the center mark patterns are symmetrically arranged corresponding to the areas of the bar patterns.
9. The photomask of claim 1 wherein the bar pattern comprises stripes of different sizes.
10. An overlay error measurement method, wherein the target design pattern is obtained by exposing the wafer with the photomask according to any of claims 1-9, so as to obtain the offset error of the overlay of the design patterns.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311475712.4A CN117518709A (en) | 2023-11-07 | 2023-11-07 | Photomask and overlay error measurement methods |
| PCT/CN2024/096218 WO2025097739A1 (en) | 2023-11-07 | 2024-05-30 | Optical mask, and overlap error measurement method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311475712.4A CN117518709A (en) | 2023-11-07 | 2023-11-07 | Photomask and overlay error measurement methods |
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|---|---|
| CN117518709A true CN117518709A (en) | 2024-02-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311475712.4A Pending CN117518709A (en) | 2023-11-07 | 2023-11-07 | Photomask and overlay error measurement methods |
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| CN (1) | CN117518709A (en) |
| WO (1) | WO2025097739A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2025097739A1 (en) * | 2023-11-07 | 2025-05-15 | 广州新锐光掩模科技有限公司 | Optical mask, and overlap error measurement method |
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| US20110051150A1 (en) * | 2009-08-31 | 2011-03-03 | Kla-Tencor Corporation | Unique mark and method to determine critical dimension uniformity and registration of reticles combined with wafer overlay capability |
| US20140362363A1 (en) * | 2013-06-05 | 2014-12-11 | Semiconductor Manufacturing International (Shanghai) Corporation | Methods for monitoring source symmetry of photolithography systems |
| CN108459463A (en) * | 2017-02-22 | 2018-08-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of light shield and preparation method thereof |
| US20190137881A1 (en) * | 2016-06-10 | 2019-05-09 | Imec Vzw | Method and Apparatus for Semiconductor Manufacturing |
| CN115542681A (en) * | 2022-09-29 | 2022-12-30 | 上海积塔半导体有限公司 | Method, device and system for processing alignment deviation of photoetching machine |
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| JP4525067B2 (en) * | 2003-12-12 | 2010-08-18 | 株式会社ニコン | Misalignment detection mark |
| KR102094974B1 (en) * | 2013-03-08 | 2020-03-30 | 삼성전자주식회사 | Methods for overlay measurements |
| CN117518709A (en) * | 2023-11-07 | 2024-02-06 | 广州新锐光掩模科技有限公司 | Photomask and overlay error measurement methods |
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2023
- 2023-11-07 CN CN202311475712.4A patent/CN117518709A/en active Pending
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- 2024-05-30 WO PCT/CN2024/096218 patent/WO2025097739A1/en active Pending
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| US20110051150A1 (en) * | 2009-08-31 | 2011-03-03 | Kla-Tencor Corporation | Unique mark and method to determine critical dimension uniformity and registration of reticles combined with wafer overlay capability |
| US20140362363A1 (en) * | 2013-06-05 | 2014-12-11 | Semiconductor Manufacturing International (Shanghai) Corporation | Methods for monitoring source symmetry of photolithography systems |
| US20190137881A1 (en) * | 2016-06-10 | 2019-05-09 | Imec Vzw | Method and Apparatus for Semiconductor Manufacturing |
| CN108459463A (en) * | 2017-02-22 | 2018-08-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of light shield and preparation method thereof |
| CN115542681A (en) * | 2022-09-29 | 2022-12-30 | 上海积塔半导体有限公司 | Method, device and system for processing alignment deviation of photoetching machine |
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| WO2025097739A1 (en) * | 2023-11-07 | 2025-05-15 | 广州新锐光掩模科技有限公司 | Optical mask, and overlap error measurement method |
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| WO2025097739A1 (en) | 2025-05-15 |
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| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Country or region after: China Address after: No. 2 Xinxinguang 1st Street, Xinxinguang Industrial Park, Huangpu District, Guangzhou City, Guangdong Province 510799 Applicant after: Guangzhou Xinrui photomask Technology Co.,Ltd. Address before: 510555 Room 518, room 406, No. 1, Yichuang street, Guangzhou City, Guangdong Province (Zhongxin Guangzhou Knowledge City) Applicant before: Guangzhou Xinrui photomask Technology Co.,Ltd. Country or region before: China |