CN117525031A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
- Publication number
- CN117525031A CN117525031A CN202210901242.2A CN202210901242A CN117525031A CN 117525031 A CN117525031 A CN 117525031A CN 202210901242 A CN202210901242 A CN 202210901242A CN 117525031 A CN117525031 A CN 117525031A
- Authority
- CN
- China
- Prior art keywords
- substrate
- silicon via
- isolation ring
- layer
- ring structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present disclosure relates to a semiconductor structure and a method of fabricating the same, the semiconductor structure comprising: a substrate having a first surface and a second surface opposite to each other; a metal pad located on a side of the second surface facing away from the substrate; a through silicon via structure penetrating through the substrate in the thickness direction via the first surface and being in contact connection with the metal pad; orthographic projection of the metal pad on the second surface covers the bottom surface of the through silicon via structure; and the isolation ring structure is formed in the substrate and surrounds the through silicon via structure, wherein the inner side wall and the outer side wall of the isolation ring structure have a preset distance. The semiconductor structure prevents the metal material sputtered by the metal pad from diffusing into the substrate in the process of etching the through silicon via structure through the arrangement of the isolation ring structure, thereby improving the isolation performance of the through silicon via structure, reducing the risk of mutual communication between adjacent through silicon via structures and improving the yield of semiconductor products.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technology, and in particular, to a semiconductor structure and a method for fabricating the same.
Background
With the rapid development of integrated circuit technology, three-dimensional packaging technology is widely applied to various high-speed circuits and miniaturized systems due to good electrical performance and high reliability. Through silicon via (Through Silicon Via, TSV) technology is an emerging three-dimensional integrated circuit fabrication process for stacking chips to achieve interconnection, with electrical interconnection between different chips being achieved by fabricating several vertical interconnect TSV structures on a wafer. The TSV technology enables the development of integrated circuit layout from traditional two-dimensional side-by-side arrangement to more advanced three-dimensional stacking, and can maximize the density of chips stacked in the three-dimensional direction, minimize the interconnection lines between chips, and minimize the external dimensions, so that the frequency characteristic and the power characteristic of the circuit can be greatly improved, which is a very important technology in the current electronic packaging technology.
In TSV process technology, since the thinned wafer is also generally at the thickness of the micron level, holes or trenches with high aspect ratio need to be manufactured, for deep hole etching with high aspect ratio, the etching energy is generally enhanced, and the etching accessories are sputtered to the side walls of the holes or trenches and gradually accumulate and diffuse, so that the isolation performance of adjacent through silicon vias is reduced, and there is a risk of conduction.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a semiconductor structure and a method for manufacturing the same, which avoid the sputtering and diffusion of etching accessories from interfering with adjacent semiconductor structures or electronic components, and improve the performance and reliability of manufacturing semiconductor products.
To achieve the above and other related objects, one aspect of the present disclosure provides a semiconductor structure including a substrate, a metal pad, a through silicon via structure, and an isolation ring structure; the substrate is provided with a first surface and a second surface which are opposite; the metal pad is positioned on one side of the second surface, which is away from the substrate; the through silicon via structure penetrates through the substrate along the thickness direction through the first surface and is in contact connection with the metal pad; the orthographic projection of the metal pad on the second surface covers the bottom surface of the through silicon via structure; the isolation ring structure is formed in the substrate and surrounds the through silicon via structure, wherein the inner side wall and the outer side wall of the isolation ring structure have a preset distance.
In the above embodiment, the metal pad is located on the second surface of the substrate and is away from the side of the substrate, and the isolation ring structure is disposed in the region surrounding the through silicon via structure, and the etching material with very high energy is used for etching in the process of forming the through silicon via structure with high aspect ratio by the TSV etching process. The deep hole etching with high depth-to-width ratio generally strengthens the energy of etching materials, so that the bottom metal pad can inevitably bombard, the side wall of a hole is sputtered and gradually diffused to enable the isolation performance of the adjacent silicon through hole to be reduced, and the risk of conduction exists.
In some of these embodiments, the insulating ring structure extends through the substrate in the thickness direction through the first surface and to the second surface.
In some embodiments, an isolation protection layer is included between an inner sidewall of the isolation ring structure and an outer sidewall of the through silicon via structure.
In some of these embodiments, the isolation protection layer comprises an insulating material.
In some of these embodiments, the semiconductor structure further comprises a collar barrier layer; the annular blocking layer surrounds the through silicon via structure and is positioned between the isolation protection layer and the through silicon via structure.
In some of these embodiments, the annular barrier extends through the substrate in the thickness direction through the first surface and to the metal pad.
In some of these embodiments, a minimum distance between an inner sidewall of the isolation ring structure and an outer sidewall of the through silicon via structure is greater than or equal to 1 μm.
In some of these embodiments, the minimum distance between the outer sidewalls of adjacent insulating ring structures is greater than or equal to 1 μm.
In some of these embodiments, the predetermined distance is 2 μm to 10 μm.
In some embodiments, the isolation ring structure comprises a first low-k material layer surrounding the through-silicon via structure, a metal barrier layer surrounding the first low-k material layer, and a second low-k material layer surrounding the metal barrier layer.
In some of these embodiments, the material of the annular barrier includes at least one of tantalum, tantalum nitride, and titanium nitride.
Another aspect of the present disclosure provides a method for fabricating a semiconductor structure, comprising:
providing a substrate with a first surface and a second surface which are opposite to each other, and forming a metal pad on one side of the second surface, which is away from the substrate;
forming an isolation ring structure in the substrate, wherein a preset distance is reserved between the inner side wall and the outer side wall of the isolation ring structure;
forming a through silicon via structure in the substrate in the isolation ring structure, wherein the through silicon via structure penetrates through the substrate along the thickness direction through the first surface and is in contact connection with the metal pad; the orthographic projection of the metal pad on the second surface covers the bottom surface of the through silicon via structure.
In the above embodiment, the metal pad is formed on the side of the second surface of the substrate away from the substrate, and the isolation ring structure is formed before the through-silicon via structure is formed, the isolation ring structure surrounds the through-silicon via structure to be formed later, when the through-silicon via structure is formed in the substrate, high-energy etching is required to be performed on the substrate, when the etching is close to the upper surface of the metal pad, the metal pad is inevitably etched, so that the metal material in the metal pad is sputtered onto the side wall of the etching hole and gradually diffuses, and because the isolation ring structure is formed before the etching hole, the metal material sputtered onto the side wall stops diffusing when diffusing and contacting the isolation ring structure, one side of the isolation ring structure away from the through-silicon via structure cannot appear, so that the sputtered metal material cannot diffuse to the deep of the substrate to be communicated with the adjacent through-silicon via structure, the risk of conducting between different through-silicon via structures is avoided, the performance of the through-silicon via structure is improved, and the yield of a semiconductor product is improved.
In some of these embodiments, a first dielectric layer is formed between the metal pad and the second surface; the isolation ring structure comprises a first low dielectric constant material layer, a metal barrier layer and a second low dielectric constant material layer, wherein the first low dielectric constant material layer surrounds the through silicon via structure, the metal barrier layer surrounds the first low dielectric constant material layer, and the second low dielectric constant material layer surrounds the metal barrier layer; the step of forming an isolation ring structure in a substrate includes:
forming a second dielectric layer on the first surface of the substrate;
etching the second dielectric layer and the substrate to obtain an isolation ring gap, wherein part of the first dielectric layer is exposed out of the isolation ring gap;
forming a first low-dielectric-constant material layer, a metal barrier layer and a second low-dielectric-constant material layer in the isolation ring gap to obtain an isolation ring structure.
In some of these embodiments, the step of forming a through silicon via structure in the substrate within the isolation ring structure includes:
etching the second dielectric layer and the substrate in the isolation ring structure to obtain a through hole, wherein part of the metal pad is exposed out of the through hole;
forming an isolation protection layer on the side wall of the through hole;
depositing an annular barrier layer on the side wall of the isolation protection layer;
and filling the conductive material layer in the through hole, and carrying out planarization treatment to obtain the silicon through hole structure.
In some of these embodiments, a minimum distance between an inner sidewall of the isolation ring structure and an outer sidewall of the through silicon via structure is greater than or equal to 1 μm.
In some of these embodiments, the minimum distance between the outer sidewalls of adjacent insulating ring structures is greater than or equal to 1 μm.
In some of these embodiments, the predetermined distance is 2 μm to 10 μm.
Drawings
For a better description and illustration of those disclosed embodiments and/or examples disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of any of the disclosed disclosure, the presently described embodiments and/or examples, and the presently understood best mode of carrying out these disclosure.
FIGS. 1-2 are schematic cross-sectional views of a semiconductor structure during the process of etching a TSV in accordance with conventional techniques provided in one embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;
FIG. 4 is a schematic cross-sectional view of a semiconductor structure along the direction AA' in FIG. 3 according to one embodiment of the present disclosure;
FIG. 5 is a schematic flow chart of a method for fabricating a semiconductor structure according to an embodiment of the disclosure;
Fig. 6 is a schematic flow chart of a method for manufacturing a semiconductor structure according to another embodiment of the disclosure;
fig. 7 is a schematic flow chart of a method for manufacturing a semiconductor structure according to another embodiment of the disclosure;
fig. 8 shows a schematic cross-sectional view of a semiconductor structure provided in another embodiment of the present disclosure.
Reference numerals illustrate:
10. a substrate; 10a, a first surface; 10b, a second surface; 11. a metal pad; 111. etching the attachment; 12. a through silicon via structure; 13. an isolation ring structure; 14. an isolation protection layer; 15. an annular barrier; 16. a first dielectric layer; 17. a second dielectric layer; 131. a first low dielectric constant material layer; 132. a metal barrier layer; 133. a second low dielectric constant material layer.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on …," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The disclosed embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing, the regions illustrated in the figures being schematic in nature, and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
Please refer to fig. 1-8. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
With the development of integrated circuits and the transition of the times, the requirements of people on electronic products are approaching to the directions of smaller volume, more functions, greener color and the like, so people strive to find the technical directions that the smaller the electronic system is, the higher the integration level is, and the more functions are, and therefore, many new technologies, new materials and new designs are generated. Moore's law predicts that the number of components that can be accommodated on an integrated circuit doubles about 18-24 months apart when the price is unchanged, but as the physical size of Complementary Metal Oxide Semiconductor (CMOS) transistors approaches the limit, it is no longer reasonable to simply rely on reducing the transistor size to improve integrated circuit performance. It has become impossible to increase the performance of integrated circuits and reduce power consumption by means of shrinking transistor dimensions, and three-dimensional integrated circuits are considered as one of the viable solutions for continuing moore's law, further increasing the performance of integrated circuits and reducing power consumption, wherein stacked chip packaging techniques are typical of these techniques, and stacked chip packaging techniques are abbreviated as 3D packaging techniques, which refers to packaging techniques in which two or more chips are stacked in the vertical direction within the same package without changing the size of the package. The 3D Package has two modes of Package-on-Package (POP) and chip stack Package (chip stack), and the Package stack technology is generally obtained by stacking Thin Small Outline Package (TSOP) or chip size Package (Chip Scale Package, CSP) based on the conventional Package technology, however, there are long interconnection lines between chips, which limits the high frequency and high speed performance of the Package stack. Currently, TSV technology based on wafer manufacturing technology is receiving increasing attention from the semiconductor manufacturing industry, and the TSV technology realizes electrical interconnection between upper and lower chips by making vertical interconnection through holes on a wafer, as opposed to wire bonding, flip chip bonding, and other processes. TSV technology can reduce the interconnect length between two nodes, thus providing several advantages over two-dimensional integrated circuits: shorter signal delay, higher operating frequency, smaller parasitic capacitance and lower energy consumption, can effectively realize 3D chip lamination, and manufacture packages with more complex structure, stronger performance and cost efficiency.
As an example, referring to fig. 1-2, in the fabrication process of three-dimensional integrated circuits, TSVs have been used to form electrical connections between layers in stacked arrangements or 3D arrangements in devices such as MEMS (Micro-Electro-Mechanical System, microelectromechanical systems) and semiconductor devices, TSVs are important technologies in advanced packaging platforms, requiring etching of thinned wafers and other dielectric layers, and ultimately connection with metal pads, and since thinned wafers are also typically at a micrometer level of thickness, holes or trenches with a very large aspect ratio need to be fabricated in a substrate by advanced etching processes. In fig. 1, in deep hole etching with high aspect ratio on a substrate, energy of etching material is generally enhanced, and at this time, bombardment is inevitably generated on an underlying metal pad, so that etching appendages 111 are sputtered to the side walls of holes or trenches and gradually accumulate, and the etching appendages 111 sputtered to the side walls gradually infiltrate into the inside of the side walls and spread; in fig. 2, after the TSV process is completed, although the barrier layer is formed, the etching appendages 111 sputtered to the sidewalls of the holes are already diffused into the substrate, and when the etching appendages 111 diffused deep into the substrate are gradually increased, the adjacent through-silicon vias may be at risk of conducting, so that the isolation performance of the adjacent through-silicon vias is reduced, and the manufacturing defects of the TSV may seriously affect the production yield of semiconductor products. Accordingly, the present disclosure provides a semiconductor structure and a method for manufacturing the same, which can prevent the etching appendages 111 from diffusing into the substrate, i.e., prevent the material in the metal pad from diffusing into the sidewall and interfering with the adjacent TSVs, and can effectively improve the degradation of TSV isolation performance caused by deep hole etching and increase the yield.
As an example, referring to fig. 3, a semiconductor structure is provided in an embodiment of the present disclosure, including a substrate 10, a metal pad 11, a through-silicon via structure 12, and an isolation ring structure 13; the substrate 10 has a first surface 10a and a second surface 10b opposite to each other; the metal pad 11 is located on the side of the second surface 10b facing away from the substrate 10; the through-silicon via structure 12 penetrates the substrate 10 in the thickness direction via the first surface 10a and is in contact connection with the metal pad 11; the orthographic projection of the metal pad 11 on the second surface 10b covers the bottom surface of the through silicon via structure 12; the isolation ring structure 13 is formed in the substrate 10 and surrounds the through silicon via structure 12, wherein the inner sidewall and the outer sidewall of the isolation ring structure 13 have a predetermined distance.
In the above embodiment, the metal pad 11 is located on the second surface 10b of the substrate 10 and is away from the side of the substrate 10, and the isolation ring structure 13 is disposed in the region surrounding the through silicon via structure 12, and etching is performed by using an etching material with very high energy in the process of forming the through silicon via structure 12 with a high aspect ratio by the TSV etching process, when the etching process is performed on the substrate 10 to form the through silicon via, the etching material with high energy bombards the metal pad 11 when the bottom of the substrate 10 approaches to the upper surface of the metal pad 11, the metal material in the metal pad 11 splashes to the side wall of the etching hole, and then the material in the metal pad 11 diffuses into the side wall and the substrate 10, but due to the arrangement of the isolation ring structure 13, the material in the metal pad 11 does not appear on the side of the isolation ring structure 13 away from the through silicon via structure 12, i.e. does not diffuse deep into the substrate 10, thereby avoiding the condition that adjacent through silicon vias are connected due to gradual diffusion of metal in the inside the substrate 10 during or even after the process of etching the through silicon via structure 12 is completed, and the performance of the through silicon via structure 12 is improved. In the conventional art, energy of etching materials is generally reinforced for deep hole etching with high depth-to-width ratio, so that bombardment is inevitably generated on the bottom metal pad 11, and therefore, adjacent through silicon via isolation performance is reduced due to sputtering to the side wall of a hole and gradual diffusion, and the risk of conduction exists.
As an example, the substrate may be formed using a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 10 may have a single-layer structure or a multilayer structure. For example, the substrate 10 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, and also for example, the substrate 10 may be a layered substrate comprising a material such as Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Those skilled in the art may select a substrate type according to a transistor type formed on the substrate 10, and thus the type of the substrate 10 should not limit the scope of the present disclosure.
As an example, referring to fig. 3, the isolation ring structure 13 penetrates the substrate 10 through the first surface 10a and extends to the second surface 10b along the thickness direction, so as to prevent the metal material in the metal pad 11 from being present on the side of the isolation ring structure 13 away from the through-silicon via structure 12, i.e. the metal material in the metal pad 11 does not diffuse deep into the substrate 10, so that the situation that adjacent through-silicon vias are connected due to gradual diffusion of metal inside the substrate 10 is avoided.
As an example, with continued reference to fig. 3, an isolation protection layer 14 is included between the inner sidewall of the isolation ring structure 13 and the outer sidewall of the through-silicon via structure 12. The isolation protection layer 14 includes an insulating material, and specifically, the material of the isolation protection layer 14 may be silicon dioxide (SiO 2 )。
As an example, the semiconductor structure further comprises a ring-shaped barrier layer 15; the annular barrier 15 surrounds the through-silicon via structure 12 and is located between the isolation protection layer 14 and the through-silicon via structure 12. The annular barrier 15 penetrates the substrate 10 in the thickness direction via the first surface 10a and extends to the metal pad 11.
As an example, the minimum distance between the inner sidewall of the isolation ring structure 13 and the outer sidewall of the through silicon via structure 12 is greater than or equal to 1 μm. For example, the minimum distance between the inner sidewall of the isolation ring structure 13 and the outer sidewall of the through silicon via structure 12 may be 1 μm, 1.5 μm, 2 μm, 3 μm, or the like.
As an example, the minimum distance between the outer side walls of adjacent insulating ring structures 13 is greater than or equal to 1 μm. For example, the minimum distance between the outer sidewalls of adjacent insulating ring structures 13 may be 1 μm, 1.5 μm, 2 μm or 2.5 μm, etc.
As an example, the preset distance is 2 μm-10 μm. For example, the preset distance may be 2 μm, 3 μm, 6 μm, 10 μm, or the like.
As an example, referring to fig. 8, in fig. 8, the material of the isolation ring structure 13 includes a first low-k material layer 131, a metal barrier layer 132 and a second low-k material layer 133, wherein the first low-k material layer 131 is located in the substrate 10 and surrounds the through-silicon via structure 12, the metal barrier layer 132 surrounds the first low-k material layer 131, and the second low-k material layer 133 surrounds the metal barrier layer 132. The first low-k material layer 131 may include fluorine-doped silicon dioxide (SiOF), carbon-doped silicon dioxide (SiOC), fluorocarbon (a-C: F), etc., the metal barrier layer 132 may include at least one of tantalum (Ta), tantalum nitride (TaN), and titanium nitride (Ti), and the second low-k material layer 133 may include fluorine-doped silicon dioxide (SiOF), carbon-doped silicon dioxide (SiOC), fluorocarbon (a-C: F), etc. For example, the material of the first low-k material layer 131 and the second low-k material layer 133 may be carbon-doped silicon dioxide, and the material of the metal barrier layer 132 may be tantalum nitride. In the semiconductor device, parasitic capacitance inevitably exists between the filling material in the through silicon via structure 12 and the metal barrier layer 132, the parasitic capacitance not only affects the speed of the chip, but also forms a serious threat to the operation reliability, and since the capacitance can be reduced by reducing the dielectric constant value of the dielectric medium, when the metal barrier layer 132 is adopted as the isolation ring structure 13, the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133 are formed on the inner wall and the outer wall of the isolation ring structure 13, so that the parasitic capacitance between the through silicon via structure 12 and the isolation ring structure 13 can be effectively reduced, and the overall performance of the semiconductor product can be improved.
As an example, referring to fig. 8, the thickness of the metal barrier layer 132 may be smaller than the sum of the thicknesses of the first low-k material layer 131 and the second low-k material layer 133, so as to ensure the isolation performance and the metal barrier performance of the isolation ring structure 13.
As an example, with continued reference to fig. 8, the thickness of the metal barrier layer 132 may be 1/3-2/3 of the sum of the thicknesses of the first low-k material layer 131 and the second low-k material layer 133. For example, the thickness of the metal barrier layer 132 may be 1/3, 0.5, 0.55, 2/3, or the like of the sum of the thicknesses of the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133. The thickness of the metal barrier layer 132 should not be too thin to effectively avoid the sputtering and diffusion of etching appendages during the fabrication of the through-silicon via structure from interfering with adjacent semiconductor structures or electronic components; the thickness of the metal barrier layer 132 should not be too thick, so as to avoid the problem of increasing parasitic capacitance caused by relatively reducing the thickness of the first low-k material layer 131 or the thickness of the second low-k material layer 133.
As an example, with continued reference to fig. 3 and 8, the material of the annular barrier 15 includes at least one of tantalum, tantalum nitride and titanium nitride; the material of the isolation protection layer 14 includes an insulating material and/or a low dielectric constant material, and specifically, the material of the isolation protection layer 14 may be silicon dioxide.
As an example, referring to fig. 4, fig. 4 is a schematic top view of the semiconductor structure in the above embodiment, that is, a cross-sectional view along the AA' direction in fig. 3, the annular barrier 15, the isolation protection layer 14 and the isolation ring structure 13 are concentric rings and have the same center with the through-silicon via structure 12, and the annular barrier 15, the isolation protection layer 14, the isolation ring structure 13 and the through-silicon via structure 12 penetrate through the substrate 10 along the thickness direction, wherein the predetermined distance is 2 μm-10 μm, and the minimum distance between the inner sidewall of the isolation ring structure 13 and the outer sidewall of the through-silicon via structure 12 is greater than or equal to 1 μm. The structure can avoid metal sputtering diffusion caused by etching to the metal pad 11 into the deep of the substrate 10 in the process of etching the through silicon via structure 12, so that the communication of the adjacent through silicon via structures 12 is caused, and the isolation performance of the through silicon via structure 12 can be improved.
As an example, referring to fig. 5, a method for manufacturing a semiconductor structure is further provided in an embodiment of the disclosure, including the following steps:
step S10: providing a substrate with a first surface and a second surface which are opposite to each other, and forming a metal pad on one side of the second surface, which is away from the substrate;
step S20: forming an isolation ring structure in the substrate, wherein a preset distance is reserved between the inner side wall and the outer side wall of the isolation ring structure;
Step S30: forming a through silicon via structure in the substrate in the isolation ring structure, wherein the through silicon via structure penetrates through the substrate along the thickness direction through the first surface and is in contact connection with the metal pad; the orthographic projection of the metal pad on the second surface covers the bottom surface of the through silicon via structure.
In step S10, referring to step S10 in fig. 3 and 5, a substrate 10 having a first surface 10a and a second surface 10b opposite to each other is provided, and a metal pad 11 is formed on the second surface 10 b.
As an example, step S10 may further include the steps of: the substrate 10 is thinned to a predetermined thickness, and the thinning method may include grinding processing including various processing steps such as rough grinding, fine grinding, and polishing, for example, the thickness of the thinned substrate 10 is 100 μm or less. After the substrate 10 is thinned to a preset thickness, performing rapid wet etching on the surface of the substrate 10, and eliminating the stress on the substrate 10 through isotropy of the wet etching; since the thinned back surface of the substrate 10 has a surface damaged layer, the residual stress thereof may cause the thinned epitaxial wafer to bend and be easily broken in the subsequent process, thereby affecting the yield. The back surface of the substrate 10 may be polished after thinning, and in particular, the polishing process technique may employ a chemical mechanical polishing technique (Chemical Mechanical Polishing, CMP).
In step S20, referring to step S20 in fig. 3 and 5, an isolation ring structure 13 is formed in the substrate 10, and a predetermined distance is provided between an inner sidewall and an outer sidewall of the isolation ring structure 13. Since the material of the isolation ring structure 13 is selected to be a material capable of blocking metal in the metal pad, when etching causes etching attachment, that is, when the metal material in the metal pad splashes during the subsequent formation of the through-silicon via structure 12, the splashing etching attachment is prevented from diffusing into one side of the isolation ring structure 13 away from the through-silicon via structure 12 in the width direction, so that the interconnection of the adjacent through-silicon via structures 12 is prevented; and can avoid the sputtering and diffusion of etching accessories to generate interference to adjacent semiconductor structures or electronic elements, and improve the performance and reliability of the prepared semiconductor products.
In step S30, referring to step S30 in fig. 3 and 5, a through-silicon via structure 12 is formed in the substrate 10 in the isolation ring structure 13, and the through-silicon via structure 12 penetrates the substrate 10 through the first surface 10a in the thickness direction and is in contact connection with the metal pad 11; the metal pad 11 covers the bottom surface of the through-silicon via structure 12 in the orthographic projection of the second surface 10 b. Since the isolation ring structure 13 is formed before the through-silicon via structure 12, during the process of forming the through-silicon via structure 12, when the etching of the through-silicon via structure by the high-energy etching material is about to end, the metal pad 11 contacted with the through-silicon via structure 12 is bombarded to the metal sputtering, and at this time, the metal sputtering is stopped at the side wall and the position of diffusing to the isolation ring structure 13, and does not diffuse into the substrate 10, i.e. the phenomenon that the adjacent through-silicon via structures 12 are communicated does not occur.
In the above embodiment, the metal pad 11 is formed on the side of the second surface 10b of the substrate 10 away from the substrate 10, and the isolation ring structure 13 is formed before the formation of the through silicon via structure 12, and the isolation ring structure 13 surrounds the through silicon via structure 12 to be formed subsequently, when the through silicon via structure 12 is formed in the substrate 10, high-energy etching needs to be performed on the substrate 10, when the etching is close to the upper surface of the metal pad 11, the metal pad 11 is inevitably etched, so that the metal material in the metal pad 11 is sputtered onto the side wall of the etching hole and gradually diffuses, and because the isolation ring structure 13 is already formed before the etching hole, the metal material sputtered onto the side wall stops the diffusion movement when diffusing and contacting the isolation ring structure 13, and does not appear on the side of the isolation ring structure 13 away from the through silicon via structure 12 in the width direction, so that the sputtered metal material does not diffuse to the deep of the substrate 10 to communicate with the adjacent through silicon via structure 12, the risk of conducting between different through silicon via structures 12 is avoided, the performance of the through silicon via structure 12 is improved, and the yield of semiconductor is improved.
As an example, referring to fig. 6, a first dielectric layer is formed between the metal pad and the second surface; the step of forming an isolation ring structure in a substrate includes:
Step S21: forming a second dielectric layer on the first surface of the substrate;
step S22: etching the second dielectric layer and the substrate to obtain an isolation ring gap, wherein part of the first dielectric layer is exposed out of the isolation ring gap;
step S23: forming a first low-dielectric-constant material layer, a metal barrier layer and a second low-dielectric-constant material layer in the isolation ring gap to obtain an isolation ring structure.
In step S21, referring to step S21 in fig. 8 and 6, a second dielectric layer 17 is formed on the first surface 10a of the substrate 10. The second dielectric layer 17 may be formed using a rapid thermal oxidation process (Rapid Thermal Oxidation, RTO).
In step S22, referring to step S22 in fig. 8 and fig. 6, a dry etching process may be used to etch the second dielectric layer 17 and the substrate 10, so as to obtain an isolation ring gap, where a portion of the first dielectric layer is exposed by the isolation ring gap. The etching process may include, but is not limited to, a dry etching process and/or a wet etching process. The dry etching process may include, but is not limited to, one or more of Reactive Ion Etching (RIE), inductively coupled plasma etching (ICP), high-concentration plasma etching (HDP), and the like.
In step S23, referring to step S23 of fig. 8 and 6, an initial low-k material layer is deposited on the inner wall and the bottom of the isolation ring gap, and the deposition process may include any one or more of physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD) and atomic layer deposition (Atomic Layer Deposition, ALD), and the portion of the initial low-k material layer at the bottom of the isolation ring gap is etched and removed to expose the first dielectric layer 16, thereby forming a first low-k material layer 131 surrounding the through-silicon via structure 12 and a second low-k material layer 133 surrounding the first low-k material layer 131; then, a metal barrier layer 132 is formed in the gap between the first low-k material layer 131 and the second low-k material layer 133. The process of forming the metal barrier layer 132 may include any one or more of CVD, PVD, and ALD processes.
As an example, referring to fig. 8, the isolation ring structure 13 includes a first low-k material layer 131, a metal barrier layer 132, and a second low-k material layer 133, wherein the first low-k material layer 131 is disposed in the substrate 10 and surrounds the through-silicon via structure 12, the metal barrier layer 132 surrounds the first low-k material layer 131, and the second low-k material layer 133 surrounds the metal barrier layer 132. When the metal barrier layer 132 is used as the isolation ring structure 13, the first low-k material layer 131 and the second low-k material layer 133 are formed on the inner wall and the outer wall of the isolation ring structure 13, so that parasitic capacitance between the through-silicon via structure 12 and the isolation ring structure 13 can be effectively reduced, and overall performance of the semiconductor device can be improved.
As an example, referring to fig. 7, the step of forming a through silicon via structure in a substrate within an isolation ring structure includes:
step S31: etching the second dielectric layer and the substrate in the isolation ring structure to obtain a through hole, wherein part of the metal pad is exposed out of the through hole;
step S32: forming an isolation protection layer on the side wall of the through hole;
step S33: depositing an annular barrier layer on the side wall of the isolation protection layer; step S34: and filling the conductive material layer in the through hole, and carrying out planarization treatment to obtain the silicon through hole structure.
In step S31, referring to step S31 in fig. 8 and fig. 7, the second dielectric layer 17 and the substrate 10 in the isolation ring structure 13 are etched to obtain a via hole exposing a portion of the metal pad 11. Specifically, the process of etching the via hole may employ a Plasma (Plasma) etching technique.
As an example, before step S31, and after step S23, the following steps may be further included: spin-coating photoresist on the first surface 10b of the substrate 10, and forming a pattern opening through a photolithography process; the photoresist is removed after the end of step S31.
In step S32, referring to step S32 in fig. 8 and fig. 7, an isolation protection layer 14 is formed on the sidewall of the via hole. The isolation protective layer 14 may be formed by rapid thermal oxidation (Rapid Thermal Oxidation, RTO), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or sub-atmospheric chemical vapor deposition (Selected Area Chemical Vapor Deposition, SACVD).
In step S33, please refer to step S33 in fig. 8 and fig. 7, a ring-shaped barrier layer 15 is deposited on the sidewall of the isolation protection layer 14. The annular barrier 15 may be formed by a physical vapor deposition process (Physical Vapor Deposition, PVD). Generally, in the TSV process, an electroplating process is used to fill the through hole, for example, an electroplated copper process is used to fill the through hole, but the diffusion speed of copper in the isolation protection layer is high, so that the dielectric property of copper is easily seriously degraded, and copper has a very strong trap effect on the carrier of the semiconductor, so that when copper diffuses into the semiconductor bulk material, the electrical characteristics of the semiconductor device are seriously affected, and the adhesion strength between copper and the isolation protection layer 14 is poor. Therefore, the annular barrier layer 15 is deposited between the through-silicon via structure 12 and the isolation protection layer 14, which can prevent the diffusion of the conductive material layer filled in the through-silicon via structure 12 formed later and can improve the performance of the semiconductor device.
In step S34, referring to step S34 in fig. 8 and 7, a conductive material layer is filled in the via hole, and the planarization process is performed to obtain the through-silicon via structure 12.
As an example, the method of filling the conductive material layer may employ an electroplating method, and the step of filling the conductive material layer in the via hole and planarizing in step S34 may include: firstly, air in the cavity is exhausted in a physical mode, for example, electroplating liquid smoothly enters the cavity in an ultrasonic mode, a spraying mode, a vacuumizing mode and the like; secondly, filling the conductive material layer by adopting an electrolytic copper plating process, wherein the electrolytic copper plating process comprises degreasing, microetching, pickling, plating the conductive material and the like, the degreasing comprises removing greasy dirt and fingerprints on a plate surface, the microetching comprises cleaning a roughened copper surface, removing plate surface oxides and impurities, the pickling comprises removing an oxide film on the surface of a metal pad 11 and activating the surface of the metal pad 11, impurities can be reduced, and the copper plating comprises depositing the conductive material layer on the surface of the metal pad 11 and in holes by adopting a direct current electroplating method; after electroplating, since excessive internal stress is accumulated in the electroplated conductive material layer, a plurality of protrusion defects can be generated, and a low-temperature annealing process can be adopted to inhibit the generation of the protrusion defects; in addition, after the low temperature annealing process, the through-silicon via structure 12 may be planarized, where any one or more of a CMP process, a dry etching process, a horizontal pushing process, and the like may be used for the planarization process.
It should be understood that, although the steps in the flowcharts of fig. 5-7 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, although at least a portion of the steps of fig. 5-7 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the steps or stages are performed is not necessarily sequential, and may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or steps.
As an example, the minimum distance between the inner sidewall of the isolation ring structure 13 and the outer sidewall of the through-silicon via structure 12 is greater than or equal to 1 μm, for example, the minimum distance between the inner sidewall of the isolation ring structure 13 and the outer sidewall of the through-silicon via structure 12 may be 1 μm, 1.5 μm, 2 μm, 3 μm, or the like.
As an example, the minimum distance between the outer side walls of adjacent insulating ring structures 13 is greater than or equal to 1 μm, e.g., the minimum distance between the outer side walls of adjacent insulating ring structures 13 may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, etc.
As an example, the preset distance is 2 μm-10 μm, for example, the preset distance may be 2 μm, 3 μm, 6 μm, 10 μm, or the like.
As an example, the method of forming the semiconductor structure may be combined with a conventional semiconductor device forming process, for example, a semiconductor device (not shown), such as a Metal Oxide Semiconductor (MOS) transistor (metal oxide semiconductor transistor) or a dynamic random access memory (Dynamic Random Access Memory, DRAM), may be formed on the substrate 10, and then the isolation ring structure 13 and the through-silicon via structure 12 may be formed by the steps of the present disclosure.
In the semiconductor structure and the method for manufacturing the same described in the above embodiments, first, a substrate is provided, and a metal pad is formed on a side of a second surface of the substrate facing away from the substrate; then, forming an isolation ring structure in the substrate, wherein a preset distance is reserved between the inner side wall and the outer side wall of the isolation ring structure; and then, forming a through silicon via structure in the substrate in the isolation ring structure, wherein the through silicon via structure penetrates through the substrate along the thickness direction through the first surface and is in contact connection with the metal pad. In the process of etching the through silicon via structure, as the metal pad covers the bottom surface of the through silicon via structure through orthographic projection on the second surface, the metal pad is etched when the etching process is carried out to a position close to the metal pad, so that metal materials in the metal pad are sputtered into the side wall of the through silicon via structure.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples represent only a few embodiments of the present disclosure, which are described in more detail and detail, but are not to be construed as limiting the scope of the disclosure. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.
Claims (15)
1. A semiconductor structure, comprising:
A substrate having a first surface and a second surface opposite to each other;
a metal pad located on a side of the second surface facing away from the substrate;
a through silicon via structure penetrating through the substrate in the thickness direction via the first surface and being in contact connection with the metal pad; orthographic projection of the metal pad on the second surface covers the bottom surface of the through silicon via structure;
and the isolation ring structure is formed in the substrate and surrounds the through silicon via structure, wherein the inner side wall and the outer side wall of the isolation ring structure have a preset distance.
2. The semiconductor structure of claim 1, wherein the isolation ring structure extends through the substrate in the thickness direction via the first surface and to the second surface.
3. The semiconductor structure of claim 2, wherein an isolation protection layer is included between an inner sidewall of the isolation ring structure and an outer sidewall of the through silicon via structure.
4. The semiconductor structure of claim 3, wherein the isolation protection layer comprises an insulating material.
5. The semiconductor structure of claim 4, further comprising:
and the annular blocking layer surrounds the through silicon via structure and is positioned between the isolation protection layer and the through silicon via structure.
6. The semiconductor structure of claim 5, wherein the annular barrier extends through the substrate in a thickness direction through the first surface and to the metal pad.
7. The semiconductor structure of any of claims 3-6, wherein a minimum distance between an inner sidewall of the isolation ring structure and an outer sidewall of the through silicon via structure is greater than or equal to 1 μιη.
8. The semiconductor structure of any of claims 1-6, wherein a minimum distance between outer sidewalls of adjacent isolation ring structures is greater than or equal to 1 μιη.
9. The semiconductor structure of any of claims 1-6, wherein the predetermined distance is 2 μιη to 10 μιη.
10. The semiconductor structure of any of claims 1-3, wherein the isolation ring structure comprises a first low dielectric constant material layer, a metal barrier layer, and a second low dielectric constant material layer, wherein the first low dielectric constant material layer surrounds the through silicon via structure, the metal barrier layer surrounds the first low dielectric constant material layer, and the second low dielectric constant material layer surrounds the metal barrier layer.
11. The semiconductor structure of claim 5 or 6, wherein the annular barrier material comprises at least one of tantalum, tantalum nitride, and titanium nitride.
12. A method of fabricating a semiconductor structure, comprising:
providing a substrate with a first surface and a second surface which are opposite to each other, and forming a metal pad on one side of the second surface, which is away from the substrate;
forming an isolation ring structure in the substrate, wherein a preset distance is reserved between the inner side wall and the outer side wall of the isolation ring structure;
forming a through silicon via structure in the substrate in the isolation ring structure, wherein the through silicon via structure penetrates through the substrate along the thickness direction through the first surface and is in contact connection with the metal pad; and orthographic projection of the metal pad on the second surface covers the bottom surface of the through silicon via structure.
13. The method of manufacturing according to claim 12, wherein a first dielectric layer is formed between the metal pad and the second surface; the isolation ring structure comprises a first low-dielectric-constant material layer, a metal barrier layer and a second low-dielectric-constant material layer, wherein the first low-dielectric-constant material layer surrounds the through silicon via structure, the metal barrier layer surrounds the first low-dielectric-constant material layer, and the second low-dielectric-constant material layer surrounds the metal barrier layer; the step of forming an isolation ring structure within the substrate comprises:
Forming a second dielectric layer on the first surface of the substrate;
etching the second dielectric layer and the substrate to obtain an isolation ring gap, wherein part of the first dielectric layer is exposed out of the isolation ring gap;
and forming the first low-dielectric-constant material layer, the metal barrier layer and the second low-dielectric-constant material layer in the isolation ring gap to obtain the isolation ring structure.
14. The method of claim 13, wherein the step of forming a through silicon via structure in the substrate within the isolation ring structure comprises:
etching the second dielectric layer and the substrate in the isolation ring structure to obtain a through hole, wherein part of the metal pad is exposed out of the through hole;
forming an isolation protection layer on the side wall of the through hole;
depositing an annular barrier layer on the side wall of the isolation protection layer;
and filling a conductive material layer in the through hole, and carrying out planarization treatment to obtain the silicon through hole structure.
15. The method of any one of claims 12-14, further comprising at least one of the following features:
the minimum distance between the inner side wall of the isolation ring structure and the outer side wall of the through silicon via structure is larger than or equal to 1 mu m;
The minimum distance between the outer side walls of adjacent isolation ring structures is greater than or equal to 1 μm;
the preset distance is 2-10 mu m.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210901242.2A CN117525031A (en) | 2022-07-28 | 2022-07-28 | Semiconductor structure and preparation method thereof |
| PCT/CN2023/089000 WO2024021693A1 (en) | 2022-07-28 | 2023-04-18 | Semiconductor structure and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210901242.2A CN117525031A (en) | 2022-07-28 | 2022-07-28 | Semiconductor structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117525031A true CN117525031A (en) | 2024-02-06 |
Family
ID=89705200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210901242.2A Pending CN117525031A (en) | 2022-07-28 | 2022-07-28 | Semiconductor structure and preparation method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN117525031A (en) |
| WO (1) | WO2024021693A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118471932B (en) * | 2024-07-09 | 2024-10-01 | 武汉新芯集成电路股份有限公司 | Semiconductor device and method for manufacturing the same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101789390A (en) * | 2009-01-23 | 2010-07-28 | 财团法人工业技术研究院 | Method for manufacturing silicon through hole and silicon through hole structure |
| CN102623437B (en) * | 2012-04-06 | 2017-05-31 | 上海集成电路研发中心有限公司 | Through-silicon via structure and its manufacture method |
| CN108538811A (en) * | 2018-03-20 | 2018-09-14 | 杭州电子科技大学 | With the low stopping area differential transfer structure and its interlayer interconnection structure of silicon hole |
| WO2020052630A1 (en) * | 2018-09-14 | 2020-03-19 | Changxin Memory Technologies, Inc. | Semiconductor device and methods for manufacturing thereof |
| CN111769097B (en) * | 2020-06-18 | 2022-11-18 | 复旦大学 | Silicon through hole structure for three-dimensional interconnection and manufacturing method thereof |
-
2022
- 2022-07-28 CN CN202210901242.2A patent/CN117525031A/en active Pending
-
2023
- 2023-04-18 WO PCT/CN2023/089000 patent/WO2024021693A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024021693A1 (en) | 2024-02-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11545392B2 (en) | Semiconductor component having through-silicon vias | |
| US11596800B2 (en) | Interconnect structure and method of forming same | |
| US12381195B2 (en) | Semiconductor devices and methods of manufacture thereof | |
| US7626257B2 (en) | Semiconductor devices and methods of manufacture thereof | |
| US9064849B2 (en) | 3D integrated circuit structure, semiconductor device and method of manufacturing same | |
| US10361234B2 (en) | 3DIC interconnect apparatus and method | |
| US8796852B2 (en) | 3D integrated circuit structure and method for manufacturing the same | |
| US8822329B2 (en) | Method for making conductive interconnects | |
| US20080113505A1 (en) | Method of forming a through-substrate via | |
| TW201605012A (en) | Stacked integrated circuits with redistribution lines | |
| JP2010157741A (en) | Through silicon via with scalloped sidewall | |
| CN116072547B (en) | Semiconductor structure and forming method thereof, and wafer bonding method | |
| CN107305840B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| US12322654B2 (en) | Semiconductor structure, method for forming same, and wafer on wafer bonding method | |
| CN117525031A (en) | Semiconductor structure and preparation method thereof | |
| US11776848B2 (en) | Semiconductor device and methods for manufacturing thereof | |
| US10811382B1 (en) | Method of manufacturing semiconductor device | |
| JP2025504616A (en) | Semiconductor structure having embedded power interconnects - Patents.com | |
| US20240395728A1 (en) | Semiconductor devices and methods of manufacture | |
| US20230201613A1 (en) | Interconnect Structure and Method of Forming Same | |
| CN119153398A (en) | Semiconductor structure, forming method and related device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |