CN117597016A - Variable resistance memory device and electronic apparatus including the same - Google Patents

Abstract

A variable resistance memory device and/or an electronic apparatus including the same are provided. The variable resistance memory device includes: a resistance-changing layer comprising a metal oxide having an oxygen deficiency of greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of gate electrodes spaced apart from each other on the gate insulating layer.

Description

Variable resistance memory device and electronic equipment including the same

Cross-references to related applications

This application is based on Korean Patent Application No. 10-2022-0104269 filed with the Korean Intellectual Property Office on August 19, 2022 and Korean Patent Application No. 10-2022-0153995 filed with the Korean Intellectual Property Office on November 16, 2022. , and claims the right of priority, the entire disclosure content of which is incorporated herein by reference.

Technical field

Various example embodiments relate to memory devices including variable resistance materials and/or electronic devices including the memory devices.

Background technique

The nonvolatile memory device includes a plurality of memory cells that retain data even when power is interrupted or stopped, and therefore, the stored data can be used again when power is supplied. Non-volatile memory devices may be used in one or more of: cell phones, digital cameras, portable digital assistants (PDAs), mobile computing devices, stationary computing devices, and other devices.

Recently, research has been conducted on the use of three-dimensional (or vertical) NAND (or VNAND) structures in chips used to form next-generation neuromorphic computing platforms or neural networks.

Contents of the invention

A variable resistance memory device including a resistance change layer that may include a plurality of oxygen vacancies and/or an electronic device including the variable resistance memory device is provided.

Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the variously described example embodiments.

According to various example embodiments, a variable resistance memory device includes a resistance change layer including a metal oxide including a first metal element and optionally a second metal element, the metal oxide having a thickness greater than or an oxygen deficiency rate (oxygen deficiency ratio) equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer (gate insulating layer) on the semiconductor layer; and on the gate insulating layer A plurality of gate electrodes on the layer and spaced apart from each other.

The content of the first metal element may be greater than or equal to about 50 atomic % relative to the total metal of the resistance change layer.

The content of the second metal element may be less than or equal to about 35 atomic % relative to the total metal of the resistance change layer.

The first metal element may include at least one of Ta, Ti, Sn, Cr, and Mn.

The second metal element may include at least one of Hf, Al, Nb, La, Zr, Sc, W, V, and Mo.

The variable resistance change layer may further include Si.

The semiconductor layer may be configured to receive a write voltage applied thereto having an absolute value less than or equal to about 4V.

The variable resistance memory device may further include an oxide layer between the semiconductor layer and the resistance change layer.

The thickness of the oxide layer may be smaller than the thickness of the resistance change layer.

The variable resistance change layer may include a first resistance change layer and a second resistance change layer sequentially arranged in a direction away from the semiconductor layer, and the oxygen deficiency rate of the first resistance change layer may be greater than the Oxygen deficiency rate of the second resistance change layer.

At least three of the plurality of gate electrodes may be periodically arranged, and a pitch of the at least three of the plurality of gate electrodes may be less than or equal to about 20 nm.

The variable resistance memory device may further include a pillar, wherein the resistance change layer, the semiconductor layer, and the gate insulating layer may sequentially surround the pillar in a shell shape, and the plurality of gate electrodes and the insulating elements may be in a shell shape. surrounding the gate insulating layer.

The posts may include insulating material.

The pillars may include electrically conductive material.

The pillar may be configured to receive a voltage greater than or equal to the voltage applied to the semiconductor layer.

According to various example embodiments, a variable resistance memory device includes: a resistance change layer including a metal oxide including silicon having an oxygen deficiency rate greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of gate electrodes spaced apart from each other on the gate insulating layer.

The variable resistance change layer may include at least one of Ta, Ti, Sn, Cr, and Mn.

The content of silicon may be less than or equal to about 35 atomic % relative to the sum of metal and silicon of the resistance change layer.

According to various example embodiments, a variable resistance memory device includes a resistance change layer and includes a first metal oxide having an oxygen deficiency rate greater than or equal to about 9% and a second metal having an oxygen deficiency rate less than 9%. an oxide, wherein the content of the first metal oxide is greater than the content of the second metal oxide; a semiconductor layer disposed on the resistance change layer; a gate insulating layer disposed on the semiconductor layer; and A plurality of gate electrodes are arranged spaced apart from each other on the gate insulating layer.

The content of the metal included in the second metal oxide may be less than or equal to about 35 atomic % relative to the total metal included in the resistance change layer.

Description of drawings

These and/or other aspects will become apparent and better understood from the following description of various example embodiments, considered in conjunction with the accompanying drawings, in which:

1 is a diagram showing a schematic structure of a variable resistance memory device according to various example embodiments;

Figure 2 is a circuit diagram such as an equivalent circuit diagram of the variable resistance memory device of Figure 1;

FIG. 3 is a conceptual diagram of an example of operation of the variable resistance memory device of FIG. 1;

4 is a graph showing the relationship between oxygen deficiency rate and formation voltage of metal oxides according to various example embodiments;

5 is a graph showing the relationship between oxygen deficiency rate and formation voltage of metal oxides according to various example embodiments;

6 is a graph showing the relationship between oxygen formation energy and oxygen deficiency rate of metal oxides according to various example embodiments;

7 is a graph showing differences in oxygen formation energies between various metal oxides according to various example embodiments;

8A is a diagram showing characteristic IV of a variable resistance memory device using hafnium oxide as a resistance change layer;

8B is a diagram showing characteristic IV of a variable resistance memory device using tantalum oxide as a resistance change layer;

9 is a structural diagram of a variable resistance memory device according to various example embodiments;

Figure 10 is a circuit diagram such as an equivalent circuit diagram of the variable resistance memory device of Figure 9;

11 is a diagram showing a portion of a variable resistance memory device including a plurality of resistance change layers in accordance with various example embodiments;

12 is a diagram showing a portion of a variable resistance memory device further including an oxide layer, in accordance with various example embodiments;

13 is a diagram of a variable resistance memory device including conductive pillars, according to various example embodiments;

14 is a schematic block diagram of an electronic device including a variable resistance memory device according to various example embodiments;

15 is a schematic block diagram of a memory system including a variable resistance memory device, according to various example embodiments; and

Figure 16 is a schematic diagram of a neuromorphic device including a memory device, according to various example embodiments.

Detailed ways

Various embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, example embodiments are described below merely to illustrate aspects, by referring to the drawings. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of" when preceding or following a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

Phrases such as “in some embodiments,” “according to various example embodiments,” etc., described in various sections of this specification do not necessarily refer to the same elements as each other.

One or more example implementations may be described as functional block components and various processing operations. All or part of such functional blocks may be implemented by any number of hardware and/or software components configured to perform the illustrated functions. For example, the functional blocks of the disclosure may be implemented in one or more microprocessors or in a circuit structure for certain functions. Additionally, for example, the functional blocks of the disclosure may be implemented in a variety of programming or scripting languages. Functional blocks may be implemented by algorithms executed by one or more processors. Additionally, the disclosure may employ conventional techniques for electronic device configuration, signal processing, and/or data control. Terms such as "mechanism," "element," "component," etc. are not limited to mechanical and physical components.

Furthermore, the connecting lines or connections shown in the figures are intended to represent example functional relationships and/or physical or logical couplings between various elements. It should be noted that many alternative or additional functional relationships, physical connections, or logical connections may exist in an actual device.

Terms such as "comprises" or "includes" used in this specification should not be construed as requiring that all of the various components or various operations described in the specification are included. Rather, it will be understood that some components or operations may be excluded, or additional components or operations may be further included.

In the following text, it will be understood that when an element is referred to as being "on" or "above" another element, it can be directly above or below or to the right or left side of the further element, or between Intermediate elements may also be present. Hereinafter, various example implementations will be described in detail with reference to the accompanying drawings.

Although terms such as "first," "second," etc. may be used herein to describe various elements, these terms do not limit the elements. These terms are only used to distinguish one element from another.

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing a schematic structure of a variable resistance memory device 100 according to various example embodiments, FIG. 2 is a circuit diagram of the variable resistance memory device 100 of FIG. 1 , and FIG. 3 is a diagram showing the variable resistance memory device 100 of FIG. 1 An example conceptual diagram of the operation of memory device 100.

Referring to FIG. 1 , the variable resistance memory device 100 may include a resistance change layer 122 , a semiconductor layer 123 disposed on the resistance change layer 122 , a gate insulating layer 124 disposed on the semiconductor layer 123 , and a gate insulating layer 124 disposed on the semiconductor layer 123 . a plurality of gate electrodes 131 on. An insulating element 132 for insulating the plurality of gate electrodes 131 adjacent to each other may be further disposed between the plurality of gate electrodes 131 . However, this is only an example, and the insulating element 132 may be omitted.

The resistance change layer 122 may include a material having resistance that changes according to applied voltage. The resistance change layer 122 may change from a high resistance state to a low resistance state or from a low resistance state to a high resistance state according to one or more voltages applied to the gate electrode 131 .

The resistance change layer 122 may have a smaller thickness to achieve a desired variation range than other variable resistance memory devices using phase change materials and/or additional charge trapping based variable resistance memory devices. The thickness of the resistance change layer 122 may be less than or equal to 100 nm or less than or equal to 5 nm. The thickness of the resistance change layer 122 may be greater than or equal to 1 nm.

The resistance change layer 122 may include a material having hysteresis characteristics. For example, the resistance change layer 122 may include metal oxide. The resistance change layer 122 may include at least two of the following: TaOx, TiOx, SnOx, CrOx, MnOx, HfOx, AlOx, SiOx, NbOx, LaOx, ZrOx, ScOx, WOx, VOx, and MoOx.

In some example implementations, the resistance change of resistance change layer 122 may be a phenomenon due to oxygen vacancies. When there are many oxygen vacancies in the resistance change layer 122, for example, conductive threads can be easily formed. The conductive filaments can cause the resistance change layer 122 to change to a low resistance state such that current can flow through the resistance change layer 122 and, therefore, the variable resistance memory device 100 can operate, for example, to store logic data such as logic "0" or logic "1". When the resistance change layer 122 includes a material in which oxygen vacancies can be easily formed, the variable resistance memory device 100 can operate well, for example, even when the absolute value of the voltage applied to the resistance change layer 122 or the semiconductor layer 123 decreases. . Materials of the resistance change layer 122 in which oxygen vacancies can be formed more easily will be described below.

The semiconductor layer 123 may include polycrystalline Si or polycrystalline silicon such as doped or undoped polycrystalline silicon. The material of the semiconductor layer 123 is not limited to polycrystalline Si. For example, one or more of various semiconductor materials such as Ge, IGZO (Indium Gallium Zinc Oxide), GaAs, etc. may alternatively or additionally be included in the semiconductor layer 123 .

The source electrode S and the drain electrode D may be connected to both ends of the semiconductor layer 123 respectively.

Gate insulating layer 124 may include various types of insulating materials. For example, silicon oxide, silicon nitride, or silicon oxynitride may be included in the gate insulating layer 124 .

A voltage for turning on/off the semiconductor layer 123 , for example, the same or different voltages, may be selectively applied to each of the plurality of gate electrodes 131 .

The variable resistance memory device 100 as shown may have a structure in which a plurality of memory cells MC are arrayed, wherein each of the memory cells MC may have a form in which a transistor and a variable resistance are connected in parallel, as in the equivalent or corresponding circuit of FIG. 2 shown in .

The operation of the variable resistance memory device 100 is described with reference to FIG. 3 .

In order to select a memory cell, for example, to select a memory cell for reading, the control logic (not shown) may perform a control operation to apply the turn-off voltage OFF to the gate electrode 131 of the specific memory cell MC2 and to the remaining memory cells MC1 and On-voltage ON is applied to the gate electrode 131 of MC3. The turn-off voltage OFF may be configured to turn off the transistor and control current not to flow through the semiconductor layer 123 of the transistor included in the selected memory cell MC2. The turn-on voltage ON may be configured to turn on the transistors and control the flow of current through the semiconductor layer 123 of the transistors included in the unselected memory cells MC1 and MC3. Therefore, the semiconductor layer 123 corresponding to the selected memory cell MC2 may have insulating properties, and the semiconductor layer 123 corresponding to the unselected memory cells MC1 and MC3 may have conductive properties.

The turn-off voltage OFF and the turn-on voltage ON may change according to one or more types, thicknesses, and the like of materials included in the resistance change layer 122 , the semiconductor layer 123 , the gate insulating layer 124 , and the gate electrode 131 . For example, when the turn-off voltage OFF is a negative voltage, the turn-off voltage OFF may be greater than or equal to about -10V and less than or equal to about -2V. When the turn-on voltage ON is a positive voltage, the turn-on voltage ON may be greater than about 0V and less than or equal to about 10V. The same value of on-voltage ON may be applied to unselected memory cells MC1 and MC3, or different values of on-voltage ON may be applied to unselected memory cells MC1 and MC3.

In the writing operation, when a writing voltage is applied between the source electrode S and the drain electrode D, a current path (path) may be formed as shown by arrow A, so that the resistance of the resistance change layer 122 may be changed. By using this principle, information can be stored in the resistance change layer 122 . The reason for the change in resistance of the resistance change layer 122 may be that when current flows in the resistance change layer 122, oxygen vacancies Vo and/or interstitial oxygen ions may be formed, and the oxygen vacancies may aggregate to form conductive filaments. The conductive filaments formed by oxygen vacancies may have low resistance, and therefore, the resistance of the resistance change layer 122 may vary.

In order to use the variable resistance memory device 100, it is expected that a large difference exists between the resistance in the high resistance state and the resistance in the low resistance state of the resistance change layer 122, and for this reason, it is expected that the resistance change layer 122 can easily Oxygen vacancies are formed. In particular, it is desirable that oxygen vacancies may be formed more easily in the resistance change layer 122 to prevent or Deterioration of the semiconductor layer 123 is reduced.

The resistance change layer 122 according to various example embodiments may include a metal oxide having a high oxygen deficiency rate. For example, the resistance change layer 122 may be or may include a metal oxide having an oxygen deficiency rate greater than or equal to 9 atomic %. In embodiments, the oxygen deficiency rate may be less than or equal to 25 atomic %, less than or equal to 20 atomic %, less than or equal to 18 atomic %, or less than or equal to 16.5 atomic %. The hypoxia rate can be defined by Equation 1 below.

[Equation 1]

Here, M1, M2, M3, M4, M5 and O respectively represent monovalent metal element content, divalent metal element content, trivalent metal element content, tetravalent metal element content, pentavalent metal element content and oxygen content.

A high oxygen deficiency rate may indicate that relatively few oxygen ions are present compared to metal cations, and therefore, a metal oxide with a high oxygen deficiency rate may have an increased oxygen vacancy content. When there are many oxygen vacancies in the resistance change layer 122, the resistance state of the resistance change layer can be easily changed, and therefore, the characteristics of the variable resistance memory device 100 can be improved. Alternatively or additionally, when many oxygen vacancies are present, the conductive filaments may be formed more easily when a voltage is applied, and therefore, the formation voltage may be reduced so that the operating voltage of the variable resistance memory device 100 is reduced.

The resistance change layer 122 according to various example embodiments may include a binary metal oxide having an oxygen deficiency rate greater than or equal to 9% or a ternary metal oxide having an oxygen deficiency rate greater than or equal to 9%.

The binary metal oxide included in the resistance change layer 122 may include at least one of TaOx, TiOx, SnOx, CrOx, and MnOx.

The resistance change layer 122 may be or include a ternary metal oxide, and may include first and second metal elements that are different from each other, and an oxygen element. In the metal oxide, the content of the first metal element may be greater than the content of the second metal element. For example, the content of the first metal element may be greater than or equal to 50 atomic % relative to the total metal in the resistance change layer 122 , and the content of the second metal element may be greater than or equal to 50 atomic % relative to the total metal in the resistance change layer 122 . Less than or equal to 35 atomic%. The first metal element may include one of Ta, Ti, Sn, Cr, and Mn, and the second metal element may include one of Hf, Al, Nb, La, Zr, Sc, W, V, and Mo. species or at least one.

Alternatively or additionally, the resistance change layer 122 may be or may include a ternary metal oxide, and may include a metal element, a silicon element, and an oxygen element. In the resistance change layer 122, the content of the metal element may be greater than the content of the silicon element. The content of the metal element may be greater than or equal to 50 atomic % relative to the sum of the metal element and the silicon element in the resistance change layer 122 , and relative to the sum of the metal element and the silicon element in the resistance change layer 122 , the content of the silicon element may be less than or equal to 35 atomic %. The metal element may include one or at least one of Ta, Ti, Sn, Cr, and Mn.

Alternatively or additionally, the resistance change layer 122 may include a first metal oxide having an oxygen deficiency rate greater than or equal to 9% and a second metal oxide having an oxygen deficiency rate less than 9%. The content of the first metal oxide may be greater than the content of the second metal oxide. The metal content of the first metal oxide may be greater than or equal to 50 atomic % with respect to the total metal content of the resistance change layer 122 , and the metal content of the second metal oxide may be greater than or equal to 50 atomic % with respect to the total metal content of the resistance change layer 122 . The content may be less than or equal to 35 atomic %. The first metal oxide may include at least one of TaOx, TiOx, SnOx, CrOx, and MnOx. The second metal oxide may include at least one of HfOx, AlOx, SiOx, NbOx, LaOx, ZrOx, ScOx, WOx, VOx, and MoOx.

4 is a graph showing the relationship between oxygen deficiency rate and formation voltage of metal oxides according to various example embodiments. Referring to Figure 4, hafnium oxide (HfOx), which is a binary oxide, can have an oxygen deficiency rate as low as about 2.1% and can _have a formation voltage V as high as about 7.4V. HfOx is a representative variable resistance material, but has a high formation voltage, and therefore, when HfOx is applied to the variable resistance memory device 100, the semiconductor layer 123 of the variable resistance memory device 100 may deteriorate.

Tantalum oxide (TaOx) can _form with an oxygen deficiency rate as high as about 16.5% and a formation voltage V as low as about 1.65V. It is expected that when TaOx is used as a material of the resistance change layer 122 according to various example embodiments, the variable resistance memory device 100 can be realized to have a low operating voltage.

Although HfOx may not be used alone as a material of the resistance change layer 122 due to its low oxygen deficiency rate, HfOx may be used as a material of the resistance change layer 122 together with TaOx having a high oxygen deficiency rate. As shown in Figure 4, the oxygen deficiency rate and formation voltage may vary depending on the type of material included in the metal oxide. For example, while TaSiO having a silicon content of 12 atomic % may have an oxygen deficiency rate of about 12.13% and the formation voltage of TaSiO may be about 1.55 V, TaAlO having an aluminum content of 12 atomic % may have an oxygen deficiency rate of about 13.92 % and the formation voltage of TaAlO may be about 0.95V. When TaOx includes more aluminum than silicon, it is determined that the oxygen deficiency rate may increase and the formation voltage may decrease. Generally, as the oxygen starvation rate increases, the formation voltage can decrease.

When the resistance change layer 122 includes a metal oxide including a plurality of different metals, the formation voltage may change according to the content ratio of the metals. For example, when the aluminum content is 5 atomic % relative to the total metal of TaAlO, the formation voltage of TaAlO may be about 1.3 V, and when the aluminum content is 12 atomic % relative to the total metal of TaAlO, the formation voltage may be is about 0.95V. It was determined that when the aluminum content is increased, the formation voltage can be reduced. However, the formation voltage of TaAlO with an aluminum content of 35 atomic % was about 3.5 V, and therefore, it was determined that the formation voltage could increase when the aluminum content was too high.

The resistance change layer 122 according to various example embodiments may include a first metal element and a second metal element that are different from each other, and may include an oxygen deficiency rate greater than or equal to 9%. In the metal oxide, the content of the first metal element may be greater than the content of the second metal element. Alternatively, the content of the first metal element may be greater than or equal to 50 atomic % with respect to the entire metal of the resistance change layer 122 , and the content of the second metal element may be 50 atomic % with respect to the entire metal of the resistance change layer 122 . Less than or equal to 35 atomic%. The first metal element may include one or at least one of Ta, Ti, Sn, Cr, and Mn, and the second metal element may include Hf, Al, Nb, La, Zr, Sc, W, V One or at least one of , and Mo.

From another perspective, the resistance change layer 122 may have a metal oxide with a high oxygen deficiency rate as a base, and may be doped with a metal or metal oxide with a low oxygen deficiency rate to reduce the formation voltage. However, when the content of the doped metal or metal oxide is too high, the formation voltage may increase instead, and therefore, the content of the doped metal may be less than or equal to about 35 atoms relative to the total metal in the resistance change layer 122 %.

The absolute value of an operating voltage, such as a write voltage or an erase voltage, of the variable resistance memory device 100 according to various example embodiments may be less than or equal to about 4V. Alternatively, the absolute value of the write voltage or erase voltage of the variable resistance memory device 100 according to various example embodiments may be less than or equal to about 2V.

5 is a graph showing the relationship between oxygen deficiency rate and formation voltage of metal oxides according to various example embodiments. Referring to Figure 5, it can be determined that as the oxygen starvation rate increases, the formation voltage can decrease. However, the relationship between oxygen deficiency rate and formation voltage may be approximately inversely proportional and may not be completely inversely proportional. The type and/or content of the metal oxide of the resistance change layer 122 may be appropriately adjusted to reduce the formation voltage.

The oxygen deficiency rate of the metal oxide may be related to the difference in oxygen formation energy between multiple metal oxides of the same metal with different valences.

6 is a graph showing the relationship between oxygen formation energy and oxygen deficiency rate of metal oxides according to various example embodiments. Referring to FIG. 6 , the difference in oxygen formation energy between multiple tantalum oxides with different atomic valences, such as Ta ₂ O ₅ and TaO ₂ , may be about 4.42 kJ/mol, which is relatively small. However, the oxygen deficiency rate of the various tantalum oxides may be about 16.5%, which is relatively large. However, although the difference in oxygen formation energy between aluminum oxides is about 123.79 kJ/mol, which is relatively large, the oxygen deficiency rate of the aluminum oxides may be about 2.1%, which is relatively small. It can be determined that the difference in oxygen formation energy between metal oxides can be inversely proportional to the oxygen deficiency rate.

Although the oxygen deficiency rate of AlOx and that of HfOx are both about 2.1%, the difference in the oxygen formation energy with respect to AlOx is about 123.79 kJ/mol, which is larger than the difference with respect to the oxygen formation energy of HfOx, which is 34.38 kJ/mol. mol). For example, even when the oxygen deficiency rates may be the same as each other, the differences in oxygen formation energies may be different from each other. Accordingly, according to various example embodiments, a metal oxide having a difference in oxygen formation energy greater than or equal to about 10 kJ/mol may be used as the matrix of the resistance change layer 122 and having a difference in oxygen formation energy less than about 10 kJ/mol. The metal oxide or metal may be used as a dopant of the resistance change layer 122 .

7 is a graph showing differences in oxygen formation energies for various metal oxides, according to various example embodiments. Referring to Figure 7, the difference in oxygen formation energies for MnOx, TiOx, SnOx, and CrOx may be less than 10 kJ/mol. MnOx, TiOx, SnOx, and CrOx may be used as dopants of the resistance change layer 122 according to various example embodiments.

The difference in oxygen formation energies for MoOx, VOx, ScOx, WOx, NbOx, LaOx, and ZrOx may be greater than or equal to 10 kJ/mol. MoOx, VOx, ScOx, WOx, NbOx, LaOx, and ZrOx may be used as the matrix of the resistance change layer 122 according to various example embodiments.

8A is a graph showing the current-voltage (IV) characteristics of the variable resistance memory device using HfOx as the resistance change layer, and FIG. 8B is a graph showing the IV characteristics of the variable resistance memory device using TaOx as the resistance change layer. The variable resistance memory device including HfOx may have an absolute value of a forming voltage of about 7V to about 8V, as shown in FIG. 8A. As mentioned above, the oxygen deficiency rate of HfOx can be relatively low, about 2.1%.

The variable resistance memory device including TaOx may have an absolute value of the formation voltage less than about 2V, as shown in FIG. 8B. As mentioned above, the oxygen deficiency rate of TaOx can be relatively high, about 16.5%. This may indicate that as the oxygen deficiency rate increases, more oxygen vacancies may be formed in the resistance change layer 122, and therefore, the conductive filaments may be easily formed at a low operating voltage.

FIG. 9 is a structural diagram of a variable resistance memory device 100a according to various example embodiments, and FIG. 10 is a circuit diagram of the variable resistance memory device 100a of FIG. 9 .

The variable resistance memory device 100a according to various example embodiments may correspond to a vertical NAND (VNAND) memory in which a plurality of memory cells MC including a variable resistance material are vertically arrayed.

Referring to FIG. 9 , a plurality of cell strings CS may be formed on a substrate 101 .

The substrate 101 may include silicon material doped with first type impurities. For example, the substrate 101 may include silicon material doped with p-type impurities. For example, substrate 101 may include a p-type well (eg, a pocket p-well). Hereinafter, it is assumed that the substrate 101 includes p-type silicon. However, the substrate 101 is not limited to p-type silicon.

A doped region 110 as a source region may be provided on the substrate 101 . The doped region 110 may include a different n-type region than the substrate 101 . Hereinafter, it is assumed that the doped region 110 includes an n-type region. However, the doped region 110 is not limited to n-type regions. The doped region 110 may be connected to the common source line CSL.

For k and n integers, k*n cell strings CS may be provided as shown in the equivalent circuit diagram of FIG. 10 and may be arranged in a matrix form. According to the positions of columns and rows, the cell string CS can be called CSij (1≤i≤k, 1≤j≤n). Each cell string CSij may be connected to a bit line BL, a string select line SSL, a word line WL, and a common source line CSL.

Each cell string CSij may include a memory cell MC and a string selection transistor SST. The memory cells MC and the string selection transistors SST of each cell string CSij can be stacked in the height direction.

Rows of multiple cell strings CS may be respectively connected to different string selection lines SSL1 to SSLk. For example, the string selection transistors SST of the cell strings CS11 to CS1n may be commonly connected to the string selection line SSL1. The string selection transistors SST of the cell strings CSk1 to CSkn may be commonly connected to the string selection line SSLk.

The columns of the plurality of cell strings CS may be connected to different bit lines BL1 to BLn respectively. For example, the memory cells MC and the string selection transistor SST of the cell strings CS11 to CSk1 may be commonly connected to the bit line BL1, and the memory cells MC and the string selection transistor SST of the cell strings CS1n to CSkn may be commonly connected to the bit line BLn.

Rows of multiple cell strings CS may be respectively connected to different common source lines CSL1 to CSLk. For example, the string selection transistors SST of the cell strings CS11 to CS1n may be commonly connected to the common source line CSL1, and the string selection transistors SST of the cell strings CSk1 to CSkn may be commonly connected to the common source line CSLk.

The gate electrodes 131 of the memory cells MC disposed at the same height from the substrate 101 or the string selection transistor SST may be commonly connected to one word line WL. In addition, the gate electrodes 131 of the memory cells MC arranged at different heights from the substrate 101 or the string selection transistor SST may be connected to different word lines WL1 to WLn respectively.

The circuit structure shown is an example. For example, the number of rows of cell strings CS may be increased or decreased. When the number of rows of cell strings CS is changed, the number of string selection lines connected to the rows of cell strings CS and the number of cell strings CS connected to one bit line may also be changed. When the number of rows of cell strings CS changes, the number of common source lines connected to the rows of cell strings CS may also change.

The number of columns of the cell string CS may also be increased or decreased and is not limited to FIG. 9 . When the number of columns of cell strings CS is changed, the number of bit lines connected to the columns of cell strings CS and the number of cell strings CS connected to one string selection line may also be changed.

The height of the cell string CS may also be increased or decreased and is not limited to FIG. 9 . For example, the number of memory cells MC stacked in each of the cell strings CS may be increased or decreased. When the number of memory cells MC stacked in each cell string CS changes, the number of word lines WL may also change. For example, the number of memory cells MC included in each cell string CS may be increased. When the number of string selection transistors included in each cell string CS changes, the number of string selection lines or common source lines may also change. When the number of string selection transistors SST is increased, the string selection transistors SST may be stacked in the same shape as that of the memory cells MC.

For example, a write operation and a read operation can be performed on each row of the cell string CS. The cell string CS can be selected for each row through the common source line CSL, and the cell string CS can be selected for each row through the string selection line SSL. In addition, the voltage may be applied to the common source line CSL in units of at least two common source lines. The voltage may be applied to the common source line CSL in units of all the common source lines CSL.

Write operations and read operations can be performed on each page in the selected row of the cell string CS. One page may correspond to one row of memory cells connected to one word line WL. In the selected row of cell string CS, memory cells can be selected for each page via word line WL.

As shown in FIG. 9 , the cell string CS may include a channel hole CH having a cylindrical shape and a plurality of gate electrodes 131 and a plurality of insulating elements 132 surrounding the channel hole CH in a ring shape. A plurality of insulating elements 132 may be provided to insulate between the plurality of gate electrodes 131 . The plurality of gate electrodes 131 and the plurality of insulating elements 132 may be alternately stacked in the vertical direction (z direction). The channel hole CH having a cylindrical shape may include an insulating pillar 121 having a cylindrical shape extending in a vertical direction and a resistance change layer 122 having a shape sequentially surrounding the insulating pillar 121 in a cylindrical shell shape, a semiconductor layer 123 and a gate electrode. Insulating layer 124.

The gate electrode 131 may include a metal material, and/or a silicon material doped with a high concentration. Each gate electrode 131 may be connected to any one of the word line WL and the string selection line SSL.

Insulating element 132 may include one or more of a variety of insulating materials such as silicon oxide, silicon nitride, and the like.

The channel hole CH may include a plurality of layers. The outermost layer of the channel hole CH may be the gate insulating layer 124 . For example, the gate insulating layer 124 may include one or more of a variety of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and the like. The gate insulation layer 124 may be conformally deposited on the channel hole CH.

Semiconductor layer 123 may be conformally deposited along the inner surface of gate insulating layer 124 . The semiconductor layer 123 may include a semiconductor material doped with a first type material. Semiconductor layer 123 may include silicon material doped with the same type of material as substrate 101 . For example, when the substrate 101 includes p-type doped silicon material, the semiconductor layer 123 may also include p-type doped silicon material. Alternatively or additionally, the semiconductor layer 123 may include one or more materials such as Ge, IGZO, GaAs, and the like.

The resistance change layer 122 may be arranged along the inner surface of the semiconductor layer 123 . The resistance change layer 122 may be disposed in contact with the semiconductor layer 123 and may be conformally deposited on the semiconductor layer 123 .

The resistance change layer 122 may change to a high resistance state or a low resistance state according to an applied voltage, and may include a metal oxide having a high oxygen deficiency rate.

The resistance change layer 122 may have substantially the same materials and characteristics as the resistance change layer 122 described above. The resistance change layer 122 may include a binary metal oxide having an oxygen deficiency rate greater than or equal to 9% or a ternary metal oxide having an oxygen deficiency rate greater than or equal to 9%.

The binary metal oxide included in the resistance change layer 122 may be or include at least one of TaOx, TiOx, SnOx, CrOx, and MnOx.

The ternary metal oxide included in the resistance change layer 122 may include a first metal element and a second metal element that are different from each other, and an oxygen element. In the metal oxide, the content of the first metal element may be greater than the content of the second metal element. For example, the content of the first metal element may be greater than or equal to 50 atomic % relative to the total metal in the resistance change layer 122 , and the content of the second metal element may be greater than or equal to 50 atomic % relative to the total metal in the resistance change layer 122 . Less than or equal to 35 atomic%. The first metal element may include one or at least one of Ta, Ti, Sn, Cr, and Mn, and the second metal element may include Hf, Al, Nb, La, Zr, Sc, W, V One or at least one of , and Mo.

In the resistance change layer 122, the content of the metal element may be greater than the content of the silicon element. The content of the metal element may be greater than or equal to 50 atomic % relative to the sum of the metal element and the silicon element in the resistance change layer 122 , and relative to the sum of the metal element and the silicon element in the resistance change layer 122 , the content of silicon element may be less than or equal to 35 atomic %. The metal element may include one or at least one of Ta, Ti, Sn, Cr, and Mn.

Alternatively, the resistance change layer 122 may include a first metal oxide having an oxygen deficiency rate greater than or equal to 9% and a second metal oxide having an oxygen deficiency rate less than 9%. The content of the first metal oxide may be greater than the content of the second metal oxide. The metal content of the first metal oxide may be greater than or equal to 50 atomic % with respect to the total metal content of the resistance change layer 122 , and the metal content of the second metal oxide may be greater than or equal to 50 atomic % with respect to the total metal content of the resistance change layer 122 . The content may be less than or equal to 35 atomic %. The first metal oxide may be or include at least one of TaOx, TiOx, SnOx, CrOx, and MnOx. The second metal oxide may be or include at least one of HfOx, AlOx, SiOx, NbOx, LaOx, ZrOx, ScOx, WOx, VOx, and MoOx.

The variable resistance memory device 100a may include the resistance change layer 122 in which oxygen vacancies may be easily formed, and therefore, the difference between the resistance value in the high resistance state and the resistance value in the low resistance state may be increased, and low resistance may be achieved. setting voltage and low reset voltage characteristics.

Insulating pillars 121 may be deposited along the inner surface of resistance change layer 122 . The insulating pillar 121 may fill the innermost space of the channel hole CH.

The resistance change layer 122 and the semiconductor layer 123 may contact the doped region 110, that is, the common source region.

The drain region 140 may be disposed in the channel hole CH of the cell string CS. Drain region 140 may include a second type doped silicon material. For example, drain region 140 may include silicon material doped with n-type material.

Bit line 150 may be provided on drain region 140. The drain region 140 and the bit line 150 may be connected to each other via contact plugs.

Each gate electrode 131 and the gate insulating layer 124, the semiconductor layer 123, and the resistance change layer 122 facing the gate electrode 131 in the horizontal direction (x direction) may form a memory cell MC. For example, the memory cell MC may have a circuit structure in which transistors including the gate electrode 131, the gate insulating layer 124, and the semiconductor layer 123 are connected in parallel with variable resistance due to the resistance change layer 122.

The parallel connection structures may be continuously arranged in the vertical direction (z direction) to form the cell string CS. In addition, both ends of the cell string CS may be connected to the common source line CSL and the bit line BL, as shown in the circuit diagram of FIG. 10 . By applying voltages to the common source line CSL and the bit line BL, programming, reading, and erasing can be performed on the plurality of memory cells MC.

For example, when the memory cell MC for which the programming operation is to be performed is selected, the gate voltage value of the selected cell may be adjusted so that the selected cell is in the channel off state, and the gate voltage of the unselected cell may be adjusted value, so that the unselected cells are in the channel conduction state. Therefore, a current path due to the voltage applied to the common source line CSL and the bit line BL may pass through the region of the resistance change layer 122 of the selected memory cell MC. Here, the applied voltage can be set to VSET or VRESET to form LRS (low resistance state) or HRS (high resistance state) in the selected memory cell MC as desired and write logic "1" or logic " 0" data.

Regarding the read operation, the read can be performed on the selected unit according to a similar method. For example, the gate voltage applied to each gate electrode 131 may be adjusted so that the selected memory cell MC is in a channel-off state and the unselected memory cell MC is in a channel-on state. Then, the current flowing through the corresponding cell MC due to the applied voltage V read between the common source line CSL and the bit line BL may be measured to determine the cell state, such as logic "1" or logic "0".

As described above, according to the variable resistance memory device 100a according to various example embodiments, the memory cell MC may be formed by using the resistance change layer 122 including a material for easily forming an oxygen vacancy-based conductive filament, and the memory cell MC The memory devices may be formed in arrays. Therefore, the resistance change layer 122 may be formed to have a reduced thickness and the variable resistance memory device 100 a may have a low operating voltage compared to other structures such as a phase change material-based memory device or a charge trapping-based memory device. For example, the variable resistance memory device 100a may have an operating voltage, such as a write voltage or an erase voltage, whose absolute value is less than or equal to about 4V. Alternatively, the variable resistance memory device 100a may have an operating voltage, such as a write voltage or an erase voltage, whose absolute value is less than or equal to about 2V.

In the VNAND structure, due to packaging characteristics or restrictions according to the height of the cell string CS, there is a limit on increasing the number of gate electrodes 131 included in the cell string CS. Furthermore, in the case of a charge trapping based memory device, there may be a limitation on reducing the distance between adjacent gate electrodes 131 due to interference. For example, it may be difficult to reduce the pitch of gate electrodes adjacent to each other in the vertical direction (z direction) to less than or equal to about 38 nm, and therefore, there is a limit on storage capacity.

The variable resistance memory device 100a according to various example embodiments may use the above-described resistance change layer 122, and therefore, the pitch between the gate electrodes 131, such as gate electrodes 131 that may be arranged in a periodic manner, may be reduced or minimized. The electrodes 131 have a pitch of at least three. According to various example embodiments, the pitch may be reduced to less than or equal to 20 nm, such as about 15 nm, and in this case, the storage capacity may be increased by a factor of two or more.

Based on this structure, the variable resistance memory device 100a can solve or at least partially solve the problem of scaling between memory cells in next-generation VNAND memory to increase density and/or achieve low power consumption.

11 is a diagram of a portion of a variable resistance memory device 100b including a plurality of resistance change layers 122a, according to various example embodiments. Referring to FIGS. 9 and 11, the variable resistance memory device 100b of FIG. 11 may include a plurality of resistance change layers 122a. For example, the resistance change layer 122a may include a first resistance change layer RS1 and a second resistance change layer RS2 sequentially arranged in a direction away from the semiconductor layer 123.

At least one of the first and second resistance change layers RS1 and RS2 may include a metal oxide having an oxygen deficiency rate greater than or equal to 9%. For example, the first resistance change layer RS1 may include a first metal oxide having an oxygen deficiency rate greater than or equal to 9% as a base and may be doped with a second metal oxide having an oxygen deficiency rate less than 9%. The oxygen deficiency rate of the first metal oxide included in the first resistance change layer RS1 may be greater than the oxygen deficiency rate of the first metal oxide included in the second resistance change layer RS2. Oxygen vacancies may be easily or more easily formed in the first resistance change layer RS1 adjacent to the semiconductor layer 123, and therefore, the operating voltage of the variable resistance memory device 100 may be reduced.

12 is a diagram of a portion of a variable resistance memory device 100c further including an oxide layer 125, according to various example embodiments. Referring to FIGS. 9 and 12 , the variable resistance memory device 100 c of FIG. 12 may further include an oxide layer 125 between the semiconductor layer 123 and the resistance change layer 122 . The oxide layer 125 may include silicon oxide, but is not limited thereto. In a device implementing the variable resistance memory device 100c, the oxide layer 125 may include an oxide of a material contacting the oxide layer 125, for example, an oxide of a material included in the semiconductor layer 123. The thickness of the oxide layer 125 may be smaller than the thickness of the resistance change layer 122 . For example, the thickness of oxide layer 125 may be less than or equal to about 5 nm.

13 is a diagram of a variable resistance memory device 100d including conductive pillars 126, according to various example embodiments. To compare FIG. 9 with FIG. 13, the variable resistance memory device 100d of FIG. 13 may include conductive pillars 126 instead of insulating pillars.

The conductive pillars 126 may contact the resistance change layer 122 . Conductive pillars 126 may be conformally deposited on resistance change layer 122 . Conductive pillars 126 may include materials with improved or superior electrical conductivity properties. For example, the conductive pillar 126 may include at least one of W, Ti, TiN, Ru, RuO ₂ , Ta, and TaN. The conductive pillar 126 may include the same material as the gate electrode 131 .

The entire area of the conductive pillar 126 may be spatially separated from the entire area of the semiconductor layer 123 by the resistance change layer 122 . Since the conductive pillar 126 is electrically insulated from the semiconductor layer 123, a voltage can be applied separately to the conductive pillar 126 and the semiconductor layer 123.

The variable resistance memory device 100d may further include a first bit line (not shown) electrically connected to the conductive pillar 126 and providing a voltage to the conductive pillar 126 and electrically insulated from the first bit line and electrically connected to the semiconductor layer 123 and A second bit line (not shown) provides voltage to the semiconductor layer 123 .

When variable resistance memory device 100d is operating, voltage may also be applied to conductive pillars 126. The voltage applied to the conductive pillar 126 may be greater than the gate voltage of the selected memory cell (which is the turn-off voltage), and may be greater than or equal to the voltage applied to the semiconductor layer 123 . Therefore, a horizontal electric field toward the semiconductor layer 123 may be formed in the resistance change layer 122 corresponding to the selected memory cell. Oxygen vacancies in the resistance change layer 122 corresponding to the selected memory cell may be concentrated in a region of the resistance change layer 122 adjacent to the semiconductor layer 123, and therefore, conductive threads may be formed relatively easily.

14 is a schematic block diagram of an electronic device 200 including a variable resistance memory device, according to various example implementations.

Referring to FIG. 14 , an electronic device 200 according to various example embodiments may be one of the following: a personal digital assistant (PDA), a laptop computer, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a wired Or wireless electronic equipment, or composite electronic equipment including at least two of them. Electronic device 200 may include a controller 220 connected to each other via bus 210 , input and output devices 230 such as one or more of a keypad, a keyboard, and a display, memory 240 , and a wireless interface 250 .

Controller 220 may include, for example, one or more of a microprocessor, digital signal processor, microcontroller, or similar components. Memory 240 may be used, for example, to store instructions for execution by controller 220.

Memory 240 may be used to store user data. Memory 240 may include at least one variable resistance memory device according to various example implementations.

Electronic device 200 may use wireless interface 250 to transmit data to or receive data from a wireless communication network that performs communication via radio frequency (RF) signals. For example, wireless interface 250 may include an antenna, a wireless transceiver, or the like. Electronic device 200 may be used in one or more of communication interface protocols such as third generation (3G) communication systems such as CDMA, GSM, NADC, E-TDMA, WCDMA, and CDMA2000.

15 is a schematic block diagram of a memory system 300 including a variable resistance memory device, according to various example implementations.

Referring to FIG. 15 , variable resistance memory devices according to various example embodiments may be used to implement memory system 300 . The storage system 300 may include a memory 310 that stores a large amount of data and a memory controller 320. The memory controller 320 may control the memory 310 so that data stored in the memory 310 may be read or written in response to a read/write request from the host 330 . Memory controller 320 may configure host 330 with an address mapping table, for example, for mapping addresses provided from a mobile device or computer system into physical addresses of memory 310 . Memory 310 may include at least one semiconductor memory device according to various example implementations.

Variable resistance memory devices according to various example embodiments described above may be implemented in the form of chips and may be used as neuromorphic computing platforms.

Figure 16 is a schematic diagram of a neuromorphic device 400 including a memory device, according to various example implementations. Referring to Figure 16, neuromorphic device 400 may include processing circuitry 410 and/or memory 420. Memory 420 of neuromorphic device 400 may include a storage system according to various example implementations.

Processing circuitry 410 may be configured to control functions for driving neuromorphic device 400 . For example, processing circuitry 410 may be configured to control neuromorphic device 400 by executing a program stored in memory 420 of neuromorphic device 400 .

Processing circuitry 410 may include hardware such as logic circuitry; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processor may include, but is not limited to, one or more of the following: a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 400, an arithmetic logic unit (ALU), digital signal processor, microcomputer, field programmable gate array (FPGA), system on chip (SoC), programmable logic unit, microprocessor, application specific integrated circuit (ASIC), etc.

Processing circuitry 410 may be configured to read various data from/write various data in external device 430 and/or execute neuromorphic device 400 by using the read/written data. External device 430 may include external memory and/or sensor arrays having image sensors (eg, CMOS image sensor circuits).

The neuromorphic device 400 in Figure 16 can be applied to machine learning systems. The machine learning system may utilize various artificial neural network organizations and processing models, such as one or more of: convolutional neural networks (CNN), deconvolutional neural networks, optionally including long short-term memory (LSTM) Recurrent Neural Networks (RNN), Stacked Neural Networks (SNN), State Space Dynamic Neural Networks (SSDNN), Deep Belief Networks (DBN), Generative Adversarial Networks (GAN), and/or Restricted Boltzmann Machine (RBM).

Such machine learning systems may include other forms of machine learning models such as linear and/or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and/or combinations thereof, Includes ensembles such as random forests. Such machine learning models can be used to provide a variety of services, such as image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance systems (ADAS) services, voice assistant services, automatic speech recognition (ASR) ) services, etc., and can be installed and implemented by other electronic devices.

The variable resistance memory device according to various example embodiments operates even when a voltage of relatively small absolute value is applied thereto.

Alternatively or additionally, variable resistance memory devices according to various example embodiments may be advantageous for achieving lower power consumption and/or higher integration.

It should be understood that the various example embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, and example embodiments are not necessarily mutually exclusive.

Any of the elements and/or functional blocks disclosed above may include or be implemented in: processing circuitry such as hardware including logic circuitry; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuit system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip ( SoC), programmable logic unit, microprocessor, application specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of a transistor, a resistor, a capacitor, and the like. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, and the like.

When "about" or "substantially" is used in this specification with respect to a numerical value, it is intended that the relevant numerical value includes manufacturing or operating tolerances (eg, ±10%) surrounding the stated numerical value. Furthermore, when the words "substantially" and "substantially" are used with respect to a geometric shape, it is intended that the exactness of the geometric shape is not required, but that the tolerances of the shape are within the scope of the disclosure. Furthermore, when the words "substantially" and "substantially" are used with respect to a composition of material, it is intended that the exact nature of the material is not required, but that the tolerance of the material is within the scope of the disclosure.

Furthermore, regardless of whether a numerical value or shape is modified as "about" or "substantially," it will be understood that these values and shapes are to be interpreted as including manufacturing or operating tolerances (e.g., ±10%) surrounding the stated numerical value or shape. . Thus, although the terms "same," "the same," or "equal" are used in descriptions of example embodiments, it is to be understood that some imprecision may exist. Therefore, when an element or a value is referred to as being the same or equal to another value, it will be understood that the one element or value is the same as the other element within expected manufacturing or operating tolerances (e.g., ±10%). One component or another has the same value.

Although one or more example embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various modifications may be made therein without departing from the spirit and scope as defined by the appended claims. Many variations in details. Additionally, example implementations are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.

Claims (20)

1. Variable resistance memory devices, including: A resistance change layer comprising a metal oxide including a first metal element and optionally a second metal element, the metal oxide having an oxygen deficiency rate greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and A plurality of gate electrodes spaced apart from each other on the gate insulating layer. 2. The variable resistance memory device of claim 1, wherein the content of the first metal element is greater than or equal to about 50 atomic % with respect to all metals of the resistance change layer. 3. The variable resistance memory device of claim 1, wherein a content of the second metal element is less than or equal to about 35 atomic % relative to all metals of the resistance change layer. 4. The variable resistance memory device of claim 1, wherein the first metal element includes at least one of Ta, Ti, Sn, Cr, and Mn. 5. The variable resistance memory device of claim 1, wherein the second metal element includes at least one of Hf, Al, Nb, La, Zr, Sc, W, V, and Mo. 6. The variable resistance memory device of claim 1, wherein the resistance change layer further includes Si. 7. The variable resistance memory device of claim 1, wherein the semiconductor layer is configured to receive a write voltage applied thereto having an absolute value less than or equal to about 4V. 8. The variable resistance memory device of claim 1, further comprising: An oxide layer between the semiconductor layer and the resistance change layer. 9. The variable resistance memory device of claim 8, wherein the thickness of the oxide layer is smaller than the thickness of the resistance change layer. 10. The variable resistance memory device of claim 1, wherein The resistance change layer includes a first resistance change layer and a second resistance change layer sequentially arranged in a direction away from the semiconductor layer; and The oxygen deficiency rate of the first resistance change layer is greater than the oxygen deficiency rate of the second resistance change layer. 11. The variable resistance memory device of claim 1, wherein At least three of the plurality of gate electrodes are periodically arranged, and a pitch of the at least three of the plurality of gate electrodes is less than or equal to about 20 nm. 12. The variable resistance memory device of claim 1, further comprising: column, wherein the resistance change layer, the semiconductor layer, and the gate insulating layer sequentially surround the pillar in a shell shape, and The plurality of gate electrodes and insulating elements surround the gate insulating layer in a shell shape. 13. The variable resistance memory device of claim 12, wherein the pillars comprise insulating material. 14. The variable resistance memory device of claim 12, wherein the pillars comprise conductive material. 15. The variable resistance memory device of claim 14, wherein the pillar is configured to receive a voltage greater than or equal to a voltage applied to the semiconductor layer. 16. Variable resistance memory devices, including: A resistance change layer comprising a metal oxide having an oxygen deficiency rate greater than or equal to about 9% and including silicon; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and A plurality of gate electrodes spaced apart from each other on the gate insulating layer. 17. The variable resistance memory device of claim 16, wherein the resistance change layer includes at least one of Ta, Ti, Sn, Cr, and Mn. 18. The variable resistance memory device of claim 16, wherein the silicon content is less than or equal to about 35 atomic % relative to the sum of metal and silicon of the resistance change layer. 19. Variable resistance memory devices, including: A resistance change layer comprising a first metal oxide having an oxygen deficiency rate greater than or equal to about 9% and a second metal oxide having an oxygen deficiency rate less than 9%, wherein the content of the first metal oxide is greater than The content of the second metal oxide; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and A plurality of gate electrodes spaced apart from each other on the gate insulating layer. 20. The variable resistance memory device of claim 19, wherein the content of the metal included in the second metal oxide is less than or equal to about 35 atomic % with respect to the total metal included in the resistance change layer.